xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-load-compare-store.ll (revision 34d88cf6cfe9f878e6330f157f178c2b104c3949) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64 -mattr=+sve < %s | FileCheck %s
3
4define void @sve_load_compare_store(ptr noalias nocapture noundef readonly %a, ptr noalias nocapture noundef %b) {
5; CHECK-LABEL: sve_load_compare_store:
6; CHECK:       // %bb.0: // %entry
7; CHECK-NEXT:    ptrue p0.b
8; CHECK-NEXT:    ld1h { z0.s }, p0/z, [x0]
9; CHECK-NEXT:    cmphs p0.s, p0/z, z0.s, #0
10; CHECK-NEXT:    st1b { z0.s }, p0, [x1]
11; CHECK-NEXT:    ret
12entry:
13  %0 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
14  %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
15  %2 = tail call <vscale x 4 x i16> @llvm.masked.load.nxv4i16.p0(ptr %a, i32 1, <vscale x 4 x i1> %1, <vscale x 4 x i16> zeroinitializer)
16  %3 = zext <vscale x 4 x i16> %2 to <vscale x 4 x i32>
17  %4 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.nxv4i32(<vscale x 4 x i1> %1, <vscale x 4 x i32> %3, <vscale x 4 x i32> zeroinitializer)
18  %5 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
19  %6 = trunc <vscale x 4 x i16> %2 to <vscale x 4 x i8>
20  tail call void @llvm.masked.store.nxv4i8.p0(<vscale x 4 x i8> %6, ptr %b, i32 1, <vscale x 4 x i1> %4)
21  ret void
22}
23
24declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 immarg)
25declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>)
26declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
27declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>)
28declare i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
29declare <vscale x 4 x i16> @llvm.masked.load.nxv4i16.p0(ptr, i32 immarg, <vscale x 4 x i1>, <vscale x 4 x i16>)
30declare void @llvm.masked.store.nxv4i8.p0(<vscale x 4 x i8>, ptr, i32 immarg, <vscale x 4 x i1>)
31