1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s 3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s 4 5; Since UQDEC{B|H|W|D|P} and UQINC{B|H|W|D|P} have identical semantics, the tests for 6; * @llvm.aarch64.sve.uqinc{b|h|w|d|p}, and 7; * @llvm.aarch64.sve.uqdec{b|h|w|d|p} 8; should also be identical (with the instruction name being adjusted). When 9; updating this file remember to make similar changes in the file testing the 10; other intrinsic. 11 12; 13; UQDECH (vector) 14; 15 16define <vscale x 8 x i16> @uqdech(<vscale x 8 x i16> %a) { 17; CHECK-LABEL: uqdech: 18; CHECK: // %bb.0: 19; CHECK-NEXT: uqdech z0.h, pow2 20; CHECK-NEXT: ret 21 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16> %a, 22 i32 0, i32 1) 23 ret <vscale x 8 x i16> %out 24} 25 26; 27; UQDECW (vector) 28; 29 30define <vscale x 4 x i32> @uqdecw(<vscale x 4 x i32> %a) { 31; CHECK-LABEL: uqdecw: 32; CHECK: // %bb.0: 33; CHECK-NEXT: uqdecw z0.s, vl1, mul #2 34; CHECK-NEXT: ret 35 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqdecw.nxv4i32(<vscale x 4 x i32> %a, 36 i32 1, i32 2) 37 ret <vscale x 4 x i32> %out 38} 39 40; 41; UQDECD (vector) 42; 43 44define <vscale x 2 x i64> @uqdecd(<vscale x 2 x i64> %a) { 45; CHECK-LABEL: uqdecd: 46; CHECK: // %bb.0: 47; CHECK-NEXT: uqdecd z0.d, vl2, mul #3 48; CHECK-NEXT: ret 49 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqdecd.nxv2i64(<vscale x 2 x i64> %a, 50 i32 2, i32 3) 51 ret <vscale x 2 x i64> %out 52} 53 54; 55; UQDECP (vector) 56; 57 58define <vscale x 8 x i16> @uqdecp_b16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %b) { 59; CHECK-LABEL: uqdecp_b16: 60; CHECK: // %bb.0: 61; CHECK-NEXT: uqdecp z0.h, p0.h 62; CHECK-NEXT: ret 63 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqdecp.nxv8i16(<vscale x 8 x i16> %a, 64 <vscale x 8 x i1> %b) 65 ret <vscale x 8 x i16> %out 66} 67 68define <vscale x 4 x i32> @uqdecp_b32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %b) { 69; CHECK-LABEL: uqdecp_b32: 70; CHECK: // %bb.0: 71; CHECK-NEXT: uqdecp z0.s, p0.s 72; CHECK-NEXT: ret 73 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqdecp.nxv4i32(<vscale x 4 x i32> %a, 74 <vscale x 4 x i1> %b) 75 ret <vscale x 4 x i32> %out 76} 77 78define <vscale x 2 x i64> @uqdecp_b64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %b) { 79; CHECK-LABEL: uqdecp_b64: 80; CHECK: // %bb.0: 81; CHECK-NEXT: uqdecp z0.d, p0.d 82; CHECK-NEXT: ret 83 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqdecp.nxv2i64(<vscale x 2 x i64> %a, 84 <vscale x 2 x i1> %b) 85 ret <vscale x 2 x i64> %out 86} 87 88; 89; UQDECB (scalar) 90; 91 92define i32 @uqdecb_n32(i32 %a) { 93; CHECK-LABEL: uqdecb_n32: 94; CHECK: // %bb.0: 95; CHECK-NEXT: uqdecb w0, vl3, mul #4 96; CHECK-NEXT: ret 97 %out = call i32 @llvm.aarch64.sve.uqdecb.n32(i32 %a, i32 3, i32 4) 98 ret i32 %out 99} 100 101define i64 @uqdecb_n64(i64 %a) { 102; CHECK-LABEL: uqdecb_n64: 103; CHECK: // %bb.0: 104; CHECK-NEXT: uqdecb x0, vl4, mul #5 105; CHECK-NEXT: ret 106 %out = call i64 @llvm.aarch64.sve.uqdecb.n64(i64 %a, i32 4, i32 5) 107 ret i64 %out 108} 109 110; 111; UQDECH (scalar) 112; 113 114define i32 @uqdech_n32(i32 %a) { 115; CHECK-LABEL: uqdech_n32: 116; CHECK: // %bb.0: 117; CHECK-NEXT: uqdech w0, vl5, mul #6 118; CHECK-NEXT: ret 119 %out = call i32 @llvm.aarch64.sve.uqdech.n32(i32 %a, i32 5, i32 6) 120 ret i32 %out 121} 122 123define i64 @uqdech_n64(i64 %a) { 124; CHECK-LABEL: uqdech_n64: 125; CHECK: // %bb.0: 126; CHECK-NEXT: uqdech x0, vl6, mul #7 127; CHECK-NEXT: ret 128 %out = call i64 @llvm.aarch64.sve.uqdech.n64(i64 %a, i32 6, i32 7) 129 ret i64 %out 130} 131 132; 133; UQDECW (scalar) 134; 135 136define i32 @uqdecw_n32(i32 %a) { 137; CHECK-LABEL: uqdecw_n32: 138; CHECK: // %bb.0: 139; CHECK-NEXT: uqdecw w0, vl7, mul #8 140; CHECK-NEXT: ret 141 %out = call i32 @llvm.aarch64.sve.uqdecw.n32(i32 %a, i32 7, i32 8) 142 ret i32 %out 143} 144 145define i64 @uqdecw_n64(i64 %a) { 146; CHECK-LABEL: uqdecw_n64: 147; CHECK: // %bb.0: 148; CHECK-NEXT: uqdecw x0, vl8, mul #9 149; CHECK-NEXT: ret 150 %out = call i64 @llvm.aarch64.sve.uqdecw.n64(i64 %a, i32 8, i32 9) 151 ret i64 %out 152} 153 154; 155; UQDECD (scalar) 156; 157 158define i32 @uqdecd_n32(i32 %a) { 159; CHECK-LABEL: uqdecd_n32: 160; CHECK: // %bb.0: 161; CHECK-NEXT: uqdecd w0, vl16, mul #10 162; CHECK-NEXT: ret 163 %out = call i32 @llvm.aarch64.sve.uqdecd.n32(i32 %a, i32 9, i32 10) 164 ret i32 %out 165} 166 167define i64 @uqdecd_n64(i64 %a) { 168; CHECK-LABEL: uqdecd_n64: 169; CHECK: // %bb.0: 170; CHECK-NEXT: uqdecd x0, vl32, mul #11 171; CHECK-NEXT: ret 172 %out = call i64 @llvm.aarch64.sve.uqdecd.n64(i64 %a, i32 10, i32 11) 173 ret i64 %out 174} 175 176; 177; UQDECP (scalar) 178; 179 180define i32 @uqdecp_n32_b8(i32 %a, <vscale x 16 x i1> %b) { 181; CHECK-LABEL: uqdecp_n32_b8: 182; CHECK: // %bb.0: 183; CHECK-NEXT: uqdecp w0, p0.b 184; CHECK-NEXT: ret 185 %out = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv16i1(i32 %a, <vscale x 16 x i1> %b) 186 ret i32 %out 187} 188 189define i32 @uqdecp_n32_b16(i32 %a, <vscale x 8 x i1> %b) { 190; CHECK-LABEL: uqdecp_n32_b16: 191; CHECK: // %bb.0: 192; CHECK-NEXT: uqdecp w0, p0.h 193; CHECK-NEXT: ret 194 %out = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv8i1(i32 %a, <vscale x 8 x i1> %b) 195 ret i32 %out 196} 197 198define i32 @uqdecp_n32_b32(i32 %a, <vscale x 4 x i1> %b) { 199; CHECK-LABEL: uqdecp_n32_b32: 200; CHECK: // %bb.0: 201; CHECK-NEXT: uqdecp w0, p0.s 202; CHECK-NEXT: ret 203 %out = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv4i1(i32 %a, <vscale x 4 x i1> %b) 204 ret i32 %out 205} 206 207define i32 @uqdecp_n32_b64(i32 %a, <vscale x 2 x i1> %b) { 208; CHECK-LABEL: uqdecp_n32_b64: 209; CHECK: // %bb.0: 210; CHECK-NEXT: uqdecp w0, p0.d 211; CHECK-NEXT: ret 212 %out = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv2i1(i32 %a, <vscale x 2 x i1> %b) 213 ret i32 %out 214} 215 216define i64 @uqdecp_n64_b8(i64 %a, <vscale x 16 x i1> %b) { 217; CHECK-LABEL: uqdecp_n64_b8: 218; CHECK: // %bb.0: 219; CHECK-NEXT: uqdecp x0, p0.b 220; CHECK-NEXT: ret 221 %out = call i64 @llvm.aarch64.sve.uqdecp.n64.nxv16i1(i64 %a, <vscale x 16 x i1> %b) 222 ret i64 %out 223} 224 225define i64 @uqdecp_n64_b16(i64 %a, <vscale x 8 x i1> %b) { 226; CHECK-LABEL: uqdecp_n64_b16: 227; CHECK: // %bb.0: 228; CHECK-NEXT: uqdecp x0, p0.h 229; CHECK-NEXT: ret 230 %out = call i64 @llvm.aarch64.sve.uqdecp.n64.nxv8i1(i64 %a, <vscale x 8 x i1> %b) 231 ret i64 %out 232} 233 234define i64 @uqdecp_n64_b32(i64 %a, <vscale x 4 x i1> %b) { 235; CHECK-LABEL: uqdecp_n64_b32: 236; CHECK: // %bb.0: 237; CHECK-NEXT: uqdecp x0, p0.s 238; CHECK-NEXT: ret 239 %out = call i64 @llvm.aarch64.sve.uqdecp.n64.nxv4i1(i64 %a, <vscale x 4 x i1> %b) 240 ret i64 %out 241} 242 243define i64 @uqdecp_n64_b64(i64 %a, <vscale x 2 x i1> %b) { 244; CHECK-LABEL: uqdecp_n64_b64: 245; CHECK: // %bb.0: 246; CHECK-NEXT: uqdecp x0, p0.d 247; CHECK-NEXT: ret 248 %out = call i64 @llvm.aarch64.sve.uqdecp.n64.nxv2i1(i64 %a, <vscale x 2 x i1> %b) 249 ret i64 %out 250} 251 252; uqdec{h|w|d}(vector, pattern, multiplier) 253declare <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16>, i32, i32) 254declare <vscale x 4 x i32> @llvm.aarch64.sve.uqdecw.nxv4i32(<vscale x 4 x i32>, i32, i32) 255declare <vscale x 2 x i64> @llvm.aarch64.sve.uqdecd.nxv2i64(<vscale x 2 x i64>, i32, i32) 256 257; uqdec{b|h|w|d}(scalar, pattern, multiplier) 258declare i32 @llvm.aarch64.sve.uqdecb.n32(i32, i32, i32) 259declare i64 @llvm.aarch64.sve.uqdecb.n64(i64, i32, i32) 260declare i32 @llvm.aarch64.sve.uqdech.n32(i32, i32, i32) 261declare i64 @llvm.aarch64.sve.uqdech.n64(i64, i32, i32) 262declare i32 @llvm.aarch64.sve.uqdecw.n32(i32, i32, i32) 263declare i64 @llvm.aarch64.sve.uqdecw.n64(i64, i32, i32) 264declare i32 @llvm.aarch64.sve.uqdecd.n32(i32, i32, i32) 265declare i64 @llvm.aarch64.sve.uqdecd.n64(i64, i32, i32) 266 267; uqdecp(scalar, predicate) 268declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv16i1(i32, <vscale x 16 x i1>) 269declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv8i1(i32, <vscale x 8 x i1>) 270declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv4i1(i32, <vscale x 4 x i1>) 271declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv2i1(i32, <vscale x 2 x i1>) 272 273declare i64 @llvm.aarch64.sve.uqdecp.n64.nxv16i1(i64, <vscale x 16 x i1>) 274declare i64 @llvm.aarch64.sve.uqdecp.n64.nxv8i1(i64, <vscale x 8 x i1>) 275declare i64 @llvm.aarch64.sve.uqdecp.n64.nxv4i1(i64, <vscale x 4 x i1>) 276declare i64 @llvm.aarch64.sve.uqdecp.n64.nxv2i1(i64, <vscale x 2 x i1>) 277 278; uqdecp(vector, predicate) 279declare <vscale x 8 x i16> @llvm.aarch64.sve.uqdecp.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>) 280declare <vscale x 4 x i32> @llvm.aarch64.sve.uqdecp.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>) 281declare <vscale x 2 x i64> @llvm.aarch64.sve.uqdecp.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>) 282