1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s 3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s 4 5; Since SQDEC{B|H|W|D|P} and SQINC{B|H|W|D|P} have identical semantics, the tests for 6; * @llvm.aarch64.sve.sqinc{b|h|w|d|p}, and 7; * @llvm.aarch64.sve.sqdec{b|h|w|d|p} 8; should also be identical (with the instruction name being adjusted). When 9; updating this file remember to make similar changes in the file testing the 10; other intrinsic. 11 12; 13; SQDECH (vector) 14; 15 16define <vscale x 8 x i16> @sqdech(<vscale x 8 x i16> %a) { 17; CHECK-LABEL: sqdech: 18; CHECK: // %bb.0: 19; CHECK-NEXT: sqdech z0.h, pow2 20; CHECK-NEXT: ret 21 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqdech.nxv8i16(<vscale x 8 x i16> %a, 22 i32 0, i32 1) 23 ret <vscale x 8 x i16> %out 24} 25 26; 27; SQDECW (vector) 28; 29 30define <vscale x 4 x i32> @sqdecw(<vscale x 4 x i32> %a) { 31; CHECK-LABEL: sqdecw: 32; CHECK: // %bb.0: 33; CHECK-NEXT: sqdecw z0.s, vl1, mul #2 34; CHECK-NEXT: ret 35 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdecw.nxv4i32(<vscale x 4 x i32> %a, 36 i32 1, i32 2) 37 ret <vscale x 4 x i32> %out 38} 39 40; 41; SQDECD (vector) 42; 43 44define <vscale x 2 x i64> @sqdecd(<vscale x 2 x i64> %a) { 45; CHECK-LABEL: sqdecd: 46; CHECK: // %bb.0: 47; CHECK-NEXT: sqdecd z0.d, vl2, mul #3 48; CHECK-NEXT: ret 49 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdecd.nxv2i64(<vscale x 2 x i64> %a, 50 i32 2, i32 3) 51 ret <vscale x 2 x i64> %out 52} 53 54; 55; SQDECP (vector) 56; 57 58define <vscale x 8 x i16> @sqdecp_b16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %b) { 59; CHECK-LABEL: sqdecp_b16: 60; CHECK: // %bb.0: 61; CHECK-NEXT: sqdecp z0.h, p0.h 62; CHECK-NEXT: ret 63 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqdecp.nxv8i16(<vscale x 8 x i16> %a, 64 <vscale x 8 x i1> %b) 65 ret <vscale x 8 x i16> %out 66} 67 68define <vscale x 4 x i32> @sqdecp_b32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %b) { 69; CHECK-LABEL: sqdecp_b32: 70; CHECK: // %bb.0: 71; CHECK-NEXT: sqdecp z0.s, p0.s 72; CHECK-NEXT: ret 73 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdecp.nxv4i32(<vscale x 4 x i32> %a, 74 <vscale x 4 x i1> %b) 75 ret <vscale x 4 x i32> %out 76} 77 78define <vscale x 2 x i64> @sqdecp_b64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %b) { 79; CHECK-LABEL: sqdecp_b64: 80; CHECK: // %bb.0: 81; CHECK-NEXT: sqdecp z0.d, p0.d 82; CHECK-NEXT: ret 83 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdecp.nxv2i64(<vscale x 2 x i64> %a, 84 <vscale x 2 x i1> %b) 85 ret <vscale x 2 x i64> %out 86} 87 88; 89; SQDECB (scalar) 90; 91 92define i32 @sqdecb_n32_i32(i32 %a) { 93; CHECK-LABEL: sqdecb_n32_i32: 94; CHECK: // %bb.0: 95; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 96; CHECK-NEXT: sqdecb x0, w0, vl3, mul #4 97; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 98; CHECK-NEXT: ret 99 %out = call i32 @llvm.aarch64.sve.sqdecb.n32(i32 %a, i32 3, i32 4) 100 ret i32 %out 101} 102 103define i64 @sqdecb_n32_i64(i32 %a) { 104; CHECK-LABEL: sqdecb_n32_i64: 105; CHECK: // %bb.0: 106; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 107; CHECK-NEXT: sqdecb x0, w0, vl3, mul #4 108; CHECK-NEXT: ret 109 %out = call i32 @llvm.aarch64.sve.sqdecb.n32(i32 %a, i32 3, i32 4) 110 %out_sext = sext i32 %out to i64 111 112 ret i64 %out_sext 113} 114 115define i64 @sqdecb_n64(i64 %a) { 116; CHECK-LABEL: sqdecb_n64: 117; CHECK: // %bb.0: 118; CHECK-NEXT: sqdecb x0, vl4, mul #5 119; CHECK-NEXT: ret 120 %out = call i64 @llvm.aarch64.sve.sqdecb.n64(i64 %a, i32 4, i32 5) 121 ret i64 %out 122} 123 124; 125; SQDECH (scalar) 126; 127 128define i32 @sqdech_n32_i32(i32 %a) { 129; CHECK-LABEL: sqdech_n32_i32: 130; CHECK: // %bb.0: 131; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 132; CHECK-NEXT: sqdech x0, w0, vl5, mul #6 133; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 134; CHECK-NEXT: ret 135 %out = call i32 @llvm.aarch64.sve.sqdech.n32(i32 %a, i32 5, i32 6) 136 ret i32 %out 137} 138 139define i64 @sqdech_n32_i64(i32 %a) { 140; CHECK-LABEL: sqdech_n32_i64: 141; CHECK: // %bb.0: 142; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 143; CHECK-NEXT: sqdech x0, w0, vl3, mul #4 144; CHECK-NEXT: ret 145 %out = call i32 @llvm.aarch64.sve.sqdech.n32(i32 %a, i32 3, i32 4) 146 %out_sext = sext i32 %out to i64 147 148 ret i64 %out_sext 149} 150 151define i64 @sqdech_n64(i64 %a) { 152; CHECK-LABEL: sqdech_n64: 153; CHECK: // %bb.0: 154; CHECK-NEXT: sqdech x0, vl6, mul #7 155; CHECK-NEXT: ret 156 %out = call i64 @llvm.aarch64.sve.sqdech.n64(i64 %a, i32 6, i32 7) 157 ret i64 %out 158} 159 160; 161; SQDECW (scalar) 162; 163 164define i32 @sqdecw_n32_i32(i32 %a) { 165; CHECK-LABEL: sqdecw_n32_i32: 166; CHECK: // %bb.0: 167; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 168; CHECK-NEXT: sqdecw x0, w0, vl7, mul #8 169; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 170; CHECK-NEXT: ret 171 %out = call i32 @llvm.aarch64.sve.sqdecw.n32(i32 %a, i32 7, i32 8) 172 ret i32 %out 173} 174 175define i64 @sqdecw_n32_i64(i32 %a) { 176; CHECK-LABEL: sqdecw_n32_i64: 177; CHECK: // %bb.0: 178; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 179; CHECK-NEXT: sqdecw x0, w0, vl3, mul #4 180; CHECK-NEXT: ret 181 %out = call i32 @llvm.aarch64.sve.sqdecw.n32(i32 %a, i32 3, i32 4) 182 %out_sext = sext i32 %out to i64 183 184 ret i64 %out_sext 185} 186 187define i64 @sqdecw_n64(i64 %a) { 188; CHECK-LABEL: sqdecw_n64: 189; CHECK: // %bb.0: 190; CHECK-NEXT: sqdecw x0, vl8, mul #9 191; CHECK-NEXT: ret 192 %out = call i64 @llvm.aarch64.sve.sqdecw.n64(i64 %a, i32 8, i32 9) 193 ret i64 %out 194} 195 196; 197; SQDECD (scalar) 198; 199 200define i32 @sqdecd_n32_i32(i32 %a) { 201; CHECK-LABEL: sqdecd_n32_i32: 202; CHECK: // %bb.0: 203; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 204; CHECK-NEXT: sqdecd x0, w0, vl16, mul #10 205; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 206; CHECK-NEXT: ret 207 %out = call i32 @llvm.aarch64.sve.sqdecd.n32(i32 %a, i32 9, i32 10) 208 ret i32 %out 209} 210 211define i64 @sqdecd_n32_i64(i32 %a) { 212; CHECK-LABEL: sqdecd_n32_i64: 213; CHECK: // %bb.0: 214; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 215; CHECK-NEXT: sqdecd x0, w0, vl3, mul #4 216; CHECK-NEXT: ret 217 %out = call i32 @llvm.aarch64.sve.sqdecd.n32(i32 %a, i32 3, i32 4) 218 %out_sext = sext i32 %out to i64 219 220 ret i64 %out_sext 221} 222 223define i64 @sqdecd_n64(i64 %a) { 224; CHECK-LABEL: sqdecd_n64: 225; CHECK: // %bb.0: 226; CHECK-NEXT: sqdecd x0, vl32, mul #11 227; CHECK-NEXT: ret 228 %out = call i64 @llvm.aarch64.sve.sqdecd.n64(i64 %a, i32 10, i32 11) 229 ret i64 %out 230} 231 232; 233; SQDECP (scalar) 234; 235 236define i32 @sqdecp_n32_b8_i32(i32 %a, <vscale x 16 x i1> %b) { 237; CHECK-LABEL: sqdecp_n32_b8_i32: 238; CHECK: // %bb.0: 239; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 240; CHECK-NEXT: sqdecp x0, p0.b, w0 241; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 242; CHECK-NEXT: ret 243 %out = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv16i1(i32 %a, <vscale x 16 x i1> %b) 244 ret i32 %out 245} 246 247define i64 @sqdecp_n32_b8_i64(i32 %a, <vscale x 16 x i1> %b) { 248; CHECK-LABEL: sqdecp_n32_b8_i64: 249; CHECK: // %bb.0: 250; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 251; CHECK-NEXT: sqdecp x0, p0.b, w0 252; CHECK-NEXT: ret 253 %out = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv16i1(i32 %a, <vscale x 16 x i1> %b) 254 %out_sext = sext i32 %out to i64 255 256 ret i64 %out_sext 257} 258 259define i32 @sqdecp_n32_b16_i32(i32 %a, <vscale x 8 x i1> %b) { 260; CHECK-LABEL: sqdecp_n32_b16_i32: 261; CHECK: // %bb.0: 262; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 263; CHECK-NEXT: sqdecp x0, p0.h, w0 264; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 265; CHECK-NEXT: ret 266 %out = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv8i1(i32 %a, <vscale x 8 x i1> %b) 267 ret i32 %out 268} 269 270define i64 @sqdecp_n32_b16_i64(i32 %a, <vscale x 8 x i1> %b) { 271; CHECK-LABEL: sqdecp_n32_b16_i64: 272; CHECK: // %bb.0: 273; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 274; CHECK-NEXT: sqdecp x0, p0.h, w0 275; CHECK-NEXT: ret 276 %out = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv8i1(i32 %a, <vscale x 8 x i1> %b) 277 %out_sext = sext i32 %out to i64 278 279 ret i64 %out_sext 280} 281 282define i32 @sqdecp_n32_b32_i32(i32 %a, <vscale x 4 x i1> %b) { 283; CHECK-LABEL: sqdecp_n32_b32_i32: 284; CHECK: // %bb.0: 285; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 286; CHECK-NEXT: sqdecp x0, p0.s, w0 287; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 288; CHECK-NEXT: ret 289 %out = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv4i1(i32 %a, <vscale x 4 x i1> %b) 290 ret i32 %out 291} 292 293define i64 @sqdecp_n32_b32_i64(i32 %a, <vscale x 4 x i1> %b) { 294; CHECK-LABEL: sqdecp_n32_b32_i64: 295; CHECK: // %bb.0: 296; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 297; CHECK-NEXT: sqdecp x0, p0.s, w0 298; CHECK-NEXT: ret 299 %out = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv4i1(i32 %a, <vscale x 4 x i1> %b) 300 %out_sext = sext i32 %out to i64 301 302 ret i64 %out_sext 303} 304 305define i32 @sqdecp_n32_b64_i32(i32 %a, <vscale x 2 x i1> %b) { 306; CHECK-LABEL: sqdecp_n32_b64_i32: 307; CHECK: // %bb.0: 308; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 309; CHECK-NEXT: sqdecp x0, p0.d, w0 310; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 311; CHECK-NEXT: ret 312 %out = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv2i1(i32 %a, <vscale x 2 x i1> %b) 313 ret i32 %out 314} 315 316define i64 @sqdecp_n32_b64_i64(i32 %a, <vscale x 2 x i1> %b) { 317; CHECK-LABEL: sqdecp_n32_b64_i64: 318; CHECK: // %bb.0: 319; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 320; CHECK-NEXT: sqdecp x0, p0.d, w0 321; CHECK-NEXT: ret 322 %out = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv2i1(i32 %a, <vscale x 2 x i1> %b) 323 %out_sext = sext i32 %out to i64 324 325 ret i64 %out_sext 326} 327 328define i64 @sqdecp_n64_b8(i64 %a, <vscale x 16 x i1> %b) { 329; CHECK-LABEL: sqdecp_n64_b8: 330; CHECK: // %bb.0: 331; CHECK-NEXT: sqdecp x0, p0.b 332; CHECK-NEXT: ret 333 %out = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv16i1(i64 %a, <vscale x 16 x i1> %b) 334 ret i64 %out 335} 336 337define i64 @sqdecp_n64_b16(i64 %a, <vscale x 8 x i1> %b) { 338; CHECK-LABEL: sqdecp_n64_b16: 339; CHECK: // %bb.0: 340; CHECK-NEXT: sqdecp x0, p0.h 341; CHECK-NEXT: ret 342 %out = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv8i1(i64 %a, <vscale x 8 x i1> %b) 343 ret i64 %out 344} 345 346define i64 @sqdecp_n64_b32(i64 %a, <vscale x 4 x i1> %b) { 347; CHECK-LABEL: sqdecp_n64_b32: 348; CHECK: // %bb.0: 349; CHECK-NEXT: sqdecp x0, p0.s 350; CHECK-NEXT: ret 351 %out = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv4i1(i64 %a, <vscale x 4 x i1> %b) 352 ret i64 %out 353} 354 355define i64 @sqdecp_n64_b64(i64 %a, <vscale x 2 x i1> %b) { 356; CHECK-LABEL: sqdecp_n64_b64: 357; CHECK: // %bb.0: 358; CHECK-NEXT: sqdecp x0, p0.d 359; CHECK-NEXT: ret 360 %out = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv2i1(i64 %a, <vscale x 2 x i1> %b) 361 ret i64 %out 362} 363 364; sqdec{h|w|d}(vector, pattern, multiplier) 365declare <vscale x 8 x i16> @llvm.aarch64.sve.sqdech.nxv8i16(<vscale x 8 x i16>, i32, i32) 366declare <vscale x 4 x i32> @llvm.aarch64.sve.sqdecw.nxv4i32(<vscale x 4 x i32>, i32, i32) 367declare <vscale x 2 x i64> @llvm.aarch64.sve.sqdecd.nxv2i64(<vscale x 2 x i64>, i32, i32) 368 369; sqdec{b|h|w|d}(scalar, pattern, multiplier) 370declare i32 @llvm.aarch64.sve.sqdecb.n32(i32, i32, i32) 371declare i64 @llvm.aarch64.sve.sqdecb.n64(i64, i32, i32) 372declare i32 @llvm.aarch64.sve.sqdech.n32(i32, i32, i32) 373declare i64 @llvm.aarch64.sve.sqdech.n64(i64, i32, i32) 374declare i32 @llvm.aarch64.sve.sqdecw.n32(i32, i32, i32) 375declare i64 @llvm.aarch64.sve.sqdecw.n64(i64, i32, i32) 376declare i32 @llvm.aarch64.sve.sqdecd.n32(i32, i32, i32) 377declare i64 @llvm.aarch64.sve.sqdecd.n64(i64, i32, i32) 378 379; sqdecp(scalar, predicate) 380declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv16i1(i32, <vscale x 16 x i1>) 381declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv8i1(i32, <vscale x 8 x i1>) 382declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv4i1(i32, <vscale x 4 x i1>) 383declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv2i1(i32, <vscale x 2 x i1>) 384 385declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv16i1(i64, <vscale x 16 x i1>) 386declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv8i1(i64, <vscale x 8 x i1>) 387declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv4i1(i64, <vscale x 4 x i1>) 388declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv2i1(i64, <vscale x 2 x i1>) 389 390; sqdecp(vector, predicate) 391declare <vscale x 8 x i16> @llvm.aarch64.sve.sqdecp.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>) 392declare <vscale x 4 x i32> @llvm.aarch64.sve.sqdecp.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>) 393declare <vscale x 2 x i64> @llvm.aarch64.sve.sqdecp.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>) 394