xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-intrinsics-shifts.ll (revision fadea4413ecbfffa4d28ad8298e0628165b543f1) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
3
4;
5; ASR
6;
7
8define <vscale x 16 x i8> @asr_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
9; CHECK-LABEL: asr_i8:
10; CHECK:       // %bb.0:
11; CHECK-NEXT:    asr z0.b, p0/m, z0.b, z1.b
12; CHECK-NEXT:    ret
13  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> %pg,
14                                                               <vscale x 16 x i8> %a,
15                                                               <vscale x 16 x i8> %b)
16  ret <vscale x 16 x i8> %out
17}
18
19define <vscale x 8 x i16> @asr_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
20; CHECK-LABEL: asr_i16:
21; CHECK:       // %bb.0:
22; CHECK-NEXT:    asr z0.h, p0/m, z0.h, z1.h
23; CHECK-NEXT:    ret
24  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1> %pg,
25                                                               <vscale x 8 x i16> %a,
26                                                               <vscale x 8 x i16> %b)
27  ret <vscale x 8 x i16> %out
28}
29
30define <vscale x 4 x i32> @asr_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
31; CHECK-LABEL: asr_i32:
32; CHECK:       // %bb.0:
33; CHECK-NEXT:    asr z0.s, p0/m, z0.s, z1.s
34; CHECK-NEXT:    ret
35  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1> %pg,
36                                                               <vscale x 4 x i32> %a,
37                                                               <vscale x 4 x i32> %b)
38  ret <vscale x 4 x i32> %out
39}
40
41define <vscale x 2 x i64> @asr_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
42; CHECK-LABEL: asr_i64:
43; CHECK:       // %bb.0:
44; CHECK-NEXT:    asr z0.d, p0/m, z0.d, z1.d
45; CHECK-NEXT:    ret
46  %out = call <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1> %pg,
47                                                               <vscale x 2 x i64> %a,
48                                                               <vscale x 2 x i64> %b)
49  ret <vscale x 2 x i64> %out
50}
51
52define <vscale x 16 x i8> @asr_wide_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) {
53; CHECK-LABEL: asr_wide_i8:
54; CHECK:       // %bb.0:
55; CHECK-NEXT:    asr z0.b, p0/m, z0.b, z1.d
56; CHECK-NEXT:    ret
57  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.wide.nxv16i8(<vscale x 16 x i1> %pg,
58                                                                    <vscale x 16 x i8> %a,
59                                                                    <vscale x 2 x i64> %b)
60  ret <vscale x 16 x i8> %out
61}
62
63define <vscale x 8 x i16> @asr_wide_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b) {
64; CHECK-LABEL: asr_wide_i16:
65; CHECK:       // %bb.0:
66; CHECK-NEXT:    asr z0.h, p0/m, z0.h, z1.d
67; CHECK-NEXT:    ret
68  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.wide.nxv8i16(<vscale x 8 x i1> %pg,
69                                                                    <vscale x 8 x i16> %a,
70                                                                    <vscale x 2 x i64> %b)
71  ret <vscale x 8 x i16> %out
72}
73
74define <vscale x 4 x i32> @asr_wide_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
75; CHECK-LABEL: asr_wide_i32:
76; CHECK:       // %bb.0:
77; CHECK-NEXT:    asr z0.s, p0/m, z0.s, z1.d
78; CHECK-NEXT:    ret
79  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.wide.nxv4i32(<vscale x 4 x i1> %pg,
80                                                                    <vscale x 4 x i32> %a,
81                                                                    <vscale x 2 x i64> %b)
82  ret <vscale x 4 x i32> %out
83}
84
85;
86; ASRD
87;
88
89define <vscale x 16 x i8> @asrd_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
90; CHECK-LABEL: asrd_i8:
91; CHECK:       // %bb.0:
92; CHECK-NEXT:    asrd z0.b, p0/m, z0.b, #1
93; CHECK-NEXT:    ret
94  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> %pg,
95                                                                <vscale x 16 x i8> %a,
96                                                                i32 1)
97  ret <vscale x 16 x i8> %out
98}
99
100define <vscale x 8 x i16> @asrd_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
101; CHECK-LABEL: asrd_i16:
102; CHECK:       // %bb.0:
103; CHECK-NEXT:    asrd z0.h, p0/m, z0.h, #2
104; CHECK-NEXT:    ret
105  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> %pg,
106                                                                <vscale x 8 x i16> %a,
107                                                                i32 2)
108  ret <vscale x 8 x i16> %out
109}
110
111define <vscale x 4 x i32> @asrd_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
112; CHECK-LABEL: asrd_i32:
113; CHECK:       // %bb.0:
114; CHECK-NEXT:    asrd z0.s, p0/m, z0.s, #31
115; CHECK-NEXT:    ret
116  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> %pg,
117                                                                <vscale x 4 x i32> %a,
118                                                                i32 31)
119  ret <vscale x 4 x i32> %out
120}
121
122define <vscale x 2 x i64> @asrd_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
123; CHECK-LABEL: asrd_i64:
124; CHECK:       // %bb.0:
125; CHECK-NEXT:    asrd z0.d, p0/m, z0.d, #64
126; CHECK-NEXT:    ret
127  %out = call <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1> %pg,
128                                                                <vscale x 2 x i64> %a,
129                                                                i32 64)
130  ret <vscale x 2 x i64> %out
131}
132
133;
134; INSR
135;
136
137define <vscale x 16 x i8> @insr_i8(<vscale x 16 x i8> %a, i8 %b) {
138; CHECK-LABEL: insr_i8:
139; CHECK:       // %bb.0:
140; CHECK-NEXT:    insr z0.b, w0
141; CHECK-NEXT:    ret
142  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.insr.nxv16i8(<vscale x 16 x i8> %a, i8 %b)
143  ret <vscale x 16 x i8> %out
144}
145
146define <vscale x 8 x i16> @insr_i16(<vscale x 8 x i16> %a, i16 %b) {
147; CHECK-LABEL: insr_i16:
148; CHECK:       // %bb.0:
149; CHECK-NEXT:    insr z0.h, w0
150; CHECK-NEXT:    ret
151  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.insr.nxv8i16(<vscale x 8 x i16> %a, i16 %b)
152  ret <vscale x 8 x i16> %out
153}
154
155define <vscale x 4 x i32> @insr_i32(<vscale x 4 x i32> %a, i32 %b) {
156; CHECK-LABEL: insr_i32:
157; CHECK:       // %bb.0:
158; CHECK-NEXT:    insr z0.s, w0
159; CHECK-NEXT:    ret
160  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.insr.nxv4i32(<vscale x 4 x i32> %a, i32 %b)
161  ret <vscale x 4 x i32> %out
162}
163
164define <vscale x 2 x i64> @insr_i64(<vscale x 2 x i64> %a, i64 %b) {
165; CHECK-LABEL: insr_i64:
166; CHECK:       // %bb.0:
167; CHECK-NEXT:    insr z0.d, x0
168; CHECK-NEXT:    ret
169  %out = call <vscale x 2 x i64> @llvm.aarch64.sve.insr.nxv2i64(<vscale x 2 x i64> %a, i64 %b)
170  ret <vscale x 2 x i64> %out
171}
172
173define <vscale x 8 x half> @insr_f16(<vscale x 8 x half> %a, half %b) {
174; CHECK-LABEL: insr_f16:
175; CHECK:       // %bb.0:
176; CHECK-NEXT:    // kill: def $h1 killed $h1 def $z1
177; CHECK-NEXT:    insr z0.h, h1
178; CHECK-NEXT:    ret
179  %out = call <vscale x 8 x half> @llvm.aarch64.sve.insr.nxv8f16(<vscale x 8 x half> %a, half %b)
180  ret <vscale x 8 x half> %out
181}
182
183define <vscale x 8 x bfloat> @insr_bf16(<vscale x 8 x bfloat> %a, bfloat %b) #0 {
184; CHECK-LABEL: insr_bf16:
185; CHECK:       // %bb.0:
186; CHECK-NEXT:    // kill: def $h1 killed $h1 def $z1
187; CHECK-NEXT:    insr z0.h, h1
188; CHECK-NEXT:    ret
189  %out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.insr.nxv8bf16(<vscale x 8 x bfloat> %a, bfloat %b)
190  ret <vscale x 8 x bfloat> %out
191}
192
193define <vscale x 4 x float> @insr_f32(<vscale x 4 x float> %a, float %b) {
194; CHECK-LABEL: insr_f32:
195; CHECK:       // %bb.0:
196; CHECK-NEXT:    // kill: def $s1 killed $s1 def $z1
197; CHECK-NEXT:    insr z0.s, s1
198; CHECK-NEXT:    ret
199  %out = call <vscale x 4 x float> @llvm.aarch64.sve.insr.nxv4f32(<vscale x 4 x float> %a, float %b)
200  ret <vscale x 4 x float> %out
201}
202
203define <vscale x 2 x double> @insr_f64(<vscale x 2 x double> %a, double %b) {
204; CHECK-LABEL: insr_f64:
205; CHECK:       // %bb.0:
206; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
207; CHECK-NEXT:    insr z0.d, d1
208; CHECK-NEXT:    ret
209  %out = call <vscale x 2 x double> @llvm.aarch64.sve.insr.nxv2f64(<vscale x 2 x double> %a, double %b)
210  ret <vscale x 2 x double> %out
211}
212
213;
214; LSL
215;
216
217define <vscale x 16 x i8> @lsl_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
218; CHECK-LABEL: lsl_i8:
219; CHECK:       // %bb.0:
220; CHECK-NEXT:    lsl z0.b, p0/m, z0.b, z1.b
221; CHECK-NEXT:    ret
222  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> %pg,
223                                                               <vscale x 16 x i8> %a,
224                                                               <vscale x 16 x i8> %b)
225  ret <vscale x 16 x i8> %out
226}
227
228define <vscale x 8 x i16> @lsl_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
229; CHECK-LABEL: lsl_i16:
230; CHECK:       // %bb.0:
231; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, z1.h
232; CHECK-NEXT:    ret
233  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1> %pg,
234                                                               <vscale x 8 x i16> %a,
235                                                               <vscale x 8 x i16> %b)
236  ret <vscale x 8 x i16> %out
237}
238
239define <vscale x 4 x i32> @lsl_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
240; CHECK-LABEL: lsl_i32:
241; CHECK:       // %bb.0:
242; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, z1.s
243; CHECK-NEXT:    ret
244  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1> %pg,
245                                                               <vscale x 4 x i32> %a,
246                                                               <vscale x 4 x i32> %b)
247  ret <vscale x 4 x i32> %out
248}
249
250define <vscale x 2 x i64> @lsl_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
251; CHECK-LABEL: lsl_i64:
252; CHECK:       // %bb.0:
253; CHECK-NEXT:    lsl z0.d, p0/m, z0.d, z1.d
254; CHECK-NEXT:    ret
255  %out = call <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1> %pg,
256                                                               <vscale x 2 x i64> %a,
257                                                               <vscale x 2 x i64> %b)
258  ret <vscale x 2 x i64> %out
259}
260
261define <vscale x 16 x i8> @lsl_wide_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) {
262; CHECK-LABEL: lsl_wide_i8:
263; CHECK:       // %bb.0:
264; CHECK-NEXT:    lsl z0.b, p0/m, z0.b, z1.d
265; CHECK-NEXT:    ret
266  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.wide.nxv16i8(<vscale x 16 x i1> %pg,
267                                                                    <vscale x 16 x i8> %a,
268                                                                    <vscale x 2 x i64> %b)
269  ret <vscale x 16 x i8> %out
270}
271
272define <vscale x 8 x i16> @lsl_wide_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b) {
273; CHECK-LABEL: lsl_wide_i16:
274; CHECK:       // %bb.0:
275; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, z1.d
276; CHECK-NEXT:    ret
277  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.lsl.wide.nxv8i16(<vscale x 8 x i1> %pg,
278                                                                    <vscale x 8 x i16> %a,
279                                                                    <vscale x 2 x i64> %b)
280  ret <vscale x 8 x i16> %out
281}
282
283define <vscale x 4 x i32> @lsl_wide_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
284; CHECK-LABEL: lsl_wide_i32:
285; CHECK:       // %bb.0:
286; CHECK-NEXT:    lsl z0.s, p0/m, z0.s, z1.d
287; CHECK-NEXT:    ret
288  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.wide.nxv4i32(<vscale x 4 x i1> %pg,
289                                                                    <vscale x 4 x i32> %a,
290                                                                    <vscale x 2 x i64> %b)
291  ret <vscale x 4 x i32> %out
292}
293
294;
295; LSR
296;
297
298define <vscale x 16 x i8> @lsr_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
299; CHECK-LABEL: lsr_i8:
300; CHECK:       // %bb.0:
301; CHECK-NEXT:    lsr z0.b, p0/m, z0.b, z1.b
302; CHECK-NEXT:    ret
303  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> %pg,
304                                                               <vscale x 16 x i8> %a,
305                                                               <vscale x 16 x i8> %b)
306  ret <vscale x 16 x i8> %out
307}
308
309define <vscale x 8 x i16> @lsr_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
310; CHECK-LABEL: lsr_i16:
311; CHECK:       // %bb.0:
312; CHECK-NEXT:    lsr z0.h, p0/m, z0.h, z1.h
313; CHECK-NEXT:    ret
314  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1> %pg,
315                                                               <vscale x 8 x i16> %a,
316                                                               <vscale x 8 x i16> %b)
317  ret <vscale x 8 x i16> %out
318}
319
320define <vscale x 4 x i32> @lsr_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
321; CHECK-LABEL: lsr_i32:
322; CHECK:       // %bb.0:
323; CHECK-NEXT:    lsr z0.s, p0/m, z0.s, z1.s
324; CHECK-NEXT:    ret
325  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1> %pg,
326                                                               <vscale x 4 x i32> %a,
327                                                               <vscale x 4 x i32> %b)
328  ret <vscale x 4 x i32> %out
329}
330
331define <vscale x 2 x i64> @lsr_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
332; CHECK-LABEL: lsr_i64:
333; CHECK:       // %bb.0:
334; CHECK-NEXT:    lsr z0.d, p0/m, z0.d, z1.d
335; CHECK-NEXT:    ret
336  %out = call <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1> %pg,
337                                                               <vscale x 2 x i64> %a,
338                                                               <vscale x 2 x i64> %b)
339  ret <vscale x 2 x i64> %out
340}
341
342define <vscale x 16 x i8> @lsr_wide_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) {
343; CHECK-LABEL: lsr_wide_i8:
344; CHECK:       // %bb.0:
345; CHECK-NEXT:    lsr z0.b, p0/m, z0.b, z1.d
346; CHECK-NEXT:    ret
347  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.wide.nxv16i8(<vscale x 16 x i1> %pg,
348                                                                    <vscale x 16 x i8> %a,
349                                                                    <vscale x 2 x i64> %b)
350  ret <vscale x 16 x i8> %out
351}
352
353define <vscale x 8 x i16> @lsr_wide_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b) {
354; CHECK-LABEL: lsr_wide_i16:
355; CHECK:       // %bb.0:
356; CHECK-NEXT:    lsr z0.h, p0/m, z0.h, z1.d
357; CHECK-NEXT:    ret
358  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.lsr.wide.nxv8i16(<vscale x 8 x i1> %pg,
359                                                                    <vscale x 8 x i16> %a,
360                                                                    <vscale x 2 x i64> %b)
361  ret <vscale x 8 x i16> %out
362}
363
364define <vscale x 4 x i32> @lsr_wide_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
365; CHECK-LABEL: lsr_wide_i32:
366; CHECK:       // %bb.0:
367; CHECK-NEXT:    lsr z0.s, p0/m, z0.s, z1.d
368; CHECK-NEXT:    ret
369  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.wide.nxv4i32(<vscale x 4 x i1> %pg,
370                                                                    <vscale x 4 x i32> %a,
371                                                                    <vscale x 2 x i64> %b)
372  ret <vscale x 4 x i32> %out
373}
374
375declare <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
376declare <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
377declare <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
378declare <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
379
380declare <vscale x 16 x i8> @llvm.aarch64.sve.asr.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)
381declare <vscale x 8 x i16> @llvm.aarch64.sve.asr.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)
382declare <vscale x 4 x i32> @llvm.aarch64.sve.asr.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)
383
384declare <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, i32)
385declare <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, i32)
386declare <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i32)
387declare <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i32)
388
389declare <vscale x 16 x i8> @llvm.aarch64.sve.insr.nxv16i8(<vscale x 16 x i8>, i8)
390declare <vscale x 8 x i16> @llvm.aarch64.sve.insr.nxv8i16(<vscale x 8 x i16>, i16)
391declare <vscale x 4 x i32> @llvm.aarch64.sve.insr.nxv4i32(<vscale x 4 x i32>, i32)
392declare <vscale x 2 x i64> @llvm.aarch64.sve.insr.nxv2i64(<vscale x 2 x i64>, i64)
393declare <vscale x 8 x half> @llvm.aarch64.sve.insr.nxv8f16(<vscale x 8 x half>, half)
394declare <vscale x 8 x bfloat> @llvm.aarch64.sve.insr.nxv8bf16(<vscale x 8 x bfloat>, bfloat)
395declare <vscale x 4 x float> @llvm.aarch64.sve.insr.nxv4f32(<vscale x 4 x float>, float)
396declare <vscale x 2 x double> @llvm.aarch64.sve.insr.nxv2f64(<vscale x 2 x double>, double)
397
398declare <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
399declare <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
400declare <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
401declare <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
402
403declare <vscale x 16 x i8> @llvm.aarch64.sve.lsl.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)
404declare <vscale x 8 x i16> @llvm.aarch64.sve.lsl.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)
405declare <vscale x 4 x i32> @llvm.aarch64.sve.lsl.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)
406
407declare <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
408declare <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
409declare <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
410declare <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
411
412declare <vscale x 16 x i8> @llvm.aarch64.sve.lsr.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)
413declare <vscale x 8 x i16> @llvm.aarch64.sve.lsr.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)
414declare <vscale x 4 x i32> @llvm.aarch64.sve.lsr.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)
415
416; +bf16 is required for the bfloat version.
417attributes #0 = { "target-features"="+sve,+bf16" }
418