xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-intrinsics-scatter-stores-64bit-scaled-offset.ll (revision 5ddce70ef0e5a641d7fea95e31fc5e2439cb98cb) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
3
4;
5; ST1H, ST1W, ST1D: base + 64-bit scaled offset
6;   e.g. st1h { z0.d }, p0, [x0, z0.d, lsl #1]
7;
8
9define void @sst1h_index(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i64> %offsets) {
10; CHECK-LABEL: sst1h_index:
11; CHECK:       // %bb.0:
12; CHECK-NEXT:    st1h { z0.d }, p0, [x0, z1.d, lsl #1]
13; CHECK-NEXT:    ret
14  %data_trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i16>
15  call void @llvm.aarch64.sve.st1.scatter.index.nxv2i16(<vscale x 2 x i16> %data_trunc,
16                                                        <vscale x 2 x i1> %pg,
17                                                        ptr %base,
18                                                        <vscale x 2 x i64> %offsets)
19  ret void
20}
21
22define void @sst1w_index(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i64> %offsets) {
23; CHECK-LABEL: sst1w_index:
24; CHECK:       // %bb.0:
25; CHECK-NEXT:    st1w { z0.d }, p0, [x0, z1.d, lsl #2]
26; CHECK-NEXT:    ret
27  %data_trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i32>
28  call void @llvm.aarch64.sve.st1.scatter.index.nxv2i32(<vscale x 2 x i32> %data_trunc,
29                                                        <vscale x 2 x i1> %pg,
30                                                        ptr %base,
31                                                        <vscale x 2 x i64> %offsets)
32  ret void
33}
34
35define void  @sst1d_index(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i64> %offsets) {
36; CHECK-LABEL: sst1d_index:
37; CHECK:       // %bb.0:
38; CHECK-NEXT:    st1d { z0.d }, p0, [x0, z1.d, lsl #3]
39; CHECK-NEXT:    ret
40  call void @llvm.aarch64.sve.st1.scatter.index.nxv2i64(<vscale x 2 x i64> %data,
41                                                        <vscale x 2 x i1> %pg,
42                                                        ptr %base,
43                                                        <vscale x 2 x i64> %offsets)
44  ret void
45}
46
47define void  @sst1d_index_double(<vscale x 2 x double> %data, <vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i64> %offsets) {
48; CHECK-LABEL: sst1d_index_double:
49; CHECK:       // %bb.0:
50; CHECK-NEXT:    st1d { z0.d }, p0, [x0, z1.d, lsl #3]
51; CHECK-NEXT:    ret
52  call void @llvm.aarch64.sve.st1.scatter.index.nxv2f64(<vscale x 2 x double> %data,
53                                                        <vscale x 2 x i1> %pg,
54                                                        ptr %base,
55                                                        <vscale x 2 x i64> %offsets)
56  ret void
57}
58
59
60declare void @llvm.aarch64.sve.st1.scatter.index.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i1>, ptr, <vscale x 2 x i64>)
61declare void @llvm.aarch64.sve.st1.scatter.index.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i1>, ptr, <vscale x 2 x i64>)
62declare void @llvm.aarch64.sve.st1.scatter.index.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, ptr, <vscale x 2 x i64>)
63declare void @llvm.aarch64.sve.st1.scatter.index.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, ptr, <vscale x 2 x i64>)
64