xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-intrinsics-scatter-stores-32bit-scaled-offsets.ll (revision 5ddce70ef0e5a641d7fea95e31fc5e2439cb98cb) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
3
4;
5; ST1H, ST1W, ST1D: base + 32-bit scaled offset, sign (sxtw) or zero
6; (uxtw) extended to 64 bits.
7;   e.g. st1h { z0.d }, p0, [x0, z1.d, uxtw #1]
8;
9
10; ST1H
11define void @sst1h_s_uxtw(<vscale x 4 x i32> %data, <vscale x 4 x i1> %pg, ptr %base, <vscale x 4 x i32> %indices) {
12; CHECK-LABEL: sst1h_s_uxtw:
13; CHECK:       // %bb.0:
14; CHECK-NEXT:    st1h { z0.s }, p0, [x0, z1.s, uxtw #1]
15; CHECK-NEXT:    ret
16  %data_trunc = trunc <vscale x 4 x i32> %data to <vscale x 4 x i16>
17  call void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv4i16(<vscale x 4 x i16> %data_trunc,
18                                                             <vscale x 4 x i1> %pg,
19                                                             ptr %base,
20                                                             <vscale x 4 x i32> %indices)
21  ret void
22}
23
24define void @sst1h_s_sxtw(<vscale x 4 x i32> %data, <vscale x 4 x i1> %pg, ptr %base, <vscale x 4 x i32> %indices) {
25; CHECK-LABEL: sst1h_s_sxtw:
26; CHECK:       // %bb.0:
27; CHECK-NEXT:    st1h { z0.s }, p0, [x0, z1.s, sxtw #1]
28; CHECK-NEXT:    ret
29  %data_trunc = trunc <vscale x 4 x i32> %data to <vscale x 4 x i16>
30  call void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv4i16(<vscale x 4 x i16> %data_trunc,
31                                                             <vscale x 4 x i1> %pg,
32                                                             ptr %base,
33                                                             <vscale x 4 x i32> %indices)
34  ret void
35}
36
37define void @sst1h_d_uxtw(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %indices) {
38; CHECK-LABEL: sst1h_d_uxtw:
39; CHECK:       // %bb.0:
40; CHECK-NEXT:    st1h { z0.d }, p0, [x0, z1.d, uxtw #1]
41; CHECK-NEXT:    ret
42  %data_trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i16>
43  call void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv2i16(<vscale x 2 x i16> %data_trunc,
44                                                             <vscale x 2 x i1> %pg,
45                                                             ptr %base,
46                                                             <vscale x 2 x i32> %indices)
47  ret void
48}
49
50define void @sst1h_d_sxtw(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %indices) {
51; CHECK-LABEL: sst1h_d_sxtw:
52; CHECK:       // %bb.0:
53; CHECK-NEXT:    st1h { z0.d }, p0, [x0, z1.d, sxtw #1]
54; CHECK-NEXT:    ret
55  %data_trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i16>
56  call void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv2i16(<vscale x 2 x i16> %data_trunc,
57                                                             <vscale x 2 x i1> %pg,
58                                                             ptr %base,
59                                                             <vscale x 2 x i32> %indices)
60  ret void
61}
62
63; ST1W
64define void @sst1w_s_uxtw(<vscale x 4 x i32> %data, <vscale x 4 x i1> %pg, ptr %base, <vscale x 4 x i32> %indices) {
65; CHECK-LABEL: sst1w_s_uxtw:
66; CHECK:       // %bb.0:
67; CHECK-NEXT:    st1w { z0.s }, p0, [x0, z1.s, uxtw #2]
68; CHECK-NEXT:    ret
69  call void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv4i32(<vscale x 4 x i32> %data,
70                                                             <vscale x 4 x i1> %pg,
71                                                             ptr %base,
72                                                             <vscale x 4 x i32> %indices)
73  ret void
74}
75
76define void @sst1w_s_sxtw(<vscale x 4 x i32> %data, <vscale x 4 x i1> %pg, ptr %base, <vscale x 4 x i32> %indices) {
77; CHECK-LABEL: sst1w_s_sxtw:
78; CHECK:       // %bb.0:
79; CHECK-NEXT:    st1w { z0.s }, p0, [x0, z1.s, sxtw #2]
80; CHECK-NEXT:    ret
81  call void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv4i32(<vscale x 4 x i32> %data,
82                                                             <vscale x 4 x i1> %pg,
83                                                             ptr %base,
84                                                             <vscale x 4 x i32> %indices)
85  ret void
86}
87
88define void @sst1w_d_uxtw(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %indices) {
89; CHECK-LABEL: sst1w_d_uxtw:
90; CHECK:       // %bb.0:
91; CHECK-NEXT:    st1w { z0.d }, p0, [x0, z1.d, uxtw #2]
92; CHECK-NEXT:    ret
93  %data_trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i32>
94  call void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv2i32(<vscale x 2 x i32> %data_trunc,
95                                                             <vscale x 2 x i1> %pg,
96                                                             ptr %base,
97                                                             <vscale x 2 x i32> %indices)
98  ret void
99}
100
101define void @sst1w_d_sxtw(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %indices) {
102; CHECK-LABEL: sst1w_d_sxtw:
103; CHECK:       // %bb.0:
104; CHECK-NEXT:    st1w { z0.d }, p0, [x0, z1.d, sxtw #2]
105; CHECK-NEXT:    ret
106  %data_trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i32>
107  call void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv2i32(<vscale x 2 x i32> %data_trunc,
108                                                             <vscale x 2 x i1> %pg,
109                                                             ptr %base,
110                                                             <vscale x 2 x i32> %indices)
111  ret void
112}
113
114define void @sst1w_s_uxtw_float(<vscale x 4 x float> %data, <vscale x 4 x i1> %pg, ptr %base, <vscale x 4 x i32> %indices) {
115; CHECK-LABEL: sst1w_s_uxtw_float:
116; CHECK:       // %bb.0:
117; CHECK-NEXT:    st1w { z0.s }, p0, [x0, z1.s, uxtw #2]
118; CHECK-NEXT:    ret
119  call void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv4f32(<vscale x 4 x float> %data,
120                                                             <vscale x 4 x i1> %pg,
121                                                             ptr %base,
122                                                             <vscale x 4 x i32> %indices)
123  ret void
124}
125
126define void @sst1w_s_sxtw_float(<vscale x 4 x float> %data, <vscale x 4 x i1> %pg, ptr %base, <vscale x 4 x i32> %indices) {
127; CHECK-LABEL: sst1w_s_sxtw_float:
128; CHECK:       // %bb.0:
129; CHECK-NEXT:    st1w { z0.s }, p0, [x0, z1.s, sxtw #2]
130; CHECK-NEXT:    ret
131  call void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv4f32(<vscale x 4 x float> %data,
132                                                             <vscale x 4 x i1> %pg,
133                                                             ptr %base,
134                                                             <vscale x 4 x i32> %indices)
135  ret void
136}
137
138; ST1D
139define void @sst1d_d_uxtw(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %indices) {
140; CHECK-LABEL: sst1d_d_uxtw:
141; CHECK:       // %bb.0:
142; CHECK-NEXT:    st1d { z0.d }, p0, [x0, z1.d, uxtw #3]
143; CHECK-NEXT:    ret
144  call void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv2i64(<vscale x 2 x i64> %data,
145                                                             <vscale x 2 x i1> %pg,
146                                                             ptr %base,
147                                                             <vscale x 2 x i32> %indices)
148  ret void
149}
150
151define void @sst1d_d_sxtw(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %indices) {
152; CHECK-LABEL: sst1d_d_sxtw:
153; CHECK:       // %bb.0:
154; CHECK-NEXT:    st1d { z0.d }, p0, [x0, z1.d, sxtw #3]
155; CHECK-NEXT:    ret
156  call void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv2i64(<vscale x 2 x i64> %data,
157                                                             <vscale x 2 x i1> %pg,
158                                                             ptr %base,
159                                                             <vscale x 2 x i32> %indices)
160  ret void
161}
162
163define void @sst1d_d_uxtw_double(<vscale x 2 x double> %data, <vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %indices) {
164; CHECK-LABEL: sst1d_d_uxtw_double:
165; CHECK:       // %bb.0:
166; CHECK-NEXT:    st1d { z0.d }, p0, [x0, z1.d, uxtw #3]
167; CHECK-NEXT:    ret
168  call void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv2f64(<vscale x 2 x double> %data,
169                                                             <vscale x 2 x i1> %pg,
170                                                             ptr %base,
171                                                             <vscale x 2 x i32> %indices)
172  ret void
173}
174
175define void @sst1d_d_sxtw_double(<vscale x 2 x double> %data, <vscale x 2 x i1> %pg, ptr %base, <vscale x 2 x i32> %indices) {
176; CHECK-LABEL: sst1d_d_sxtw_double:
177; CHECK:       // %bb.0:
178; CHECK-NEXT:    st1d { z0.d }, p0, [x0, z1.d, sxtw #3]
179; CHECK-NEXT:    ret
180  call void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv2f64(<vscale x 2 x double> %data,
181                                                             <vscale x 2 x i1> %pg,
182                                                             ptr %base,
183                                                             <vscale x 2 x i32> %indices)
184  ret void
185}
186
187
188; ST1H
189declare void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i1>, ptr, <vscale x 4 x i32>)
190declare void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i1>, ptr, <vscale x 2 x i32>)
191declare void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i1>, ptr, <vscale x 4 x i32>)
192declare void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i1>, ptr, <vscale x 2 x i32>)
193
194; ST1W
195declare void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, ptr, <vscale x 4 x i32>)
196declare void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i1>, ptr, <vscale x 2 x i32>)
197declare void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, ptr, <vscale x 4 x i32>)
198declare void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i1>, ptr, <vscale x 2 x i32>)
199
200declare void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, ptr, <vscale x 4 x i32>)
201declare void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, ptr, <vscale x 4 x i32>)
202
203; ST1D
204declare void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, ptr, <vscale x 2 x i32>)
205declare void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, ptr, <vscale x 2 x i32>)
206
207declare void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, ptr, <vscale x 2 x i32>)
208declare void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, ptr, <vscale x 2 x i32>)
209