xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-intrinsics-logical.ll (revision 62baf21daa377c4ec1a641b26931063c1117d262) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s
4
5;
6; CNOT
7;
8
9define <vscale x 16 x i8> @cnot_i8(<vscale x 16 x i8> %a, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %b) {
10; CHECK-LABEL: cnot_i8:
11; CHECK:       // %bb.0:
12; CHECK-NEXT:    cnot z0.b, p0/m, z1.b
13; CHECK-NEXT:    ret
14  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.cnot.nxv16i8(<vscale x 16 x i8> %a,
15                                                                <vscale x 16 x i1> %pg,
16                                                                <vscale x 16 x i8> %b)
17  ret <vscale x 16 x i8> %out
18}
19
20define <vscale x 8 x i16> @cnot_i16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %b) {
21; CHECK-LABEL: cnot_i16:
22; CHECK:       // %bb.0:
23; CHECK-NEXT:    cnot z0.h, p0/m, z1.h
24; CHECK-NEXT:    ret
25  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.cnot.nxv8i16(<vscale x 8 x i16> %a,
26                                                                <vscale x 8 x i1> %pg,
27                                                                <vscale x 8 x i16> %b)
28  ret <vscale x 8 x i16> %out
29}
30
31define <vscale x 4 x i32> @cnot_i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %b) {
32; CHECK-LABEL: cnot_i32:
33; CHECK:       // %bb.0:
34; CHECK-NEXT:    cnot z0.s, p0/m, z1.s
35; CHECK-NEXT:    ret
36  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.cnot.nxv4i32(<vscale x 4 x i32> %a,
37                                                                <vscale x 4 x i1> %pg,
38                                                                <vscale x 4 x i32> %b)
39  ret <vscale x 4 x i32> %out
40}
41
42define <vscale x 2 x i64> @cnot_i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b) {
43; CHECK-LABEL: cnot_i64:
44; CHECK:       // %bb.0:
45; CHECK-NEXT:    cnot z0.d, p0/m, z1.d
46; CHECK-NEXT:    ret
47  %out = call <vscale x 2 x i64> @llvm.aarch64.sve.cnot.nxv2i64(<vscale x 2 x i64> %a,
48                                                                <vscale x 2 x i1> %pg,
49                                                                <vscale x 2 x i64> %b)
50  ret <vscale x 2 x i64> %out
51}
52
53;
54; NOT
55;
56
57define <vscale x 16 x i8> @not_i8(<vscale x 16 x i8> %a, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %b) {
58; CHECK-LABEL: not_i8:
59; CHECK:       // %bb.0:
60; CHECK-NEXT:    not z0.b, p0/m, z1.b
61; CHECK-NEXT:    ret
62  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.not.nxv16i8(<vscale x 16 x i8> %a,
63                                                               <vscale x 16 x i1> %pg,
64                                                               <vscale x 16 x i8> %b)
65  ret <vscale x 16 x i8> %out
66}
67
68define <vscale x 8 x i16> @not_i16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %b) {
69; CHECK-LABEL: not_i16:
70; CHECK:       // %bb.0:
71; CHECK-NEXT:    not z0.h, p0/m, z1.h
72; CHECK-NEXT:    ret
73  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.not.nxv8i16(<vscale x 8 x i16> %a,
74                                                               <vscale x 8 x i1> %pg,
75                                                               <vscale x 8 x i16> %b)
76  ret <vscale x 8 x i16> %out
77}
78
79define <vscale x 4 x i32> @not_i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %b) {
80; CHECK-LABEL: not_i32:
81; CHECK:       // %bb.0:
82; CHECK-NEXT:    not z0.s, p0/m, z1.s
83; CHECK-NEXT:    ret
84  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.not.nxv4i32(<vscale x 4 x i32> %a,
85                                                               <vscale x 4 x i1> %pg,
86                                                               <vscale x 4 x i32> %b)
87  ret <vscale x 4 x i32> %out
88}
89
90define <vscale x 2 x i64> @not_i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b) {
91; CHECK-LABEL: not_i64:
92; CHECK:       // %bb.0:
93; CHECK-NEXT:    not z0.d, p0/m, z1.d
94; CHECK-NEXT:    ret
95  %out = call <vscale x 2 x i64> @llvm.aarch64.sve.not.nxv2i64(<vscale x 2 x i64> %a,
96                                                               <vscale x 2 x i1> %pg,
97                                                               <vscale x 2 x i64> %b)
98  ret <vscale x 2 x i64> %out
99}
100
101declare <vscale x 16 x i8> @llvm.aarch64.sve.cnot.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>)
102declare <vscale x 8 x i16> @llvm.aarch64.sve.cnot.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>)
103declare <vscale x 4 x i32> @llvm.aarch64.sve.cnot.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)
104declare <vscale x 2 x i64> @llvm.aarch64.sve.cnot.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>)
105
106declare <vscale x 16 x i8> @llvm.aarch64.sve.not.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>)
107declare <vscale x 8 x i16> @llvm.aarch64.sve.not.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>)
108declare <vscale x 4 x i32> @llvm.aarch64.sve.not.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)
109declare <vscale x 2 x i64> @llvm.aarch64.sve.not.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>)
110