xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-intrinsics-ld1ro.ll (revision 5ddce70ef0e5a641d7fea95e31fc5e2439cb98cb) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+f64mm < %s | FileCheck %s
3
4;
5; LD1ROB
6;
7
8define <vscale x 16 x i8> @ld1rob_i8(<vscale x 16 x i1> %pred, ptr %addr) nounwind {
9; CHECK-LABEL: ld1rob_i8:
10; CHECK:       // %bb.0:
11; CHECK-NEXT:    ld1rob { z0.b }, p0/z, [x0]
12; CHECK-NEXT:    ret
13  %res = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8(<vscale x 16 x i1> %pred, ptr %addr)
14  ret <vscale x 16 x i8> %res
15}
16
17;
18; LD1ROH
19;
20
21define <vscale x 8 x i16> @ld1roh_i16(<vscale x 8 x i1> %pred, ptr %addr) nounwind {
22; CHECK-LABEL: ld1roh_i16:
23; CHECK:       // %bb.0:
24; CHECK-NEXT:    ld1roh { z0.h }, p0/z, [x0]
25; CHECK-NEXT:    ret
26  %res = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16(<vscale x 8 x i1> %pred, ptr %addr)
27  ret <vscale x 8 x i16> %res
28}
29
30define <vscale x 8 x half> @ld1roh_half(<vscale x 8 x i1> %pred, ptr %addr) nounwind {
31; CHECK-LABEL: ld1roh_half:
32; CHECK:       // %bb.0:
33; CHECK-NEXT:    ld1roh { z0.h }, p0/z, [x0]
34; CHECK-NEXT:    ret
35  %res = call <vscale x 8 x half> @llvm.aarch64.sve.ld1ro.nxv8f16(<vscale x 8 x i1> %pred, ptr %addr)
36  ret <vscale x 8 x half> %res
37}
38
39;
40; LD1ROW
41;
42
43define <vscale x 4 x i32> @ld1row_i32(<vscale x 4 x i1> %pred, ptr %addr) nounwind {
44; CHECK-LABEL: ld1row_i32:
45; CHECK:       // %bb.0:
46; CHECK-NEXT:    ld1row { z0.s }, p0/z, [x0]
47; CHECK-NEXT:    ret
48  %res = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32(<vscale x 4 x i1> %pred, ptr %addr)
49  ret <vscale x 4 x i32> %res
50}
51
52define <vscale x 4 x float> @ld1row_float(<vscale x 4 x i1> %pred, ptr %addr) nounwind {
53; CHECK-LABEL: ld1row_float:
54; CHECK:       // %bb.0:
55; CHECK-NEXT:    ld1row { z0.s }, p0/z, [x0]
56; CHECK-NEXT:    ret
57  %res = call <vscale x 4 x float> @llvm.aarch64.sve.ld1ro.nxv4f32(<vscale x 4 x i1> %pred, ptr %addr)
58  ret <vscale x 4 x float> %res
59}
60
61;
62; LD1ROD
63;
64
65define <vscale x 2 x i64> @ld1rod_i64(<vscale x 2 x i1> %pred, ptr %addr) nounwind {
66; CHECK-LABEL: ld1rod_i64:
67; CHECK:       // %bb.0:
68; CHECK-NEXT:    ld1rod { z0.d }, p0/z, [x0]
69; CHECK-NEXT:    ret
70  %res = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64(<vscale x 2 x i1> %pred, ptr %addr)
71  ret <vscale x 2 x i64> %res
72}
73
74define <vscale x 2 x double> @ld1rod_double(<vscale x 2 x i1> %pred, ptr %addr) nounwind {
75; CHECK-LABEL: ld1rod_double:
76; CHECK:       // %bb.0:
77; CHECK-NEXT:    ld1rod { z0.d }, p0/z, [x0]
78; CHECK-NEXT:    ret
79  %res = call <vscale x 2 x double> @llvm.aarch64.sve.ld1ro.nxv2f64(<vscale x 2 x i1> %pred, ptr %addr)
80  ret <vscale x 2 x double> %res
81}
82
83declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8(<vscale x 16 x i1>, ptr)
84
85declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16(<vscale x 8 x i1>, ptr)
86declare <vscale x 8 x half> @llvm.aarch64.sve.ld1ro.nxv8f16(<vscale x 8 x i1>, ptr)
87
88declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32(<vscale x 4 x i1>, ptr)
89declare <vscale x 4 x float> @llvm.aarch64.sve.ld1ro.nxv4f32(<vscale x 4 x i1>, ptr)
90
91declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64(<vscale x 2 x i1>, ptr)
92declare <vscale x 2 x double> @llvm.aarch64.sve.ld1ro.nxv2f64(<vscale x 2 x i1>, ptr)
93