xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares.ll (revision 3870857226b68fe19e97969e256e31c5eb681c04) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
3
4;
5; CMPEQ
6;
7
8define <vscale x 16 x i1> @cmpeq_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
9; CHECK-LABEL: cmpeq_b:
10; CHECK:       // %bb.0:
11; CHECK-NEXT:    cmpeq p0.b, p0/z, z0.b, z1.b
12; CHECK-NEXT:    ret
13  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %pg,
14                                                                 <vscale x 16 x i8> %a,
15                                                                 <vscale x 16 x i8> %b)
16  ret <vscale x 16 x i1> %out
17}
18
19define <vscale x 8 x i1> @cmpeq_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
20; CHECK-LABEL: cmpeq_h:
21; CHECK:       // %bb.0:
22; CHECK-NEXT:    cmpeq p0.h, p0/z, z0.h, z1.h
23; CHECK-NEXT:    ret
24  %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpeq.nxv8i16(<vscale x 8 x i1> %pg,
25                                                                <vscale x 8 x i16> %a,
26                                                                <vscale x 8 x i16> %b)
27  ret <vscale x 8 x i1> %out
28}
29
30define <vscale x 4 x i1> @cmpeq_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
31; CHECK-LABEL: cmpeq_s:
32; CHECK:       // %bb.0:
33; CHECK-NEXT:    cmpeq p0.s, p0/z, z0.s, z1.s
34; CHECK-NEXT:    ret
35  %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpeq.nxv4i32(<vscale x 4 x i1> %pg,
36                                                                <vscale x 4 x i32> %a,
37                                                                <vscale x 4 x i32> %b)
38  ret <vscale x 4 x i1> %out
39}
40
41define <vscale x 2 x i1> @cmpeq_d(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
42; CHECK-LABEL: cmpeq_d:
43; CHECK:       // %bb.0:
44; CHECK-NEXT:    cmpeq p0.d, p0/z, z0.d, z1.d
45; CHECK-NEXT:    ret
46  %out = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpeq.nxv2i64(<vscale x 2 x i1> %pg,
47                                                                <vscale x 2 x i64> %a,
48                                                                <vscale x 2 x i64> %b)
49  ret <vscale x 2 x i1> %out
50}
51
52define <vscale x 16 x i1> @cmpeq_wide_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) {
53; CHECK-LABEL: cmpeq_wide_b:
54; CHECK:       // %bb.0:
55; CHECK-NEXT:    cmpeq p0.b, p0/z, z0.b, z1.d
56; CHECK-NEXT:    ret
57  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.wide.nxv16i8(<vscale x 16 x i1> %pg,
58                                                                      <vscale x 16 x i8> %a,
59                                                                      <vscale x 2 x i64> %b)
60  ret <vscale x 16 x i1> %out
61}
62
63define <vscale x 8 x i1> @cmpeq_wide_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b) {
64; CHECK-LABEL: cmpeq_wide_h:
65; CHECK:       // %bb.0:
66; CHECK-NEXT:    cmpeq p0.h, p0/z, z0.h, z1.d
67; CHECK-NEXT:    ret
68  %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpeq.wide.nxv8i16(<vscale x 8 x i1> %pg,
69                                                                     <vscale x 8 x i16> %a,
70                                                                     <vscale x 2 x i64> %b)
71  ret <vscale x 8 x i1> %out
72}
73
74define <vscale x 4 x i1> @cmpeq_wide_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
75; CHECK-LABEL: cmpeq_wide_s:
76; CHECK:       // %bb.0:
77; CHECK-NEXT:    cmpeq p0.s, p0/z, z0.s, z1.d
78; CHECK-NEXT:    ret
79  %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpeq.wide.nxv4i32(<vscale x 4 x i1> %pg,
80                                                                     <vscale x 4 x i32> %a,
81                                                                     <vscale x 2 x i64> %b)
82  ret <vscale x 4 x i1> %out
83}
84
85define <vscale x 16 x i1> @cmpeq_ir_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
86; CHECK-LABEL: cmpeq_ir_b:
87; CHECK:       // %bb.0:
88; CHECK-NEXT:    ptrue p0.b
89; CHECK-NEXT:    cmpeq p0.b, p0/z, z0.b, z1.b
90; CHECK-NEXT:    ret
91  %out = icmp eq <vscale x 16 x i8> %a, %b
92  ret <vscale x 16 x i1> %out
93}
94
95define <vscale x 8 x i1> @cmpeq_ir_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
96; CHECK-LABEL: cmpeq_ir_h:
97; CHECK:       // %bb.0:
98; CHECK-NEXT:    ptrue p0.h
99; CHECK-NEXT:    cmpeq p0.h, p0/z, z0.h, z1.h
100; CHECK-NEXT:    ret
101  %out = icmp eq <vscale x 8 x i16> %a, %b
102  ret <vscale x 8 x i1> %out
103}
104
105define <vscale x 4 x i1> @cmpeq_ir_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
106; CHECK-LABEL: cmpeq_ir_s:
107; CHECK:       // %bb.0:
108; CHECK-NEXT:    ptrue p0.s
109; CHECK-NEXT:    cmpeq p0.s, p0/z, z0.s, z1.s
110; CHECK-NEXT:    ret
111  %out = icmp eq <vscale x 4 x i32> %a, %b
112  ret <vscale x 4 x i1> %out
113}
114
115define <vscale x 2 x i1> @cmpeq_ir_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
116; CHECK-LABEL: cmpeq_ir_d:
117; CHECK:       // %bb.0:
118; CHECK-NEXT:    ptrue p0.d
119; CHECK-NEXT:    cmpeq p0.d, p0/z, z0.d, z1.d
120; CHECK-NEXT:    ret
121  %out = icmp eq <vscale x 2 x i64> %a, %b
122  ret <vscale x 2 x i1> %out
123}
124
125;
126; CMPGE
127;
128
129define <vscale x 16 x i1> @cmpge_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
130; CHECK-LABEL: cmpge_b:
131; CHECK:       // %bb.0:
132; CHECK-NEXT:    cmpge p0.b, p0/z, z0.b, z1.b
133; CHECK-NEXT:    ret
134  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.nxv16i8(<vscale x 16 x i1> %pg,
135                                                                 <vscale x 16 x i8> %a,
136                                                                 <vscale x 16 x i8> %b)
137  ret <vscale x 16 x i1> %out
138}
139
140define <vscale x 8 x i1> @cmpge_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
141; CHECK-LABEL: cmpge_h:
142; CHECK:       // %bb.0:
143; CHECK-NEXT:    cmpge p0.h, p0/z, z0.h, z1.h
144; CHECK-NEXT:    ret
145  %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpge.nxv8i16(<vscale x 8 x i1> %pg,
146                                                                <vscale x 8 x i16> %a,
147                                                                <vscale x 8 x i16> %b)
148  ret <vscale x 8 x i1> %out
149}
150
151define <vscale x 4 x i1> @cmpge_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
152; CHECK-LABEL: cmpge_s:
153; CHECK:       // %bb.0:
154; CHECK-NEXT:    cmpge p0.s, p0/z, z0.s, z1.s
155; CHECK-NEXT:    ret
156  %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpge.nxv4i32(<vscale x 4 x i1> %pg,
157                                                                <vscale x 4 x i32> %a,
158                                                                <vscale x 4 x i32> %b)
159  ret <vscale x 4 x i1> %out
160}
161
162define <vscale x 2 x i1> @cmpge_d(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
163; CHECK-LABEL: cmpge_d:
164; CHECK:       // %bb.0:
165; CHECK-NEXT:    cmpge p0.d, p0/z, z0.d, z1.d
166; CHECK-NEXT:    ret
167  %out = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpge.nxv2i64(<vscale x 2 x i1> %pg,
168                                                                <vscale x 2 x i64> %a,
169                                                                <vscale x 2 x i64> %b)
170  ret <vscale x 2 x i1> %out
171}
172
173define <vscale x 16 x i1> @cmpge_wide_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) {
174; CHECK-LABEL: cmpge_wide_b:
175; CHECK:       // %bb.0:
176; CHECK-NEXT:    cmpge p0.b, p0/z, z0.b, z1.d
177; CHECK-NEXT:    ret
178  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.wide.nxv16i8(<vscale x 16 x i1> %pg,
179                                                                      <vscale x 16 x i8> %a,
180                                                                      <vscale x 2 x i64> %b)
181  ret <vscale x 16 x i1> %out
182}
183
184define <vscale x 8 x i1> @cmpge_wide_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b) {
185; CHECK-LABEL: cmpge_wide_h:
186; CHECK:       // %bb.0:
187; CHECK-NEXT:    cmpge p0.h, p0/z, z0.h, z1.d
188; CHECK-NEXT:    ret
189  %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpge.wide.nxv8i16(<vscale x 8 x i1> %pg,
190                                                                     <vscale x 8 x i16> %a,
191                                                                     <vscale x 2 x i64> %b)
192  ret <vscale x 8 x i1> %out
193}
194
195define <vscale x 4 x i1> @cmpge_wide_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
196; CHECK-LABEL: cmpge_wide_s:
197; CHECK:       // %bb.0:
198; CHECK-NEXT:    cmpge p0.s, p0/z, z0.s, z1.d
199; CHECK-NEXT:    ret
200  %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpge.wide.nxv4i32(<vscale x 4 x i1> %pg,
201                                                                     <vscale x 4 x i32> %a,
202                                                                     <vscale x 2 x i64> %b)
203  ret <vscale x 4 x i1> %out
204}
205
206define <vscale x 16 x i1> @cmpge_ir_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
207; CHECK-LABEL: cmpge_ir_b:
208; CHECK:       // %bb.0:
209; CHECK-NEXT:    ptrue p0.b
210; CHECK-NEXT:    cmpge p0.b, p0/z, z0.b, z1.b
211; CHECK-NEXT:    ret
212  %out = icmp sge <vscale x 16 x i8> %a, %b
213  ret <vscale x 16 x i1> %out
214}
215
216define <vscale x 8 x i1> @cmpge_ir_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
217; CHECK-LABEL: cmpge_ir_h:
218; CHECK:       // %bb.0:
219; CHECK-NEXT:    ptrue p0.h
220; CHECK-NEXT:    cmpge p0.h, p0/z, z0.h, z1.h
221; CHECK-NEXT:    ret
222  %out = icmp sge <vscale x 8 x i16> %a, %b
223  ret <vscale x 8 x i1> %out
224}
225
226define <vscale x 4 x i1> @cmpge_ir_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
227; CHECK-LABEL: cmpge_ir_s:
228; CHECK:       // %bb.0:
229; CHECK-NEXT:    ptrue p0.s
230; CHECK-NEXT:    cmpge p0.s, p0/z, z0.s, z1.s
231; CHECK-NEXT:    ret
232  %out = icmp sge <vscale x 4 x i32> %a, %b
233  ret <vscale x 4 x i1> %out
234}
235
236define <vscale x 2 x i1> @cmpge_ir_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
237; CHECK-LABEL: cmpge_ir_d:
238; CHECK:       // %bb.0:
239; CHECK-NEXT:    ptrue p0.d
240; CHECK-NEXT:    cmpge p0.d, p0/z, z0.d, z1.d
241; CHECK-NEXT:    ret
242  %out = icmp sge <vscale x 2 x i64> %a, %b
243  ret <vscale x 2 x i1> %out
244}
245
246define <vscale x 16 x i1> @cmpge_ir_comm_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
247; CHECK-LABEL: cmpge_ir_comm_b:
248; CHECK:       // %bb.0:
249; CHECK-NEXT:    ptrue p0.b
250; CHECK-NEXT:    cmpge p0.b, p0/z, z1.b, z0.b
251; CHECK-NEXT:    ret
252  %out = icmp sle <vscale x 16 x i8> %a, %b
253  ret <vscale x 16 x i1> %out
254}
255
256define <vscale x 8 x i1> @cmpge_ir_comm_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
257; CHECK-LABEL: cmpge_ir_comm_h:
258; CHECK:       // %bb.0:
259; CHECK-NEXT:    ptrue p0.h
260; CHECK-NEXT:    cmpge p0.h, p0/z, z1.h, z0.h
261; CHECK-NEXT:    ret
262  %out = icmp sle <vscale x 8 x i16> %a, %b
263  ret <vscale x 8 x i1> %out
264}
265
266define <vscale x 4 x i1> @cmpge_ir_comm_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
267; CHECK-LABEL: cmpge_ir_comm_s:
268; CHECK:       // %bb.0:
269; CHECK-NEXT:    ptrue p0.s
270; CHECK-NEXT:    cmpge p0.s, p0/z, z1.s, z0.s
271; CHECK-NEXT:    ret
272  %out = icmp sle <vscale x 4 x i32> %a, %b
273  ret <vscale x 4 x i1> %out
274}
275
276define <vscale x 2 x i1> @cmpge_ir_comm_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
277; CHECK-LABEL: cmpge_ir_comm_d:
278; CHECK:       // %bb.0:
279; CHECK-NEXT:    ptrue p0.d
280; CHECK-NEXT:    cmpge p0.d, p0/z, z1.d, z0.d
281; CHECK-NEXT:    ret
282  %out = icmp sle <vscale x 2 x i64> %a, %b
283  ret <vscale x 2 x i1> %out
284}
285
286;
287; CMPGT
288;
289
290define <vscale x 16 x i1> @cmpgt_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
291; CHECK-LABEL: cmpgt_b:
292; CHECK:       // %bb.0:
293; CHECK-NEXT:    cmpgt p0.b, p0/z, z0.b, z1.b
294; CHECK-NEXT:    ret
295  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.nxv16i8(<vscale x 16 x i1> %pg,
296                                                                 <vscale x 16 x i8> %a,
297                                                                 <vscale x 16 x i8> %b)
298  ret <vscale x 16 x i1> %out
299}
300
301define <vscale x 8 x i1> @cmpgt_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
302; CHECK-LABEL: cmpgt_h:
303; CHECK:       // %bb.0:
304; CHECK-NEXT:    cmpgt p0.h, p0/z, z0.h, z1.h
305; CHECK-NEXT:    ret
306  %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpgt.nxv8i16(<vscale x 8 x i1> %pg,
307                                                                <vscale x 8 x i16> %a,
308                                                                <vscale x 8 x i16> %b)
309  ret <vscale x 8 x i1> %out
310}
311
312define <vscale x 4 x i1> @cmpgt_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
313; CHECK-LABEL: cmpgt_s:
314; CHECK:       // %bb.0:
315; CHECK-NEXT:    cmpgt p0.s, p0/z, z0.s, z1.s
316; CHECK-NEXT:    ret
317  %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.nxv4i32(<vscale x 4 x i1> %pg,
318                                                                <vscale x 4 x i32> %a,
319                                                                <vscale x 4 x i32> %b)
320  ret <vscale x 4 x i1> %out
321}
322
323define <vscale x 2 x i1> @cmpgt_d(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
324; CHECK-LABEL: cmpgt_d:
325; CHECK:       // %bb.0:
326; CHECK-NEXT:    cmpgt p0.d, p0/z, z0.d, z1.d
327; CHECK-NEXT:    ret
328  %out = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpgt.nxv2i64(<vscale x 2 x i1> %pg,
329                                                                <vscale x 2 x i64> %a,
330                                                                <vscale x 2 x i64> %b)
331  ret <vscale x 2 x i1> %out
332}
333
334define <vscale x 16 x i1> @cmpgt_wide_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) {
335; CHECK-LABEL: cmpgt_wide_b:
336; CHECK:       // %bb.0:
337; CHECK-NEXT:    cmpgt p0.b, p0/z, z0.b, z1.d
338; CHECK-NEXT:    ret
339  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.wide.nxv16i8(<vscale x 16 x i1> %pg,
340                                                                      <vscale x 16 x i8> %a,
341                                                                      <vscale x 2 x i64> %b)
342  ret <vscale x 16 x i1> %out
343}
344
345define <vscale x 8 x i1> @cmpgt_wide_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b) {
346; CHECK-LABEL: cmpgt_wide_h:
347; CHECK:       // %bb.0:
348; CHECK-NEXT:    cmpgt p0.h, p0/z, z0.h, z1.d
349; CHECK-NEXT:    ret
350  %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpgt.wide.nxv8i16(<vscale x 8 x i1> %pg,
351                                                                     <vscale x 8 x i16> %a,
352                                                                     <vscale x 2 x i64> %b)
353  ret <vscale x 8 x i1> %out
354}
355
356define <vscale x 4 x i1> @cmpgt_wide_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
357; CHECK-LABEL: cmpgt_wide_s:
358; CHECK:       // %bb.0:
359; CHECK-NEXT:    cmpgt p0.s, p0/z, z0.s, z1.d
360; CHECK-NEXT:    ret
361  %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.wide.nxv4i32(<vscale x 4 x i1> %pg,
362                                                                     <vscale x 4 x i32> %a,
363                                                                     <vscale x 2 x i64> %b)
364  ret <vscale x 4 x i1> %out
365}
366
367define <vscale x 16 x i1> @cmpgt_ir_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
368; CHECK-LABEL: cmpgt_ir_b:
369; CHECK:       // %bb.0:
370; CHECK-NEXT:    ptrue p0.b
371; CHECK-NEXT:    cmpgt p0.b, p0/z, z0.b, z1.b
372; CHECK-NEXT:    ret
373  %out = icmp sgt <vscale x 16 x i8> %a, %b
374  ret <vscale x 16 x i1> %out
375}
376
377define <vscale x 8 x i1> @cmpgt_ir_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
378; CHECK-LABEL: cmpgt_ir_h:
379; CHECK:       // %bb.0:
380; CHECK-NEXT:    ptrue p0.h
381; CHECK-NEXT:    cmpgt p0.h, p0/z, z0.h, z1.h
382; CHECK-NEXT:    ret
383  %out = icmp sgt <vscale x 8 x i16> %a, %b
384  ret <vscale x 8 x i1> %out
385}
386
387define <vscale x 4 x i1> @cmpgt_ir_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
388; CHECK-LABEL: cmpgt_ir_s:
389; CHECK:       // %bb.0:
390; CHECK-NEXT:    ptrue p0.s
391; CHECK-NEXT:    cmpgt p0.s, p0/z, z0.s, z1.s
392; CHECK-NEXT:    ret
393  %out = icmp sgt <vscale x 4 x i32> %a, %b
394  ret <vscale x 4 x i1> %out
395}
396
397define <vscale x 2 x i1> @cmpgt_ir_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
398; CHECK-LABEL: cmpgt_ir_d:
399; CHECK:       // %bb.0:
400; CHECK-NEXT:    ptrue p0.d
401; CHECK-NEXT:    cmpgt p0.d, p0/z, z0.d, z1.d
402; CHECK-NEXT:    ret
403  %out = icmp sgt <vscale x 2 x i64> %a, %b
404  ret <vscale x 2 x i1> %out
405}
406
407define <vscale x 16 x i1> @cmpgt_ir_comm_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
408; CHECK-LABEL: cmpgt_ir_comm_b:
409; CHECK:       // %bb.0:
410; CHECK-NEXT:    ptrue p0.b
411; CHECK-NEXT:    cmpgt p0.b, p0/z, z1.b, z0.b
412; CHECK-NEXT:    ret
413  %out = icmp slt <vscale x 16 x i8> %a, %b
414  ret <vscale x 16 x i1> %out
415}
416
417define <vscale x 8 x i1> @cmpgt_ir_comm_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
418; CHECK-LABEL: cmpgt_ir_comm_h:
419; CHECK:       // %bb.0:
420; CHECK-NEXT:    ptrue p0.h
421; CHECK-NEXT:    cmpgt p0.h, p0/z, z1.h, z0.h
422; CHECK-NEXT:    ret
423  %out = icmp slt <vscale x 8 x i16> %a, %b
424  ret <vscale x 8 x i1> %out
425}
426
427define <vscale x 4 x i1> @cmpgt_ir_comm_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
428; CHECK-LABEL: cmpgt_ir_comm_s:
429; CHECK:       // %bb.0:
430; CHECK-NEXT:    ptrue p0.s
431; CHECK-NEXT:    cmpgt p0.s, p0/z, z1.s, z0.s
432; CHECK-NEXT:    ret
433  %out = icmp slt <vscale x 4 x i32> %a, %b
434  ret <vscale x 4 x i1> %out
435}
436
437define <vscale x 2 x i1> @cmpgt_ir_comm_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
438; CHECK-LABEL: cmpgt_ir_comm_d:
439; CHECK:       // %bb.0:
440; CHECK-NEXT:    ptrue p0.d
441; CHECK-NEXT:    cmpgt p0.d, p0/z, z1.d, z0.d
442; CHECK-NEXT:    ret
443  %out = icmp slt <vscale x 2 x i64> %a, %b
444  ret <vscale x 2 x i1> %out
445}
446
447;
448; CMPHI
449;
450
451define <vscale x 16 x i1> @cmphi_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
452; CHECK-LABEL: cmphi_b:
453; CHECK:       // %bb.0:
454; CHECK-NEXT:    cmphi p0.b, p0/z, z0.b, z1.b
455; CHECK-NEXT:    ret
456  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.nxv16i8(<vscale x 16 x i1> %pg,
457                                                                 <vscale x 16 x i8> %a,
458                                                                 <vscale x 16 x i8> %b)
459  ret <vscale x 16 x i1> %out
460}
461
462define <vscale x 8 x i1> @cmphi_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
463; CHECK-LABEL: cmphi_h:
464; CHECK:       // %bb.0:
465; CHECK-NEXT:    cmphi p0.h, p0/z, z0.h, z1.h
466; CHECK-NEXT:    ret
467  %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmphi.nxv8i16(<vscale x 8 x i1> %pg,
468                                                                <vscale x 8 x i16> %a,
469                                                                <vscale x 8 x i16> %b)
470  ret <vscale x 8 x i1> %out
471}
472
473define <vscale x 4 x i1> @cmphi_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
474; CHECK-LABEL: cmphi_s:
475; CHECK:       // %bb.0:
476; CHECK-NEXT:    cmphi p0.s, p0/z, z0.s, z1.s
477; CHECK-NEXT:    ret
478  %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.nxv4i32(<vscale x 4 x i1> %pg,
479                                                                <vscale x 4 x i32> %a,
480                                                                <vscale x 4 x i32> %b)
481  ret <vscale x 4 x i1> %out
482}
483
484define <vscale x 2 x i1> @cmphi_d(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
485; CHECK-LABEL: cmphi_d:
486; CHECK:       // %bb.0:
487; CHECK-NEXT:    cmphi p0.d, p0/z, z0.d, z1.d
488; CHECK-NEXT:    ret
489  %out = call <vscale x 2 x i1> @llvm.aarch64.sve.cmphi.nxv2i64(<vscale x 2 x i1> %pg,
490                                                                <vscale x 2 x i64> %a,
491                                                                <vscale x 2 x i64> %b)
492  ret <vscale x 2 x i1> %out
493}
494
495define <vscale x 16 x i1> @cmphi_wide_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) {
496; CHECK-LABEL: cmphi_wide_b:
497; CHECK:       // %bb.0:
498; CHECK-NEXT:    cmphi p0.b, p0/z, z0.b, z1.d
499; CHECK-NEXT:    ret
500  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.wide.nxv16i8(<vscale x 16 x i1> %pg,
501                                                                      <vscale x 16 x i8> %a,
502                                                                      <vscale x 2 x i64> %b)
503  ret <vscale x 16 x i1> %out
504}
505
506define <vscale x 8 x i1> @cmphi_wide_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b) {
507; CHECK-LABEL: cmphi_wide_h:
508; CHECK:       // %bb.0:
509; CHECK-NEXT:    cmphi p0.h, p0/z, z0.h, z1.d
510; CHECK-NEXT:    ret
511  %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmphi.wide.nxv8i16(<vscale x 8 x i1> %pg,
512                                                                     <vscale x 8 x i16> %a,
513                                                                     <vscale x 2 x i64> %b)
514  ret <vscale x 8 x i1> %out
515}
516
517define <vscale x 4 x i1> @cmphi_wide_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
518; CHECK-LABEL: cmphi_wide_s:
519; CHECK:       // %bb.0:
520; CHECK-NEXT:    cmphi p0.s, p0/z, z0.s, z1.d
521; CHECK-NEXT:    ret
522  %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.wide.nxv4i32(<vscale x 4 x i1> %pg,
523                                                                     <vscale x 4 x i32> %a,
524                                                                     <vscale x 2 x i64> %b)
525  ret <vscale x 4 x i1> %out
526}
527
528define <vscale x 16 x i1> @cmphi_ir_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
529; CHECK-LABEL: cmphi_ir_b:
530; CHECK:       // %bb.0:
531; CHECK-NEXT:    ptrue p0.b
532; CHECK-NEXT:    cmphi p0.b, p0/z, z0.b, z1.b
533; CHECK-NEXT:    ret
534  %out = icmp ugt <vscale x 16 x i8> %a, %b
535  ret <vscale x 16 x i1> %out
536}
537
538define <vscale x 8 x i1> @cmphi_ir_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
539; CHECK-LABEL: cmphi_ir_h:
540; CHECK:       // %bb.0:
541; CHECK-NEXT:    ptrue p0.h
542; CHECK-NEXT:    cmphi p0.h, p0/z, z0.h, z1.h
543; CHECK-NEXT:    ret
544  %out = icmp ugt <vscale x 8 x i16> %a, %b
545  ret <vscale x 8 x i1> %out
546}
547
548define <vscale x 4 x i1> @cmphi_ir_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
549; CHECK-LABEL: cmphi_ir_s:
550; CHECK:       // %bb.0:
551; CHECK-NEXT:    ptrue p0.s
552; CHECK-NEXT:    cmphi p0.s, p0/z, z0.s, z1.s
553; CHECK-NEXT:    ret
554  %out = icmp ugt <vscale x 4 x i32> %a, %b
555  ret <vscale x 4 x i1> %out
556}
557
558define <vscale x 2 x i1> @cmphi_ir_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
559; CHECK-LABEL: cmphi_ir_d:
560; CHECK:       // %bb.0:
561; CHECK-NEXT:    ptrue p0.d
562; CHECK-NEXT:    cmphi p0.d, p0/z, z0.d, z1.d
563; CHECK-NEXT:    ret
564  %out = icmp ugt <vscale x 2 x i64> %a, %b
565  ret <vscale x 2 x i1> %out
566}
567
568define <vscale x 16 x i1> @cmphi_ir_comm_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
569; CHECK-LABEL: cmphi_ir_comm_b:
570; CHECK:       // %bb.0:
571; CHECK-NEXT:    ptrue p0.b
572; CHECK-NEXT:    cmphi p0.b, p0/z, z1.b, z0.b
573; CHECK-NEXT:    ret
574  %out = icmp ult <vscale x 16 x i8> %a, %b
575  ret <vscale x 16 x i1> %out
576}
577
578define <vscale x 8 x i1> @cmphi_ir_comm_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
579; CHECK-LABEL: cmphi_ir_comm_h:
580; CHECK:       // %bb.0:
581; CHECK-NEXT:    ptrue p0.h
582; CHECK-NEXT:    cmphi p0.h, p0/z, z1.h, z0.h
583; CHECK-NEXT:    ret
584  %out = icmp ult <vscale x 8 x i16> %a, %b
585  ret <vscale x 8 x i1> %out
586}
587
588define <vscale x 4 x i1> @cmphi_ir_comm_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
589; CHECK-LABEL: cmphi_ir_comm_s:
590; CHECK:       // %bb.0:
591; CHECK-NEXT:    ptrue p0.s
592; CHECK-NEXT:    cmphi p0.s, p0/z, z1.s, z0.s
593; CHECK-NEXT:    ret
594  %out = icmp ult <vscale x 4 x i32> %a, %b
595  ret <vscale x 4 x i1> %out
596}
597
598define <vscale x 2 x i1> @cmphi_ir_comm_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
599; CHECK-LABEL: cmphi_ir_comm_d:
600; CHECK:       // %bb.0:
601; CHECK-NEXT:    ptrue p0.d
602; CHECK-NEXT:    cmphi p0.d, p0/z, z1.d, z0.d
603; CHECK-NEXT:    ret
604  %out = icmp ult <vscale x 2 x i64> %a, %b
605  ret <vscale x 2 x i1> %out
606}
607
608;
609; CMPHS
610;
611
612define <vscale x 16 x i1> @cmphs_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
613; CHECK-LABEL: cmphs_b:
614; CHECK:       // %bb.0:
615; CHECK-NEXT:    cmphs p0.b, p0/z, z0.b, z1.b
616; CHECK-NEXT:    ret
617  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphs.nxv16i8(<vscale x 16 x i1> %pg,
618                                                                 <vscale x 16 x i8> %a,
619                                                                 <vscale x 16 x i8> %b)
620  ret <vscale x 16 x i1> %out
621}
622
623define <vscale x 8 x i1> @cmphs_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
624; CHECK-LABEL: cmphs_h:
625; CHECK:       // %bb.0:
626; CHECK-NEXT:    cmphs p0.h, p0/z, z0.h, z1.h
627; CHECK-NEXT:    ret
628  %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmphs.nxv8i16(<vscale x 8 x i1> %pg,
629                                                                <vscale x 8 x i16> %a,
630                                                                <vscale x 8 x i16> %b)
631  ret <vscale x 8 x i1> %out
632}
633
634define <vscale x 4 x i1> @cmphs_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
635; CHECK-LABEL: cmphs_s:
636; CHECK:       // %bb.0:
637; CHECK-NEXT:    cmphs p0.s, p0/z, z0.s, z1.s
638; CHECK-NEXT:    ret
639  %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.nxv4i32(<vscale x 4 x i1> %pg,
640                                                                <vscale x 4 x i32> %a,
641                                                                <vscale x 4 x i32> %b)
642  ret <vscale x 4 x i1> %out
643}
644
645define <vscale x 2 x i1> @cmphs_d(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
646; CHECK-LABEL: cmphs_d:
647; CHECK:       // %bb.0:
648; CHECK-NEXT:    cmphs p0.d, p0/z, z0.d, z1.d
649; CHECK-NEXT:    ret
650  %out = call <vscale x 2 x i1> @llvm.aarch64.sve.cmphs.nxv2i64(<vscale x 2 x i1> %pg,
651                                                                <vscale x 2 x i64> %a,
652                                                                <vscale x 2 x i64> %b)
653  ret <vscale x 2 x i1> %out
654}
655
656define <vscale x 16 x i1> @cmphs_wide_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) {
657; CHECK-LABEL: cmphs_wide_b:
658; CHECK:       // %bb.0:
659; CHECK-NEXT:    cmphs p0.b, p0/z, z0.b, z1.d
660; CHECK-NEXT:    ret
661  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphs.wide.nxv16i8(<vscale x 16 x i1> %pg,
662                                                                      <vscale x 16 x i8> %a,
663                                                                      <vscale x 2 x i64> %b)
664  ret <vscale x 16 x i1> %out
665}
666
667define <vscale x 8 x i1> @cmphs_wide_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b) {
668; CHECK-LABEL: cmphs_wide_h:
669; CHECK:       // %bb.0:
670; CHECK-NEXT:    cmphs p0.h, p0/z, z0.h, z1.d
671; CHECK-NEXT:    ret
672  %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmphs.wide.nxv8i16(<vscale x 8 x i1> %pg,
673                                                                     <vscale x 8 x i16> %a,
674                                                                     <vscale x 2 x i64> %b)
675  ret <vscale x 8 x i1> %out
676}
677
678define <vscale x 4 x i1> @cmphs_wide_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
679; CHECK-LABEL: cmphs_wide_s:
680; CHECK:       // %bb.0:
681; CHECK-NEXT:    cmphs p0.s, p0/z, z0.s, z1.d
682; CHECK-NEXT:    ret
683  %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.wide.nxv4i32(<vscale x 4 x i1> %pg,
684                                                                     <vscale x 4 x i32> %a,
685                                                                     <vscale x 2 x i64> %b)
686  ret <vscale x 4 x i1> %out
687}
688
689define <vscale x 16 x i1> @cmphs_ir_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
690; CHECK-LABEL: cmphs_ir_b:
691; CHECK:       // %bb.0:
692; CHECK-NEXT:    ptrue p0.b
693; CHECK-NEXT:    cmphs p0.b, p0/z, z0.b, z1.b
694; CHECK-NEXT:    ret
695  %out = icmp uge <vscale x 16 x i8> %a, %b
696  ret <vscale x 16 x i1> %out
697}
698
699define <vscale x 8 x i1> @cmphs_ir_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
700; CHECK-LABEL: cmphs_ir_h:
701; CHECK:       // %bb.0:
702; CHECK-NEXT:    ptrue p0.h
703; CHECK-NEXT:    cmphs p0.h, p0/z, z0.h, z1.h
704; CHECK-NEXT:    ret
705  %out = icmp uge <vscale x 8 x i16> %a, %b
706  ret <vscale x 8 x i1> %out
707}
708
709define <vscale x 4 x i1> @cmphs_ir_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
710; CHECK-LABEL: cmphs_ir_s:
711; CHECK:       // %bb.0:
712; CHECK-NEXT:    ptrue p0.s
713; CHECK-NEXT:    cmphs p0.s, p0/z, z0.s, z1.s
714; CHECK-NEXT:    ret
715  %out = icmp uge <vscale x 4 x i32> %a, %b
716  ret <vscale x 4 x i1> %out
717}
718
719define <vscale x 2 x i1> @cmphs_ir_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
720; CHECK-LABEL: cmphs_ir_d:
721; CHECK:       // %bb.0:
722; CHECK-NEXT:    ptrue p0.d
723; CHECK-NEXT:    cmphs p0.d, p0/z, z0.d, z1.d
724; CHECK-NEXT:    ret
725  %out = icmp uge <vscale x 2 x i64> %a, %b
726  ret <vscale x 2 x i1> %out
727}
728
729define <vscale x 16 x i1> @cmphs_ir_comm_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
730; CHECK-LABEL: cmphs_ir_comm_b:
731; CHECK:       // %bb.0:
732; CHECK-NEXT:    ptrue p0.b
733; CHECK-NEXT:    cmphs p0.b, p0/z, z1.b, z0.b
734; CHECK-NEXT:    ret
735  %out = icmp ule <vscale x 16 x i8> %a, %b
736  ret <vscale x 16 x i1> %out
737}
738
739define <vscale x 8 x i1> @cmphs_ir_comm_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
740; CHECK-LABEL: cmphs_ir_comm_h:
741; CHECK:       // %bb.0:
742; CHECK-NEXT:    ptrue p0.h
743; CHECK-NEXT:    cmphs p0.h, p0/z, z1.h, z0.h
744; CHECK-NEXT:    ret
745  %out = icmp ule <vscale x 8 x i16> %a, %b
746  ret <vscale x 8 x i1> %out
747}
748
749define <vscale x 4 x i1> @cmphs_ir_comm_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
750; CHECK-LABEL: cmphs_ir_comm_s:
751; CHECK:       // %bb.0:
752; CHECK-NEXT:    ptrue p0.s
753; CHECK-NEXT:    cmphs p0.s, p0/z, z1.s, z0.s
754; CHECK-NEXT:    ret
755  %out = icmp ule <vscale x 4 x i32> %a, %b
756  ret <vscale x 4 x i1> %out
757}
758
759define <vscale x 2 x i1> @cmphs_ir_comm_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
760; CHECK-LABEL: cmphs_ir_comm_d:
761; CHECK:       // %bb.0:
762; CHECK-NEXT:    ptrue p0.d
763; CHECK-NEXT:    cmphs p0.d, p0/z, z1.d, z0.d
764; CHECK-NEXT:    ret
765  %out = icmp ule <vscale x 2 x i64> %a, %b
766  ret <vscale x 2 x i1> %out
767}
768
769;
770; CMPLE
771;
772
773define <vscale x 16 x i1> @cmple_wide_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) {
774; CHECK-LABEL: cmple_wide_b:
775; CHECK:       // %bb.0:
776; CHECK-NEXT:    cmple p0.b, p0/z, z0.b, z1.d
777; CHECK-NEXT:    ret
778  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmple.wide.nxv16i8(<vscale x 16 x i1> %pg,
779                                                                      <vscale x 16 x i8> %a,
780                                                                      <vscale x 2 x i64> %b)
781  ret <vscale x 16 x i1> %out
782}
783
784define <vscale x 8 x i1> @cmple_wide_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b) {
785; CHECK-LABEL: cmple_wide_h:
786; CHECK:       // %bb.0:
787; CHECK-NEXT:    cmple p0.h, p0/z, z0.h, z1.d
788; CHECK-NEXT:    ret
789  %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmple.wide.nxv8i16(<vscale x 8 x i1> %pg,
790                                                                     <vscale x 8 x i16> %a,
791                                                                     <vscale x 2 x i64> %b)
792  ret <vscale x 8 x i1> %out
793}
794
795define <vscale x 4 x i1> @cmple_wide_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
796; CHECK-LABEL: cmple_wide_s:
797; CHECK:       // %bb.0:
798; CHECK-NEXT:    cmple p0.s, p0/z, z0.s, z1.d
799; CHECK-NEXT:    ret
800  %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmple.wide.nxv4i32(<vscale x 4 x i1> %pg,
801                                                                     <vscale x 4 x i32> %a,
802                                                                     <vscale x 2 x i64> %b)
803  ret <vscale x 4 x i1> %out
804}
805
806;
807; CMPLO
808;
809
810define <vscale x 16 x i1> @cmplo_wide_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) {
811; CHECK-LABEL: cmplo_wide_b:
812; CHECK:       // %bb.0:
813; CHECK-NEXT:    cmplo p0.b, p0/z, z0.b, z1.d
814; CHECK-NEXT:    ret
815  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmplo.wide.nxv16i8(<vscale x 16 x i1> %pg,
816                                                                      <vscale x 16 x i8> %a,
817                                                                      <vscale x 2 x i64> %b)
818  ret <vscale x 16 x i1> %out
819}
820
821define <vscale x 8 x i1> @cmplo_wide_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b) {
822; CHECK-LABEL: cmplo_wide_h:
823; CHECK:       // %bb.0:
824; CHECK-NEXT:    cmplo p0.h, p0/z, z0.h, z1.d
825; CHECK-NEXT:    ret
826  %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmplo.wide.nxv8i16(<vscale x 8 x i1> %pg,
827                                                                     <vscale x 8 x i16> %a,
828                                                                     <vscale x 2 x i64> %b)
829  ret <vscale x 8 x i1> %out
830}
831
832define <vscale x 4 x i1> @cmplo_wide_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
833; CHECK-LABEL: cmplo_wide_s:
834; CHECK:       // %bb.0:
835; CHECK-NEXT:    cmplo p0.s, p0/z, z0.s, z1.d
836; CHECK-NEXT:    ret
837  %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmplo.wide.nxv4i32(<vscale x 4 x i1> %pg,
838                                                                     <vscale x 4 x i32> %a,
839                                                                     <vscale x 2 x i64> %b)
840  ret <vscale x 4 x i1> %out
841}
842
843;
844; CMPLS
845;
846
847define <vscale x 16 x i1> @cmpls_wide_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) {
848; CHECK-LABEL: cmpls_wide_b:
849; CHECK:       // %bb.0:
850; CHECK-NEXT:    cmpls p0.b, p0/z, z0.b, z1.d
851; CHECK-NEXT:    ret
852  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpls.wide.nxv16i8(<vscale x 16 x i1> %pg,
853                                                                      <vscale x 16 x i8> %a,
854                                                                      <vscale x 2 x i64> %b)
855  ret <vscale x 16 x i1> %out
856}
857
858define <vscale x 8 x i1> @cmpls_wide_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b) {
859; CHECK-LABEL: cmpls_wide_h:
860; CHECK:       // %bb.0:
861; CHECK-NEXT:    cmpls p0.h, p0/z, z0.h, z1.d
862; CHECK-NEXT:    ret
863  %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpls.wide.nxv8i16(<vscale x 8 x i1> %pg,
864                                                                     <vscale x 8 x i16> %a,
865                                                                     <vscale x 2 x i64> %b)
866  ret <vscale x 8 x i1> %out
867}
868
869define <vscale x 4 x i1> @cmpls_wide_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
870; CHECK-LABEL: cmpls_wide_s:
871; CHECK:       // %bb.0:
872; CHECK-NEXT:    cmpls p0.s, p0/z, z0.s, z1.d
873; CHECK-NEXT:    ret
874  %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpls.wide.nxv4i32(<vscale x 4 x i1> %pg,
875                                                                     <vscale x 4 x i32> %a,
876                                                                     <vscale x 2 x i64> %b)
877  ret <vscale x 4 x i1> %out
878}
879
880;
881; CMPLT
882;
883
884define <vscale x 16 x i1> @cmplt_wide_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) {
885; CHECK-LABEL: cmplt_wide_b:
886; CHECK:       // %bb.0:
887; CHECK-NEXT:    cmplt p0.b, p0/z, z0.b, z1.d
888; CHECK-NEXT:    ret
889  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmplt.wide.nxv16i8(<vscale x 16 x i1> %pg,
890                                                                      <vscale x 16 x i8> %a,
891                                                                      <vscale x 2 x i64> %b)
892  ret <vscale x 16 x i1> %out
893}
894
895define <vscale x 8 x i1> @cmplt_wide_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b) {
896; CHECK-LABEL: cmplt_wide_h:
897; CHECK:       // %bb.0:
898; CHECK-NEXT:    cmplt p0.h, p0/z, z0.h, z1.d
899; CHECK-NEXT:    ret
900  %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmplt.wide.nxv8i16(<vscale x 8 x i1> %pg,
901                                                                     <vscale x 8 x i16> %a,
902                                                                     <vscale x 2 x i64> %b)
903  ret <vscale x 8 x i1> %out
904}
905
906define <vscale x 4 x i1> @cmplt_wide_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
907; CHECK-LABEL: cmplt_wide_s:
908; CHECK:       // %bb.0:
909; CHECK-NEXT:    cmplt p0.s, p0/z, z0.s, z1.d
910; CHECK-NEXT:    ret
911  %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmplt.wide.nxv4i32(<vscale x 4 x i1> %pg,
912                                                                     <vscale x 4 x i32> %a,
913                                                                     <vscale x 2 x i64> %b)
914  ret <vscale x 4 x i1> %out
915}
916
917;
918; CMPNE
919;
920
921define <vscale x 16 x i1> @cmpne_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
922; CHECK-LABEL: cmpne_b:
923; CHECK:       // %bb.0:
924; CHECK-NEXT:    cmpne p0.b, p0/z, z0.b, z1.b
925; CHECK-NEXT:    ret
926  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.nxv16i8(<vscale x 16 x i1> %pg,
927                                                                 <vscale x 16 x i8> %a,
928                                                                 <vscale x 16 x i8> %b)
929  ret <vscale x 16 x i1> %out
930}
931
932define <vscale x 8 x i1> @cmpne_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
933; CHECK-LABEL: cmpne_h:
934; CHECK:       // %bb.0:
935; CHECK-NEXT:    cmpne p0.h, p0/z, z0.h, z1.h
936; CHECK-NEXT:    ret
937  %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1> %pg,
938                                                                <vscale x 8 x i16> %a,
939                                                                <vscale x 8 x i16> %b)
940  ret <vscale x 8 x i1> %out
941}
942
943define <vscale x 4 x i1> @cmpne_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
944; CHECK-LABEL: cmpne_s:
945; CHECK:       // %bb.0:
946; CHECK-NEXT:    cmpne p0.s, p0/z, z0.s, z1.s
947; CHECK-NEXT:    ret
948  %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1> %pg,
949                                                                <vscale x 4 x i32> %a,
950                                                                <vscale x 4 x i32> %b)
951  ret <vscale x 4 x i1> %out
952}
953
954define <vscale x 2 x i1> @cmpne_d(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
955; CHECK-LABEL: cmpne_d:
956; CHECK:       // %bb.0:
957; CHECK-NEXT:    cmpne p0.d, p0/z, z0.d, z1.d
958; CHECK-NEXT:    ret
959  %out = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %pg,
960                                                                <vscale x 2 x i64> %a,
961                                                                <vscale x 2 x i64> %b)
962  ret <vscale x 2 x i1> %out
963}
964
965define <vscale x 16 x i1> @cmpne_wide_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) {
966; CHECK-LABEL: cmpne_wide_b:
967; CHECK:       // %bb.0:
968; CHECK-NEXT:    cmpne p0.b, p0/z, z0.b, z1.d
969; CHECK-NEXT:    ret
970  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.wide.nxv16i8(<vscale x 16 x i1> %pg,
971                                                                      <vscale x 16 x i8> %a,
972                                                                      <vscale x 2 x i64> %b)
973  ret <vscale x 16 x i1> %out
974}
975
976define <vscale x 8 x i1> @cmpne_wide_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b) {
977; CHECK-LABEL: cmpne_wide_h:
978; CHECK:       // %bb.0:
979; CHECK-NEXT:    cmpne p0.h, p0/z, z0.h, z1.d
980; CHECK-NEXT:    ret
981  %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.wide.nxv8i16(<vscale x 8 x i1> %pg,
982                                                                     <vscale x 8 x i16> %a,
983                                                                     <vscale x 2 x i64> %b)
984  ret <vscale x 8 x i1> %out
985}
986
987define <vscale x 4 x i1> @cmpne_wide_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
988; CHECK-LABEL: cmpne_wide_s:
989; CHECK:       // %bb.0:
990; CHECK-NEXT:    cmpne p0.s, p0/z, z0.s, z1.d
991; CHECK-NEXT:    ret
992  %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.wide.nxv4i32(<vscale x 4 x i1> %pg,
993                                                                     <vscale x 4 x i32> %a,
994                                                                     <vscale x 2 x i64> %b)
995  ret <vscale x 4 x i1> %out
996}
997
998define <vscale x 16 x i1> @cmpne_ir_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
999; CHECK-LABEL: cmpne_ir_b:
1000; CHECK:       // %bb.0:
1001; CHECK-NEXT:    ptrue p0.b
1002; CHECK-NEXT:    cmpne p0.b, p0/z, z0.b, z1.b
1003; CHECK-NEXT:    ret
1004  %out = icmp ne <vscale x 16 x i8> %a, %b
1005  ret <vscale x 16 x i1> %out
1006}
1007
1008define <vscale x 8 x i1> @cmpne_ir_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
1009; CHECK-LABEL: cmpne_ir_h:
1010; CHECK:       // %bb.0:
1011; CHECK-NEXT:    ptrue p0.h
1012; CHECK-NEXT:    cmpne p0.h, p0/z, z0.h, z1.h
1013; CHECK-NEXT:    ret
1014  %out = icmp ne <vscale x 8 x i16> %a, %b
1015  ret <vscale x 8 x i1> %out
1016}
1017
1018define <vscale x 4 x i1> @cmpne_ir_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
1019; CHECK-LABEL: cmpne_ir_s:
1020; CHECK:       // %bb.0:
1021; CHECK-NEXT:    ptrue p0.s
1022; CHECK-NEXT:    cmpne p0.s, p0/z, z0.s, z1.s
1023; CHECK-NEXT:    ret
1024  %out = icmp ne <vscale x 4 x i32> %a, %b
1025  ret <vscale x 4 x i1> %out
1026}
1027
1028define <vscale x 2 x i1> @cmpne_ir_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
1029; CHECK-LABEL: cmpne_ir_d:
1030; CHECK:       // %bb.0:
1031; CHECK-NEXT:    ptrue p0.d
1032; CHECK-NEXT:    cmpne p0.d, p0/z, z0.d, z1.d
1033; CHECK-NEXT:    ret
1034  %out = icmp ne <vscale x 2 x i64> %a, %b
1035  ret <vscale x 2 x i1> %out
1036}
1037
1038define <vscale x 1 x i1> @cmpne_ir_q(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b) {
1039; CHECK-LABEL: cmpne_ir_q:
1040; CHECK:       // %bb.0:
1041; CHECK-NEXT:    ptrue p0.d
1042; CHECK-NEXT:    cmpne p0.d, p0/z, z0.d, z1.d
1043; CHECK-NEXT:    punpklo p0.h, p0.b
1044; CHECK-NEXT:    ret
1045  %out = icmp ne <vscale x 1 x i64> %a, %b
1046  ret <vscale x 1 x i1> %out
1047}
1048
1049
1050define <vscale x 16 x i1> @cmpgt_wide_splat_b(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, i64 %b) {
1051; CHECK-LABEL: cmpgt_wide_splat_b:
1052; CHECK:       // %bb.0:
1053; CHECK-NEXT:    mov z1.d, x0
1054; CHECK-NEXT:    cmpgt p0.b, p0/z, z0.b, z1.d
1055; CHECK-NEXT:    ret
1056  %splat = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %b)
1057  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.wide.nxv16i8(<vscale x 16 x i1> %pg,
1058                                                                      <vscale x 16 x i8> %a,
1059                                                                      <vscale x 2 x i64> %splat)
1060  ret <vscale x 16 x i1> %out
1061}
1062
1063define <vscale x 4 x i1> @cmpls_wide_splat_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, i64 %b) {
1064; CHECK-LABEL: cmpls_wide_splat_s:
1065; CHECK:       // %bb.0:
1066; CHECK-NEXT:    mov z1.d, x0
1067; CHECK-NEXT:    cmpls p0.s, p0/z, z0.s, z1.d
1068; CHECK-NEXT:    ret
1069  %splat = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %b)
1070  %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpls.wide.nxv4i32(<vscale x 4 x i1> %pg,
1071                                                                     <vscale x 4 x i32> %a,
1072                                                                     <vscale x 2 x i64> %splat)
1073  ret <vscale x 4 x i1> %out
1074}
1075
1076; Verify general predicate is folded into the compare
1077define <vscale x 4 x i1> @predicated_icmp(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
1078; CHECK-LABEL: predicated_icmp:
1079; CHECK:       // %bb.0:
1080; CHECK-NEXT:    ptrue p0.s
1081; CHECK-NEXT:    cmpgt p0.s, p0/z, z0.s, z1.s
1082; CHECK-NEXT:    cmpge p0.s, p0/z, z2.s, z1.s
1083; CHECK-NEXT:    ret
1084  %icmp1 = icmp sgt <vscale x 4 x i32> %a, %b
1085  %icmp2 = icmp sle <vscale x 4 x i32> %b, %c
1086  %and = and <vscale x 4 x i1> %icmp1, %icmp2
1087  ret <vscale x 4 x i1> %and
1088}
1089
1090define <vscale x 4 x i1> @predicated_icmp_unknown_lhs(<vscale x 4 x i1> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
1091; CHECK-LABEL: predicated_icmp_unknown_lhs:
1092; CHECK:       // %bb.0:
1093; CHECK-NEXT:    cmpge p0.s, p0/z, z1.s, z0.s
1094; CHECK-NEXT:    ret
1095  %icmp = icmp sle <vscale x 4 x i32> %b, %c
1096  %and = and <vscale x 4 x i1> %a, %icmp
1097  ret <vscale x 4 x i1> %and
1098}
1099
1100define <vscale x 4 x i1> @predicated_icmp_unknown_rhs(<vscale x 4 x i1> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
1101; CHECK-LABEL: predicated_icmp_unknown_rhs:
1102; CHECK:       // %bb.0:
1103; CHECK-NEXT:    cmpge p0.s, p0/z, z1.s, z0.s
1104; CHECK-NEXT:    ret
1105  %icmp = icmp sle <vscale x 4 x i32> %b, %c
1106  %and = and <vscale x 4 x i1> %icmp, %a
1107  ret <vscale x 4 x i1> %and
1108}
1109
1110define <vscale x 16 x i1> @predicated_icmp_eq_imm(<vscale x 16 x i1> %a, <vscale x 16 x i8> %b) {
1111; CHECK-LABEL: predicated_icmp_eq_imm:
1112; CHECK:       // %bb.0:
1113; CHECK-NEXT:    cmpeq p0.b, p0/z, z0.b, #0
1114; CHECK-NEXT:    ret
1115  %imm = shufflevector <vscale x 16 x i8> insertelement (<vscale x 16 x i8> undef, i8 0, i64 0), <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
1116  %icmp = icmp eq <vscale x 16 x i8> %b, %imm
1117  %and = and <vscale x 16 x i1> %a, %icmp
1118  ret <vscale x 16 x i1> %and
1119}
1120
1121define <vscale x 8 x i1> @predicated_icmp_ne_imm(<vscale x 8 x i1> %a, <vscale x 8 x i16> %b) {
1122; CHECK-LABEL: predicated_icmp_ne_imm:
1123; CHECK:       // %bb.0:
1124; CHECK-NEXT:    cmpne p0.h, p0/z, z0.h, #-16
1125; CHECK-NEXT:    ret
1126  %imm = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 -16, i64 0), <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
1127  %icmp = icmp ne <vscale x 8 x i16> %b, %imm
1128  %and = and <vscale x 8 x i1> %a, %icmp
1129  ret <vscale x 8 x i1> %and
1130}
1131
1132define <vscale x 4 x i1> @predicated_icmp_sge_imm(<vscale x 4 x i1> %a, <vscale x 4 x i32> %b) {
1133; CHECK-LABEL: predicated_icmp_sge_imm:
1134; CHECK:       // %bb.0:
1135; CHECK-NEXT:    cmpge p0.s, p0/z, z0.s, #1
1136; CHECK-NEXT:    ret
1137  %imm = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 1, i64 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
1138  %icmp = icmp sge <vscale x 4 x i32> %b, %imm
1139  %and = and <vscale x 4 x i1> %a, %icmp
1140  ret <vscale x 4 x i1> %and
1141}
1142
1143define <vscale x 2 x i1> @predicated_icmp_sgt_imm(<vscale x 2 x i1> %a, <vscale x 2 x i64> %b) {
1144; CHECK-LABEL: predicated_icmp_sgt_imm:
1145; CHECK:       // %bb.0:
1146; CHECK-NEXT:    cmpgt p0.d, p0/z, z0.d, #2
1147; CHECK-NEXT:    ret
1148  %imm = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 2, i64 0), <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
1149  %icmp = icmp sgt <vscale x 2 x i64> %b, %imm
1150  %and = and <vscale x 2 x i1> %a, %icmp
1151  ret <vscale x 2 x i1> %and
1152}
1153
1154define <vscale x 16 x i1> @predicated_icmp_sle_imm(<vscale x 16 x i1> %a, <vscale x 16 x i8> %b) {
1155; CHECK-LABEL: predicated_icmp_sle_imm:
1156; CHECK:       // %bb.0:
1157; CHECK-NEXT:    cmple p0.b, p0/z, z0.b, #-1
1158; CHECK-NEXT:    ret
1159  %imm = shufflevector <vscale x 16 x i8> insertelement (<vscale x 16 x i8> undef, i8 -1, i64 0), <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
1160  %icmp = icmp sle <vscale x 16 x i8> %b, %imm
1161  %and = and <vscale x 16 x i1> %a, %icmp
1162  ret <vscale x 16 x i1> %and
1163}
1164
1165define <vscale x 8 x i1> @predicated_icmp_slt_imm(<vscale x 8 x i1> %a, <vscale x 8 x i16> %b) {
1166; CHECK-LABEL: predicated_icmp_slt_imm:
1167; CHECK:       // %bb.0:
1168; CHECK-NEXT:    cmplt p0.h, p0/z, z0.h, #-2
1169; CHECK-NEXT:    ret
1170  %imm = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 -2, i64 0), <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
1171  %icmp = icmp slt <vscale x 8 x i16> %b, %imm
1172  %and = and <vscale x 8 x i1> %a, %icmp
1173  ret <vscale x 8 x i1> %and
1174}
1175
1176define <vscale x 4 x i1> @predicated_icmp_uge_imm(<vscale x 4 x i1> %a, <vscale x 4 x i32> %b) {
1177; CHECK-LABEL: predicated_icmp_uge_imm:
1178; CHECK:       // %bb.0:
1179; CHECK-NEXT:    cmphs p0.s, p0/z, z0.s, #1
1180; CHECK-NEXT:    ret
1181  %imm = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 1, i64 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
1182  %icmp = icmp uge <vscale x 4 x i32> %b, %imm
1183  %and = and <vscale x 4 x i1> %a, %icmp
1184  ret <vscale x 4 x i1> %and
1185}
1186
1187define <vscale x 2 x i1> @predicated_icmp_ugt_imm(<vscale x 2 x i1> %a, <vscale x 2 x i64> %b) {
1188; CHECK-LABEL: predicated_icmp_ugt_imm:
1189; CHECK:       // %bb.0:
1190; CHECK-NEXT:    cmphi p0.d, p0/z, z0.d, #2
1191; CHECK-NEXT:    ret
1192  %imm = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 2, i64 0), <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
1193  %icmp = icmp ugt <vscale x 2 x i64> %b, %imm
1194  %and = and <vscale x 2 x i1> %a, %icmp
1195  ret <vscale x 2 x i1> %and
1196}
1197
1198define <vscale x 16 x i1> @predicated_icmp_ule_imm(<vscale x 16 x i1> %a, <vscale x 16 x i8> %b) {
1199; CHECK-LABEL: predicated_icmp_ule_imm:
1200; CHECK:       // %bb.0:
1201; CHECK-NEXT:    cmpls p0.b, p0/z, z0.b, #3
1202; CHECK-NEXT:    ret
1203  %imm = shufflevector <vscale x 16 x i8> insertelement (<vscale x 16 x i8> undef, i8 3, i64 0), <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
1204  %icmp = icmp ule <vscale x 16 x i8> %b, %imm
1205  %and = and <vscale x 16 x i1> %a, %icmp
1206  ret <vscale x 16 x i1> %and
1207}
1208
1209define <vscale x 8 x i1> @predicated_icmp_ult_imm(<vscale x 8 x i1> %a, <vscale x 8 x i16> %b) {
1210; CHECK-LABEL: predicated_icmp_ult_imm:
1211; CHECK:       // %bb.0:
1212; CHECK-NEXT:    cmplo p0.h, p0/z, z0.h, #127
1213; CHECK-NEXT:    ret
1214  %imm = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 127, i64 0), <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
1215  %icmp = icmp ult <vscale x 8 x i16> %b, %imm
1216  %and = and <vscale x 8 x i1> %a, %icmp
1217  ret <vscale x 8 x i1> %and
1218}
1219
1220%svboolx2 = type { <vscale x 4 x i1>, <vscale x 4 x i1> }
1221
1222define %svboolx2 @and_of_multiuse_icmp_sle(<vscale x 4 x i1> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
1223; CHECK-LABEL: and_of_multiuse_icmp_sle:
1224; CHECK:       // %bb.0:
1225; CHECK-NEXT:    ptrue p1.s
1226; CHECK-NEXT:    cmpge p1.s, p1/z, z1.s, z0.s
1227; CHECK-NEXT:    and p0.b, p0/z, p0.b, p1.b
1228; CHECK-NEXT:    ret
1229  %cmp = icmp sle <vscale x 4 x i32> %b, %c
1230  %and = and <vscale x 4 x i1> %a, %cmp
1231  %ins.1 = insertvalue %svboolx2 poison, <vscale x 4 x i1> %and, 0
1232  %ins.2 = insertvalue %svboolx2 %ins.1, <vscale x 4 x i1> %cmp, 1
1233  ret %svboolx2 %ins.2
1234}
1235
1236define %svboolx2 @and_of_multiuse_icmp_sle_imm(<vscale x 4 x i1> %a, <vscale x 4 x i32> %b) {
1237; CHECK-LABEL: and_of_multiuse_icmp_sle_imm:
1238; CHECK:       // %bb.0:
1239; CHECK-NEXT:    ptrue p1.s
1240; CHECK-NEXT:    cmple p1.s, p1/z, z0.s, #1
1241; CHECK-NEXT:    and p0.b, p0/z, p0.b, p1.b
1242; CHECK-NEXT:    ret
1243  %imm = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 1, i64 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
1244  %cmp = icmp sle <vscale x 4 x i32> %b, %imm
1245  %and = and <vscale x 4 x i1> %a, %cmp
1246  %ins.1 = insertvalue %svboolx2 poison, <vscale x 4 x i1> %and, 0
1247  %ins.2 = insertvalue %svboolx2 %ins.1, <vscale x 4 x i1> %cmp, 1
1248  ret %svboolx2 %ins.2
1249}
1250
1251define %svboolx2 @and_of_multiuse_icmp_ugt(<vscale x 4 x i1> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
1252; CHECK-LABEL: and_of_multiuse_icmp_ugt:
1253; CHECK:       // %bb.0:
1254; CHECK-NEXT:    ptrue p1.s
1255; CHECK-NEXT:    cmphi p1.s, p1/z, z0.s, z1.s
1256; CHECK-NEXT:    and p0.b, p0/z, p0.b, p1.b
1257; CHECK-NEXT:    ret
1258  %cmp = icmp ugt <vscale x 4 x i32> %b, %c
1259  %and = and <vscale x 4 x i1> %a, %cmp
1260  %ins.1 = insertvalue %svboolx2 poison, <vscale x 4 x i1> %and, 0
1261  %ins.2 = insertvalue %svboolx2 %ins.1, <vscale x 4 x i1> %cmp, 1
1262  ret %svboolx2 %ins.2
1263}
1264
1265define %svboolx2 @and_of_multiuse_icmp_ugt_imm(<vscale x 4 x i1> %a, <vscale x 4 x i32> %b) {
1266; CHECK-LABEL: and_of_multiuse_icmp_ugt_imm:
1267; CHECK:       // %bb.0:
1268; CHECK-NEXT:    ptrue p1.s
1269; CHECK-NEXT:    cmphi p1.s, p1/z, z0.s, #1
1270; CHECK-NEXT:    and p0.b, p0/z, p0.b, p1.b
1271; CHECK-NEXT:    ret
1272  %imm = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 1, i64 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
1273  %cmp = icmp ugt <vscale x 4 x i32> %b, %imm
1274  %and = and <vscale x 4 x i1> %a, %cmp
1275  %ins.1 = insertvalue %svboolx2 poison, <vscale x 4 x i1> %and, 0
1276  %ins.2 = insertvalue %svboolx2 %ins.1, <vscale x 4 x i1> %cmp, 1
1277  ret %svboolx2 %ins.2
1278}
1279
1280declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
1281declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpeq.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
1282declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpeq.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
1283declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpeq.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
1284declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)
1285declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpeq.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)
1286declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpeq.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)
1287
1288declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
1289declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpge.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
1290declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpge.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
1291declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpge.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
1292declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)
1293declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpge.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)
1294declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpge.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)
1295
1296declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
1297declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpgt.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
1298declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
1299declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpgt.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
1300declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)
1301declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpgt.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)
1302declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)
1303
1304declare <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
1305declare <vscale x 8 x i1> @llvm.aarch64.sve.cmphi.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
1306declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
1307declare <vscale x 2 x i1> @llvm.aarch64.sve.cmphi.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
1308declare <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)
1309declare <vscale x 8 x i1> @llvm.aarch64.sve.cmphi.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)
1310declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)
1311
1312declare <vscale x 16 x i1> @llvm.aarch64.sve.cmphs.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
1313declare <vscale x 8 x i1> @llvm.aarch64.sve.cmphs.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
1314declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
1315declare <vscale x 2 x i1> @llvm.aarch64.sve.cmphs.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
1316declare <vscale x 16 x i1> @llvm.aarch64.sve.cmphs.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)
1317declare <vscale x 8 x i1> @llvm.aarch64.sve.cmphs.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)
1318declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)
1319
1320declare <vscale x 16 x i1> @llvm.aarch64.sve.cmple.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)
1321declare <vscale x 8 x i1> @llvm.aarch64.sve.cmple.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)
1322declare <vscale x 4 x i1> @llvm.aarch64.sve.cmple.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)
1323
1324declare <vscale x 16 x i1> @llvm.aarch64.sve.cmplo.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)
1325declare <vscale x 8 x i1> @llvm.aarch64.sve.cmplo.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)
1326declare <vscale x 4 x i1> @llvm.aarch64.sve.cmplo.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)
1327
1328declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpls.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)
1329declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpls.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)
1330declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpls.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)
1331
1332declare <vscale x 16 x i1> @llvm.aarch64.sve.cmplt.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)
1333declare <vscale x 8 x i1> @llvm.aarch64.sve.cmplt.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)
1334declare <vscale x 4 x i1> @llvm.aarch64.sve.cmplt.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)
1335
1336declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
1337declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
1338declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
1339declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
1340declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)
1341declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)
1342declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)
1343
1344declare <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64)
1345