xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-intrinsics-fp-reduce.ll (revision b09a52d589c140435622c715b0608e6b5d47380f) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve < %s | FileCheck %s
3
4;
5; FADDA
6;
7
8define half @fadda_f16(<vscale x 8 x i1> %pg, half %init, <vscale x 8 x half> %a) {
9; CHECK-LABEL: fadda_f16:
10; CHECK:       // %bb.0:
11; CHECK-NEXT:    // kill: def $h0 killed $h0 def $z0
12; CHECK-NEXT:    fadda h0, p0, h0, z1.h
13; CHECK-NEXT:    // kill: def $h0 killed $h0 killed $z0
14; CHECK-NEXT:    ret
15  %res = call half @llvm.aarch64.sve.fadda.nxv8f16(<vscale x 8 x i1> %pg,
16                                                   half %init,
17                                                   <vscale x 8 x half> %a)
18  ret half %res
19}
20
21define float @fadda_f32(<vscale x 4 x i1> %pg, float %init, <vscale x 4 x float> %a) {
22; CHECK-LABEL: fadda_f32:
23; CHECK:       // %bb.0:
24; CHECK-NEXT:    // kill: def $s0 killed $s0 def $z0
25; CHECK-NEXT:    fadda s0, p0, s0, z1.s
26; CHECK-NEXT:    // kill: def $s0 killed $s0 killed $z0
27; CHECK-NEXT:    ret
28  %res = call float @llvm.aarch64.sve.fadda.nxv4f32(<vscale x 4 x i1> %pg,
29                                                    float %init,
30                                                    <vscale x 4 x float> %a)
31  ret float %res
32}
33
34define double @fadda_f64(<vscale x 2 x i1> %pg, double %init, <vscale x 2 x double> %a) {
35; CHECK-LABEL: fadda_f64:
36; CHECK:       // %bb.0:
37; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
38; CHECK-NEXT:    fadda d0, p0, d0, z1.d
39; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
40; CHECK-NEXT:    ret
41  %res = call double @llvm.aarch64.sve.fadda.nxv2f64(<vscale x 2 x i1> %pg,
42                                                     double %init,
43                                                     <vscale x 2 x double> %a)
44  ret double %res
45}
46
47;
48; FADDV
49;
50
51define half @faddv_f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
52; CHECK-LABEL: faddv_f16:
53; CHECK:       // %bb.0:
54; CHECK-NEXT:    faddv h0, p0, z0.h
55; CHECK-NEXT:    // kill: def $h0 killed $h0 killed $z0
56; CHECK-NEXT:    ret
57  %res = call half @llvm.aarch64.sve.faddv.nxv8f16(<vscale x 8 x i1> %pg,
58                                                   <vscale x 8 x half> %a)
59  ret half %res
60}
61
62define float @faddv_f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
63; CHECK-LABEL: faddv_f32:
64; CHECK:       // %bb.0:
65; CHECK-NEXT:    faddv s0, p0, z0.s
66; CHECK-NEXT:    // kill: def $s0 killed $s0 killed $z0
67; CHECK-NEXT:    ret
68  %res = call float @llvm.aarch64.sve.faddv.nxv4f32(<vscale x 4 x i1> %pg,
69                                                    <vscale x 4 x float> %a)
70  ret float %res
71}
72
73define double @faddv_f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
74; CHECK-LABEL: faddv_f64:
75; CHECK:       // %bb.0:
76; CHECK-NEXT:    faddv d0, p0, z0.d
77; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
78; CHECK-NEXT:    ret
79  %res = call double @llvm.aarch64.sve.faddv.nxv2f64(<vscale x 2 x i1> %pg,
80                                                     <vscale x 2 x double> %a)
81  ret double %res
82}
83
84;
85; FMAXNMV
86;
87
88define half @fmaxnmv_f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
89; CHECK-LABEL: fmaxnmv_f16:
90; CHECK:       // %bb.0:
91; CHECK-NEXT:    fmaxnmv h0, p0, z0.h
92; CHECK-NEXT:    // kill: def $h0 killed $h0 killed $z0
93; CHECK-NEXT:    ret
94  %res = call half @llvm.aarch64.sve.fmaxnmv.nxv8f16(<vscale x 8 x i1> %pg,
95                                                     <vscale x 8 x half> %a)
96  ret half %res
97}
98
99define float @fmaxnmv_f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
100; CHECK-LABEL: fmaxnmv_f32:
101; CHECK:       // %bb.0:
102; CHECK-NEXT:    fmaxnmv s0, p0, z0.s
103; CHECK-NEXT:    // kill: def $s0 killed $s0 killed $z0
104; CHECK-NEXT:    ret
105  %res = call float @llvm.aarch64.sve.fmaxnmv.nxv4f32(<vscale x 4 x i1> %pg,
106                                                      <vscale x 4 x float> %a)
107  ret float %res
108}
109
110define double @fmaxnmv_f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
111; CHECK-LABEL: fmaxnmv_f64:
112; CHECK:       // %bb.0:
113; CHECK-NEXT:    fmaxnmv d0, p0, z0.d
114; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
115; CHECK-NEXT:    ret
116  %res = call double @llvm.aarch64.sve.fmaxnmv.nxv2f64(<vscale x 2 x i1> %pg,
117                                                       <vscale x 2 x double> %a)
118  ret double %res
119}
120
121;
122; FMAXV
123;
124
125define half @fmaxv_f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
126; CHECK-LABEL: fmaxv_f16:
127; CHECK:       // %bb.0:
128; CHECK-NEXT:    fmaxv h0, p0, z0.h
129; CHECK-NEXT:    // kill: def $h0 killed $h0 killed $z0
130; CHECK-NEXT:    ret
131  %res = call half @llvm.aarch64.sve.fmaxv.nxv8f16(<vscale x 8 x i1> %pg,
132                                                   <vscale x 8 x half> %a)
133  ret half %res
134}
135
136define float @fmaxv_f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
137; CHECK-LABEL: fmaxv_f32:
138; CHECK:       // %bb.0:
139; CHECK-NEXT:    fmaxv s0, p0, z0.s
140; CHECK-NEXT:    // kill: def $s0 killed $s0 killed $z0
141; CHECK-NEXT:    ret
142  %res = call float @llvm.aarch64.sve.fmaxv.nxv4f32(<vscale x 4 x i1> %pg,
143                                                    <vscale x 4 x float> %a)
144  ret float %res
145}
146
147define double @fmaxv_f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
148; CHECK-LABEL: fmaxv_f64:
149; CHECK:       // %bb.0:
150; CHECK-NEXT:    fmaxv d0, p0, z0.d
151; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
152; CHECK-NEXT:    ret
153  %res = call double @llvm.aarch64.sve.fmaxv.nxv2f64(<vscale x 2 x i1> %pg,
154                                                     <vscale x 2 x double> %a)
155  ret double %res
156}
157
158;
159; FMINNMV
160;
161
162define half @fminnmv_f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
163; CHECK-LABEL: fminnmv_f16:
164; CHECK:       // %bb.0:
165; CHECK-NEXT:    fminnmv h0, p0, z0.h
166; CHECK-NEXT:    // kill: def $h0 killed $h0 killed $z0
167; CHECK-NEXT:    ret
168  %res = call half @llvm.aarch64.sve.fminnmv.nxv8f16(<vscale x 8 x i1> %pg,
169                                                     <vscale x 8 x half> %a)
170  ret half %res
171}
172
173define float @fminnmv_f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
174; CHECK-LABEL: fminnmv_f32:
175; CHECK:       // %bb.0:
176; CHECK-NEXT:    fminnmv s0, p0, z0.s
177; CHECK-NEXT:    // kill: def $s0 killed $s0 killed $z0
178; CHECK-NEXT:    ret
179  %res = call float @llvm.aarch64.sve.fminnmv.nxv4f32(<vscale x 4 x i1> %pg,
180                                                      <vscale x 4 x float> %a)
181  ret float %res
182}
183
184define double @fminnmv_f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
185; CHECK-LABEL: fminnmv_f64:
186; CHECK:       // %bb.0:
187; CHECK-NEXT:    fminnmv d0, p0, z0.d
188; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
189; CHECK-NEXT:    ret
190  %res = call double @llvm.aarch64.sve.fminnmv.nxv2f64(<vscale x 2 x i1> %pg,
191                                                       <vscale x 2 x double> %a)
192  ret double %res
193}
194
195;
196; FMINV
197;
198
199define half @fminv_f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
200; CHECK-LABEL: fminv_f16:
201; CHECK:       // %bb.0:
202; CHECK-NEXT:    fminv h0, p0, z0.h
203; CHECK-NEXT:    // kill: def $h0 killed $h0 killed $z0
204; CHECK-NEXT:    ret
205  %res = call half @llvm.aarch64.sve.fminv.nxv8f16(<vscale x 8 x i1> %pg,
206                                                   <vscale x 8 x half> %a)
207  ret half %res
208}
209
210define float @fminv_f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
211; CHECK-LABEL: fminv_f32:
212; CHECK:       // %bb.0:
213; CHECK-NEXT:    fminv s0, p0, z0.s
214; CHECK-NEXT:    // kill: def $s0 killed $s0 killed $z0
215; CHECK-NEXT:    ret
216  %res = call float @llvm.aarch64.sve.fminv.nxv4f32(<vscale x 4 x i1> %pg,
217                                                    <vscale x 4 x float> %a)
218  ret float %res
219}
220
221define double @fminv_f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
222; CHECK-LABEL: fminv_f64:
223; CHECK:       // %bb.0:
224; CHECK-NEXT:    fminv d0, p0, z0.d
225; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
226; CHECK-NEXT:    ret
227  %res = call double @llvm.aarch64.sve.fminv.nxv2f64(<vscale x 2 x i1> %pg,
228                                                     <vscale x 2 x double> %a)
229  ret double %res
230}
231
232declare half @llvm.aarch64.sve.fadda.nxv8f16(<vscale x 8 x i1>, half, <vscale x 8 x half>)
233declare float @llvm.aarch64.sve.fadda.nxv4f32(<vscale x 4 x i1>, float, <vscale x 4 x float>)
234declare double @llvm.aarch64.sve.fadda.nxv2f64(<vscale x 2 x i1>, double, <vscale x 2 x double>)
235
236declare half @llvm.aarch64.sve.faddv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>)
237declare float @llvm.aarch64.sve.faddv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>)
238declare double @llvm.aarch64.sve.faddv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>)
239
240declare half @llvm.aarch64.sve.fmaxnmv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>)
241declare float @llvm.aarch64.sve.fmaxnmv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>)
242declare double @llvm.aarch64.sve.fmaxnmv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>)
243
244declare half @llvm.aarch64.sve.fmaxv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>)
245declare float @llvm.aarch64.sve.fmaxv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>)
246declare double @llvm.aarch64.sve.fmaxv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>)
247
248declare half @llvm.aarch64.sve.fminnmv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>)
249declare float @llvm.aarch64.sve.fminnmv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>)
250declare double @llvm.aarch64.sve.fminnmv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>)
251
252declare half @llvm.aarch64.sve.fminv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>)
253declare float @llvm.aarch64.sve.fminv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>)
254declare double @llvm.aarch64.sve.fminv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>)
255