1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs < %s | FileCheck %s 3 4target triple = "aarch64-unknown-linux-gnu" 5 6; 7; RDFFR 8; 9 10define <vscale x 16 x i1> @rdffr() #0 { 11; CHECK-LABEL: rdffr: 12; CHECK: // %bb.0: 13; CHECK-NEXT: rdffr p0.b 14; CHECK-NEXT: ret 15 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr() 16 ret <vscale x 16 x i1> %out 17} 18 19define <vscale x 16 x i1> @rdffr_z(<vscale x 16 x i1> %pg) #0 { 20; CHECK-LABEL: rdffr_z: 21; CHECK: // %bb.0: 22; CHECK-NEXT: rdffr p0.b, p0/z 23; CHECK-NEXT: ret 24 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1> %pg) 25 ret <vscale x 16 x i1> %out 26} 27 28; Test that rdffr.z followed by ptest optimizes to flags-setting rdffrs. 29define i1 @rdffr_z_ptest(<vscale x 16 x i1> %pg) #0 { 30; CHECK-LABEL: rdffr_z_ptest: 31; CHECK: // %bb.0: 32; CHECK-NEXT: rdffrs p0.b, p0/z 33; CHECK-NEXT: cset w0, ne 34; CHECK-NEXT: ret 35 %rdffr = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1> %pg) 36 %out = call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %rdffr) 37 ret i1 %out 38} 39 40; 41; SETFFR 42; 43 44define void @set_ffr() #0 { 45; CHECK-LABEL: set_ffr: 46; CHECK: // %bb.0: 47; CHECK-NEXT: setffr 48; CHECK-NEXT: ret 49 call void @llvm.aarch64.sve.setffr() 50 ret void 51} 52 53; 54; WRFFR 55; 56 57define void @wrffr(<vscale x 16 x i1> %a) #0 { 58; CHECK-LABEL: wrffr: 59; CHECK: // %bb.0: 60; CHECK-NEXT: wrffr p0.b 61; CHECK-NEXT: ret 62 call void @llvm.aarch64.sve.wrffr(<vscale x 16 x i1> %a) 63 ret void 64} 65 66declare <vscale x 16 x i1> @llvm.aarch64.sve.rdffr() 67declare <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1>) 68declare void @llvm.aarch64.sve.setffr() 69declare void @llvm.aarch64.sve.wrffr(<vscale x 16 x i1>) 70 71declare i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) 72 73attributes #0 = { "target-features"="+sve" } 74