1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s 3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s 4 5; 6; Testing prfop encodings 7; 8define void @test_svprf_pldl1strm(<vscale x 16 x i1> %pg, ptr %base) { 9; CHECK-LABEL: test_svprf_pldl1strm: 10; CHECK: // %bb.0: // %entry 11; CHECK-NEXT: prfb pldl1strm, p0, [x0] 12; CHECK-NEXT: ret 13entry: 14 tail call void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1> %pg, ptr %base, i32 1) 15 ret void 16} 17 18define void @test_svprf_pldl2keep(<vscale x 16 x i1> %pg, ptr %base) { 19; CHECK-LABEL: test_svprf_pldl2keep: 20; CHECK: // %bb.0: // %entry 21; CHECK-NEXT: prfb pldl2keep, p0, [x0] 22; CHECK-NEXT: ret 23entry: 24 tail call void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1> %pg, ptr %base, i32 2) 25 ret void 26} 27 28define void @test_svprf_pldl2strm(<vscale x 16 x i1> %pg, ptr %base) { 29; CHECK-LABEL: test_svprf_pldl2strm: 30; CHECK: // %bb.0: // %entry 31; CHECK-NEXT: prfb pldl2strm, p0, [x0] 32; CHECK-NEXT: ret 33entry: 34 tail call void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1> %pg, ptr %base, i32 3) 35 ret void 36} 37 38define void @test_svprf_pldl3keep(<vscale x 16 x i1> %pg, ptr %base) { 39; CHECK-LABEL: test_svprf_pldl3keep: 40; CHECK: // %bb.0: // %entry 41; CHECK-NEXT: prfb pldl3keep, p0, [x0] 42; CHECK-NEXT: ret 43entry: 44 tail call void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1> %pg, ptr %base, i32 4) 45 ret void 46} 47 48define void @test_svprf_pldl3strm(<vscale x 16 x i1> %pg, ptr %base) { 49; CHECK-LABEL: test_svprf_pldl3strm: 50; CHECK: // %bb.0: // %entry 51; CHECK-NEXT: prfb pldl3strm, p0, [x0] 52; CHECK-NEXT: ret 53entry: 54 tail call void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1> %pg, ptr %base, i32 5) 55 ret void 56} 57 58define void @test_svprf_pstl1keep(<vscale x 16 x i1> %pg, ptr %base) { 59; CHECK-LABEL: test_svprf_pstl1keep: 60; CHECK: // %bb.0: // %entry 61; CHECK-NEXT: prfb pstl1keep, p0, [x0] 62; CHECK-NEXT: ret 63entry: 64 tail call void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1> %pg, ptr %base, i32 8) 65 ret void 66} 67 68define void @test_svprf_pstl1strm(<vscale x 16 x i1> %pg, ptr %base) { 69; CHECK-LABEL: test_svprf_pstl1strm: 70; CHECK: // %bb.0: // %entry 71; CHECK-NEXT: prfb pstl1strm, p0, [x0] 72; CHECK-NEXT: ret 73entry: 74 tail call void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1> %pg, ptr %base, i32 9) 75 ret void 76} 77 78define void @test_svprf_pstl2keep(<vscale x 16 x i1> %pg, ptr %base) { 79; CHECK-LABEL: test_svprf_pstl2keep: 80; CHECK: // %bb.0: // %entry 81; CHECK-NEXT: prfb pstl2keep, p0, [x0] 82; CHECK-NEXT: ret 83entry: 84 tail call void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1> %pg, ptr %base, i32 10) 85 ret void 86} 87 88define void @test_svprf_pstl2strm(<vscale x 16 x i1> %pg, ptr %base) { 89; CHECK-LABEL: test_svprf_pstl2strm: 90; CHECK: // %bb.0: // %entry 91; CHECK-NEXT: prfb pstl2strm, p0, [x0] 92; CHECK-NEXT: ret 93entry: 94 tail call void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1> %pg, ptr %base, i32 11) 95 ret void 96} 97 98define void @test_svprf_pstl3keep(<vscale x 16 x i1> %pg, ptr %base) { 99; CHECK-LABEL: test_svprf_pstl3keep: 100; CHECK: // %bb.0: // %entry 101; CHECK-NEXT: prfb pstl3keep, p0, [x0] 102; CHECK-NEXT: ret 103entry: 104 tail call void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1> %pg, ptr %base, i32 12) 105 ret void 106} 107 108define void @test_svprf_pstl3strm(<vscale x 16 x i1> %pg, ptr %base) { 109; CHECK-LABEL: test_svprf_pstl3strm: 110; CHECK: // %bb.0: // %entry 111; CHECK-NEXT: prfb pstl3strm, p0, [x0] 112; CHECK-NEXT: ret 113entry: 114 tail call void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1> %pg, ptr %base, i32 13) 115 ret void 116} 117 118; 119; Testing imm limits of SI form 120; 121 122define void @test_svprf_vnum_under(<vscale x 16 x i1> %pg, ptr %base) { 123; CHECK-LABEL: test_svprf_vnum_under: 124; CHECK: // %bb.0: // %entry 125; CHECK-NEXT: rdvl x8, #1 126; CHECK-NEXT: mov x9, #-528 127; CHECK-NEXT: lsr x8, x8, #4 128; CHECK-NEXT: mul x8, x8, x9 129; CHECK-NEXT: prfb pstl3strm, p0, [x0, x8] 130; CHECK-NEXT: ret 131entry: 132 %gep = getelementptr inbounds <vscale x 16 x i8>, ptr %base, i64 -33, i64 0 133 tail call void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1> %pg, ptr %gep, i32 13) 134 ret void 135} 136 137define void @test_svprf_vnum_min(<vscale x 16 x i1> %pg, ptr %base) { 138; CHECK-LABEL: test_svprf_vnum_min: 139; CHECK: // %bb.0: // %entry 140; CHECK-NEXT: prfb pstl3strm, p0, [x0, #-32, mul vl] 141; CHECK-NEXT: ret 142entry: 143 %gep = getelementptr inbounds <vscale x 16 x i8>, ptr %base, i64 -32, i64 0 144 tail call void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1> %pg, ptr %gep, i32 13) 145 ret void 146} 147 148define void @test_svprf_vnum_over(<vscale x 16 x i1> %pg, ptr %base) { 149; CHECK-LABEL: test_svprf_vnum_over: 150; CHECK: // %bb.0: // %entry 151; CHECK-NEXT: rdvl x8, #1 152; CHECK-NEXT: mov w9, #512 153; CHECK-NEXT: lsr x8, x8, #4 154; CHECK-NEXT: mul x8, x8, x9 155; CHECK-NEXT: prfb pstl3strm, p0, [x0, x8] 156; CHECK-NEXT: ret 157entry: 158 %gep = getelementptr inbounds <vscale x 16 x i8>, ptr %base, i64 32, i64 0 159 tail call void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1> %pg, ptr %gep, i32 13) 160 ret void 161} 162 163define void @test_svprf_vnum_max(<vscale x 16 x i1> %pg, ptr %base) { 164; CHECK-LABEL: test_svprf_vnum_max: 165; CHECK: // %bb.0: // %entry 166; CHECK-NEXT: prfb pstl3strm, p0, [x0, #31, mul vl] 167; CHECK-NEXT: ret 168entry: 169 %gep = getelementptr inbounds <vscale x 16 x i8>, ptr %base, i64 31, i64 0 170 tail call void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1> %pg, ptr %gep, i32 13) 171 ret void 172} 173 174; 175; scalar contiguous 176; 177 178define void @test_svprfb(<vscale x 16 x i1> %pg, ptr %base) { 179; CHECK-LABEL: test_svprfb: 180; CHECK: // %bb.0: // %entry 181; CHECK-NEXT: prfb pldl1keep, p0, [x0] 182; CHECK-NEXT: ret 183entry: 184 tail call void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1> %pg, ptr %base, i32 0) 185 ret void 186} 187 188define void @test_svprfh(<vscale x 8 x i1> %pg, ptr %base) { 189; CHECK-LABEL: test_svprfh: 190; CHECK: // %bb.0: // %entry 191; CHECK-NEXT: prfh pldl1keep, p0, [x0] 192; CHECK-NEXT: ret 193entry: 194 tail call void @llvm.aarch64.sve.prf.nxv8i1(<vscale x 8 x i1> %pg, ptr %base, i32 0) 195 ret void 196} 197 198define void @test_svprfw(<vscale x 4 x i1> %pg, ptr %base) { 199; CHECK-LABEL: test_svprfw: 200; CHECK: // %bb.0: // %entry 201; CHECK-NEXT: prfw pldl1keep, p0, [x0] 202; CHECK-NEXT: ret 203entry: 204 tail call void @llvm.aarch64.sve.prf.nxv4i1(<vscale x 4 x i1> %pg, ptr %base, i32 0) 205 ret void 206} 207 208define void @test_svprfd(<vscale x 2 x i1> %pg, ptr %base) { 209; CHECK-LABEL: test_svprfd: 210; CHECK: // %bb.0: // %entry 211; CHECK-NEXT: prfd pldl1keep, p0, [x0] 212; CHECK-NEXT: ret 213entry: 214 tail call void @llvm.aarch64.sve.prf.nxv2i1(<vscale x 2 x i1> %pg, ptr %base, i32 0) 215 ret void 216} 217 218; 219; scalar + imm contiguous 220; 221; imm form of prfb is tested above 222 223define void @test_svprfh_vnum(<vscale x 8 x i1> %pg, ptr %base) { 224; CHECK-LABEL: test_svprfh_vnum: 225; CHECK: // %bb.0: // %entry 226; CHECK-NEXT: prfh pstl3strm, p0, [x0, #31, mul vl] 227; CHECK-NEXT: ret 228entry: 229 %gep = getelementptr <vscale x 8 x i16>, ptr %base, i64 31 230 %addr = bitcast ptr %gep to ptr 231 tail call void @llvm.aarch64.sve.prf.nxv8i1(<vscale x 8 x i1> %pg, ptr %addr, i32 13) 232 ret void 233} 234 235define void @test_svprfw_vnum(<vscale x 4 x i1> %pg, ptr %base) { 236; CHECK-LABEL: test_svprfw_vnum: 237; CHECK: // %bb.0: // %entry 238; CHECK-NEXT: prfw pstl3strm, p0, [x0, #31, mul vl] 239; CHECK-NEXT: ret 240entry: 241 %gep = getelementptr <vscale x 4 x i32>, ptr %base, i64 31 242 %addr = bitcast ptr %gep to ptr 243 tail call void @llvm.aarch64.sve.prf.nxv4i1(<vscale x 4 x i1> %pg, ptr %addr, i32 13) 244 ret void 245} 246 247define void @test_svprfd_vnum(<vscale x 2 x i1> %pg, ptr %base) { 248; CHECK-LABEL: test_svprfd_vnum: 249; CHECK: // %bb.0: // %entry 250; CHECK-NEXT: prfd pstl3strm, p0, [x0, #31, mul vl] 251; CHECK-NEXT: ret 252entry: 253 %gep = getelementptr <vscale x 2 x i64>, ptr %base, i64 31 254 %addr = bitcast ptr %gep to ptr 255 tail call void @llvm.aarch64.sve.prf.nxv2i1(<vscale x 2 x i1> %pg, ptr %addr, i32 13) 256 ret void 257} 258 259; 260; scalar + scaled scalar contiguous 261; 262 263define void @test_svprfb_ss(<vscale x 16 x i1> %pg, ptr %base, i64 %offset) { 264; CHECK-LABEL: test_svprfb_ss: 265; CHECK: // %bb.0: // %entry 266; CHECK-NEXT: prfb pstl3strm, p0, [x0, x1] 267; CHECK-NEXT: ret 268entry: 269 %addr = getelementptr i8, ptr %base, i64 %offset 270 tail call void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1> %pg, ptr %addr, i32 13) 271 ret void 272} 273 274define void @test_svprfh_ss(<vscale x 8 x i1> %pg, ptr %base, i64 %offset) { 275; CHECK-LABEL: test_svprfh_ss: 276; CHECK: // %bb.0: // %entry 277; CHECK-NEXT: prfh pstl3strm, p0, [x0, x1, lsl #1] 278; CHECK-NEXT: ret 279entry: 280 %gep = getelementptr i16, ptr %base, i64 %offset 281 tail call void @llvm.aarch64.sve.prf.nxv8i1(<vscale x 8 x i1> %pg, ptr %gep, i32 13) 282 ret void 283} 284 285define void @test_svprfw_ss(<vscale x 4 x i1> %pg, ptr %base, i64 %offset) { 286; CHECK-LABEL: test_svprfw_ss: 287; CHECK: // %bb.0: // %entry 288; CHECK-NEXT: prfw pstl3strm, p0, [x0, x1, lsl #2] 289; CHECK-NEXT: ret 290entry: 291 %gep = getelementptr i32, ptr %base, i64 %offset 292 tail call void @llvm.aarch64.sve.prf.nxv4i1(<vscale x 4 x i1> %pg, ptr %gep, i32 13) 293 ret void 294} 295 296define void @test_svprfd_ss(<vscale x 2 x i1> %pg, ptr %base, i64 %offset) { 297; CHECK-LABEL: test_svprfd_ss: 298; CHECK: // %bb.0: // %entry 299; CHECK-NEXT: prfd pstl3strm, p0, [x0, x1, lsl #3] 300; CHECK-NEXT: ret 301entry: 302 %gep = getelementptr i64, ptr %base, i64 %offset 303 tail call void @llvm.aarch64.sve.prf.nxv2i1(<vscale x 2 x i1> %pg, ptr %gep, i32 13) 304 ret void 305} 306 307 308declare void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1>, ptr, i32) 309declare void @llvm.aarch64.sve.prf.nxv8i1(<vscale x 8 x i1>, ptr, i32) 310declare void @llvm.aarch64.sve.prf.nxv4i1(<vscale x 4 x i1>, ptr, i32) 311declare void @llvm.aarch64.sve.prf.nxv2i1(<vscale x 2 x i1>, ptr, i32) 312