xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-int-pred-reduce.ll (revision 1e02a29e4753ef70d7ce0ad90b7e4f29f1223006) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
3
4; ANDV
5
6define i1 @reduce_and_nxv16i1(<vscale x 16 x i1> %vec) {
7; CHECK-LABEL: reduce_and_nxv16i1:
8; CHECK:       // %bb.0:
9; CHECK-NEXT:    ptrue p1.b
10; CHECK-NEXT:    nots p0.b, p1/z, p0.b
11; CHECK-NEXT:    cset w0, eq
12; CHECK-NEXT:    ret
13  %res = call i1 @llvm.vector.reduce.and.i1.nxv16i1(<vscale x 16 x i1> %vec)
14  ret i1 %res
15}
16
17define i1 @reduce_and_nxv8i1(<vscale x 8 x i1> %vec) {
18; CHECK-LABEL: reduce_and_nxv8i1:
19; CHECK:       // %bb.0:
20; CHECK-NEXT:    ptrue p1.h
21; CHECK-NEXT:    nots p0.b, p1/z, p0.b
22; CHECK-NEXT:    cset w0, eq
23; CHECK-NEXT:    ret
24  %res = call i1 @llvm.vector.reduce.and.i1.nxv8i1(<vscale x 8 x i1> %vec)
25  ret i1 %res
26}
27
28define i1 @reduce_and_nxv4i1(<vscale x 4 x i1> %vec) {
29; CHECK-LABEL: reduce_and_nxv4i1:
30; CHECK:       // %bb.0:
31; CHECK-NEXT:    ptrue p1.s
32; CHECK-NEXT:    nots p0.b, p1/z, p0.b
33; CHECK-NEXT:    cset w0, eq
34; CHECK-NEXT:    ret
35  %res = call i1 @llvm.vector.reduce.and.i1.nxv4i1(<vscale x 4 x i1> %vec)
36  ret i1 %res
37}
38
39define i1 @reduce_and_nxv2i1(<vscale x 2 x i1> %vec) {
40; CHECK-LABEL: reduce_and_nxv2i1:
41; CHECK:       // %bb.0:
42; CHECK-NEXT:    ptrue p1.d
43; CHECK-NEXT:    nots p0.b, p1/z, p0.b
44; CHECK-NEXT:    cset w0, eq
45; CHECK-NEXT:    ret
46  %res = call i1 @llvm.vector.reduce.and.i1.nxv2i1(<vscale x 2 x i1> %vec)
47  ret i1 %res
48}
49
50define i1 @reduce_and_nxv1i1(<vscale x 1 x i1> %vec) {
51; CHECK-LABEL: reduce_and_nxv1i1:
52; CHECK:       // %bb.0:
53; CHECK-NEXT:    ptrue p1.d
54; CHECK-NEXT:    punpklo p2.h, p1.b
55; CHECK-NEXT:    eor p0.b, p1/z, p0.b, p2.b
56; CHECK-NEXT:    ptest p2, p0.b
57; CHECK-NEXT:    cset w0, eq
58; CHECK-NEXT:    ret
59  %res = call i1 @llvm.vector.reduce.and.i1.nxv1i1(<vscale x 1 x i1> %vec)
60  ret i1 %res
61}
62
63; ORV
64
65define i1 @reduce_or_nxv16i1(<vscale x 16 x i1> %vec) {
66; CHECK-LABEL: reduce_or_nxv16i1:
67; CHECK:       // %bb.0:
68; CHECK-NEXT:    ptest p0, p0.b
69; CHECK-NEXT:    cset w0, ne
70; CHECK-NEXT:    ret
71  %res = call i1 @llvm.vector.reduce.or.i1.nxv16i1(<vscale x 16 x i1> %vec)
72  ret i1 %res
73}
74
75define i1 @reduce_or_nxv8i1(<vscale x 8 x i1> %vec) {
76; CHECK-LABEL: reduce_or_nxv8i1:
77; CHECK:       // %bb.0:
78; CHECK-NEXT:    ptrue p1.h
79; CHECK-NEXT:    ptest p1, p0.b
80; CHECK-NEXT:    cset w0, ne
81; CHECK-NEXT:    ret
82  %res = call i1 @llvm.vector.reduce.or.i1.nxv8i1(<vscale x 8 x i1> %vec)
83  ret i1 %res
84}
85
86define i1 @reduce_or_nxv4i1(<vscale x 4 x i1> %vec) {
87; CHECK-LABEL: reduce_or_nxv4i1:
88; CHECK:       // %bb.0:
89; CHECK-NEXT:    ptrue p1.s
90; CHECK-NEXT:    ptest p1, p0.b
91; CHECK-NEXT:    cset w0, ne
92; CHECK-NEXT:    ret
93  %res = call i1 @llvm.vector.reduce.or.i1.nxv4i1(<vscale x 4 x i1> %vec)
94  ret i1 %res
95}
96
97define i1 @reduce_or_nxv2i1(<vscale x 2 x i1> %vec) {
98; CHECK-LABEL: reduce_or_nxv2i1:
99; CHECK:       // %bb.0:
100; CHECK-NEXT:    ptrue p1.d
101; CHECK-NEXT:    ptest p1, p0.b
102; CHECK-NEXT:    cset w0, ne
103; CHECK-NEXT:    ret
104  %res = call i1 @llvm.vector.reduce.or.i1.nxv2i1(<vscale x 2 x i1> %vec)
105  ret i1 %res
106}
107
108define i1 @reduce_or_nxv1i1(<vscale x 1 x i1> %vec) {
109; CHECK-LABEL: reduce_or_nxv1i1:
110; CHECK:       // %bb.0:
111; CHECK-NEXT:    ptrue p1.d
112; CHECK-NEXT:    punpklo p1.h, p1.b
113; CHECK-NEXT:    ptest p1, p0.b
114; CHECK-NEXT:    cset w0, ne
115; CHECK-NEXT:    ret
116  %res = call i1 @llvm.vector.reduce.or.i1.nxv1i1(<vscale x 1 x i1> %vec)
117  ret i1 %res
118}
119
120; XORV
121
122define i1 @reduce_xor_nxv16i1(<vscale x 16 x i1> %vec) {
123; CHECK-LABEL: reduce_xor_nxv16i1:
124; CHECK:       // %bb.0:
125; CHECK-NEXT:    ptrue p1.b
126; CHECK-NEXT:    cntp x8, p1, p0.b
127; CHECK-NEXT:    and w0, w8, #0x1
128; CHECK-NEXT:    ret
129  %res = call i1 @llvm.vector.reduce.xor.i1.nxv16i1(<vscale x 16 x i1> %vec)
130  ret i1 %res
131}
132
133define i1 @reduce_xor_nxv8i1(<vscale x 8 x i1> %vec) {
134; CHECK-LABEL: reduce_xor_nxv8i1:
135; CHECK:       // %bb.0:
136; CHECK-NEXT:    ptrue p1.h
137; CHECK-NEXT:    cntp x8, p1, p0.h
138; CHECK-NEXT:    and w0, w8, #0x1
139; CHECK-NEXT:    ret
140  %res = call i1 @llvm.vector.reduce.xor.i1.nxv8i1(<vscale x 8 x i1> %vec)
141  ret i1 %res
142}
143
144define i1 @reduce_xor_nxv4i1(<vscale x 4 x i1> %vec) {
145; CHECK-LABEL: reduce_xor_nxv4i1:
146; CHECK:       // %bb.0:
147; CHECK-NEXT:    ptrue p1.s
148; CHECK-NEXT:    cntp x8, p1, p0.s
149; CHECK-NEXT:    and w0, w8, #0x1
150; CHECK-NEXT:    ret
151  %res = call i1 @llvm.vector.reduce.xor.i1.nxv4i1(<vscale x 4 x i1> %vec)
152  ret i1 %res
153}
154
155define i1 @reduce_xor_nxv2i1(<vscale x 2 x i1> %vec) {
156; CHECK-LABEL: reduce_xor_nxv2i1:
157; CHECK:       // %bb.0:
158; CHECK-NEXT:    ptrue p1.d
159; CHECK-NEXT:    cntp x8, p1, p0.d
160; CHECK-NEXT:    and w0, w8, #0x1
161; CHECK-NEXT:    ret
162  %res = call i1 @llvm.vector.reduce.xor.i1.nxv2i1(<vscale x 2 x i1> %vec)
163  ret i1 %res
164}
165
166define i1 @reduce_xor_nxv1i1(<vscale x 1 x i1> %vec) {
167; CHECK-LABEL: reduce_xor_nxv1i1:
168; CHECK:       // %bb.0:
169; CHECK-NEXT:    ptrue p1.d
170; CHECK-NEXT:    punpklo p1.h, p1.b
171; CHECK-NEXT:    cntp x8, p1, p0.d
172; CHECK-NEXT:    and w0, w8, #0x1
173; CHECK-NEXT:    ret
174  %res = call i1 @llvm.vector.reduce.xor.i1.nxv1i1(<vscale x 1 x i1> %vec)
175  ret i1 %res
176}
177
178; SMAXV
179
180define i1 @reduce_smax_nxv16i1(<vscale x 16 x i1> %vec) {
181; CHECK-LABEL: reduce_smax_nxv16i1:
182; CHECK:       // %bb.0:
183; CHECK-NEXT:    ptrue p1.b
184; CHECK-NEXT:    nots p0.b, p1/z, p0.b
185; CHECK-NEXT:    cset w0, eq
186; CHECK-NEXT:    ret
187  %res = call i1 @llvm.vector.reduce.smax.i1.nxv16i1(<vscale x 16 x i1> %vec)
188  ret i1 %res
189}
190
191define i1 @reduce_smax_nxv8i1(<vscale x 8 x i1> %vec) {
192; CHECK-LABEL: reduce_smax_nxv8i1:
193; CHECK:       // %bb.0:
194; CHECK-NEXT:    ptrue p1.h
195; CHECK-NEXT:    nots p0.b, p1/z, p0.b
196; CHECK-NEXT:    cset w0, eq
197; CHECK-NEXT:    ret
198  %res = call i1 @llvm.vector.reduce.smax.i1.nxv8i1(<vscale x 8 x i1> %vec)
199  ret i1 %res
200}
201
202define i1 @reduce_smax_nxv4i1(<vscale x 4 x i1> %vec) {
203; CHECK-LABEL: reduce_smax_nxv4i1:
204; CHECK:       // %bb.0:
205; CHECK-NEXT:    ptrue p1.s
206; CHECK-NEXT:    nots p0.b, p1/z, p0.b
207; CHECK-NEXT:    cset w0, eq
208; CHECK-NEXT:    ret
209  %res = call i1 @llvm.vector.reduce.smax.i1.nxv4i1(<vscale x 4 x i1> %vec)
210  ret i1 %res
211}
212
213define i1 @reduce_smax_nxv2i1(<vscale x 2 x i1> %vec) {
214; CHECK-LABEL: reduce_smax_nxv2i1:
215; CHECK:       // %bb.0:
216; CHECK-NEXT:    ptrue p1.d
217; CHECK-NEXT:    nots p0.b, p1/z, p0.b
218; CHECK-NEXT:    cset w0, eq
219; CHECK-NEXT:    ret
220  %res = call i1 @llvm.vector.reduce.smax.i1.nxv2i1(<vscale x 2 x i1> %vec)
221  ret i1 %res
222}
223
224define i1 @reduce_smax_nxv1i1(<vscale x 1 x i1> %vec) {
225; CHECK-LABEL: reduce_smax_nxv1i1:
226; CHECK:       // %bb.0:
227; CHECK-NEXT:    ptrue p1.d
228; CHECK-NEXT:    punpklo p2.h, p1.b
229; CHECK-NEXT:    eor p0.b, p1/z, p0.b, p2.b
230; CHECK-NEXT:    ptest p2, p0.b
231; CHECK-NEXT:    cset w0, eq
232; CHECK-NEXT:    ret
233  %res = call i1 @llvm.vector.reduce.smax.i1.nxv1i1(<vscale x 1 x i1> %vec)
234  ret i1 %res
235}
236
237; SMINV
238
239define i1 @reduce_smin_nxv16i1(<vscale x 16 x i1> %vec) {
240; CHECK-LABEL: reduce_smin_nxv16i1:
241; CHECK:       // %bb.0:
242; CHECK-NEXT:    ptest p0, p0.b
243; CHECK-NEXT:    cset w0, ne
244; CHECK-NEXT:    ret
245  %res = call i1 @llvm.vector.reduce.smin.i1.nxv16i1(<vscale x 16 x i1> %vec)
246  ret i1 %res
247}
248
249define i1 @reduce_smin_nxv8i1(<vscale x 8 x i1> %vec) {
250; CHECK-LABEL: reduce_smin_nxv8i1:
251; CHECK:       // %bb.0:
252; CHECK-NEXT:    ptrue p1.h
253; CHECK-NEXT:    ptest p1, p0.b
254; CHECK-NEXT:    cset w0, ne
255; CHECK-NEXT:    ret
256  %res = call i1 @llvm.vector.reduce.smin.i1.nxv8i1(<vscale x 8 x i1> %vec)
257  ret i1 %res
258}
259
260define i1 @reduce_smin_nxv4i1(<vscale x 4 x i1> %vec) {
261; CHECK-LABEL: reduce_smin_nxv4i1:
262; CHECK:       // %bb.0:
263; CHECK-NEXT:    ptrue p1.s
264; CHECK-NEXT:    ptest p1, p0.b
265; CHECK-NEXT:    cset w0, ne
266; CHECK-NEXT:    ret
267  %res = call i1 @llvm.vector.reduce.smin.i1.nxv4i1(<vscale x 4 x i1> %vec)
268  ret i1 %res
269}
270
271define i1 @reduce_smin_nxv2i1(<vscale x 2 x i1> %vec) {
272; CHECK-LABEL: reduce_smin_nxv2i1:
273; CHECK:       // %bb.0:
274; CHECK-NEXT:    ptrue p1.d
275; CHECK-NEXT:    ptest p1, p0.b
276; CHECK-NEXT:    cset w0, ne
277; CHECK-NEXT:    ret
278  %res = call i1 @llvm.vector.reduce.smin.i1.nxv2i1(<vscale x 2 x i1> %vec)
279  ret i1 %res
280}
281
282define i1 @reduce_smin_nxv1i1(<vscale x 1 x i1> %vec) {
283; CHECK-LABEL: reduce_smin_nxv1i1:
284; CHECK:       // %bb.0:
285; CHECK-NEXT:    ptrue p1.d
286; CHECK-NEXT:    punpklo p1.h, p1.b
287; CHECK-NEXT:    ptest p1, p0.b
288; CHECK-NEXT:    cset w0, ne
289; CHECK-NEXT:    ret
290  %res = call i1 @llvm.vector.reduce.smin.i1.nxv1i1(<vscale x 1 x i1> %vec)
291  ret i1 %res
292}
293
294; UMAXV
295
296define i1 @reduce_umax_nxv16i1(<vscale x 16 x i1> %vec) {
297; CHECK-LABEL: reduce_umax_nxv16i1:
298; CHECK:       // %bb.0:
299; CHECK-NEXT:    ptest p0, p0.b
300; CHECK-NEXT:    cset w0, ne
301; CHECK-NEXT:    ret
302  %res = call i1 @llvm.vector.reduce.umax.i1.nxv16i1(<vscale x 16 x i1> %vec)
303  ret i1 %res
304}
305
306define i1 @reduce_umax_nxv8i1(<vscale x 8 x i1> %vec) {
307; CHECK-LABEL: reduce_umax_nxv8i1:
308; CHECK:       // %bb.0:
309; CHECK-NEXT:    ptrue p1.h
310; CHECK-NEXT:    ptest p1, p0.b
311; CHECK-NEXT:    cset w0, ne
312; CHECK-NEXT:    ret
313  %res = call i1 @llvm.vector.reduce.umax.i1.nxv8i1(<vscale x 8 x i1> %vec)
314  ret i1 %res
315}
316
317define i1 @reduce_umax_nxv4i1(<vscale x 4 x i1> %vec) {
318; CHECK-LABEL: reduce_umax_nxv4i1:
319; CHECK:       // %bb.0:
320; CHECK-NEXT:    ptrue p1.s
321; CHECK-NEXT:    ptest p1, p0.b
322; CHECK-NEXT:    cset w0, ne
323; CHECK-NEXT:    ret
324  %res = call i1 @llvm.vector.reduce.umax.i1.nxv4i1(<vscale x 4 x i1> %vec)
325  ret i1 %res
326}
327
328define i1 @reduce_umax_nxv2i1(<vscale x 2 x i1> %vec) {
329; CHECK-LABEL: reduce_umax_nxv2i1:
330; CHECK:       // %bb.0:
331; CHECK-NEXT:    ptrue p1.d
332; CHECK-NEXT:    ptest p1, p0.b
333; CHECK-NEXT:    cset w0, ne
334; CHECK-NEXT:    ret
335  %res = call i1 @llvm.vector.reduce.umax.i1.nxv2i1(<vscale x 2 x i1> %vec)
336  ret i1 %res
337}
338
339define i1 @reduce_umax_nxv1i1(<vscale x 1 x i1> %vec) {
340; CHECK-LABEL: reduce_umax_nxv1i1:
341; CHECK:       // %bb.0:
342; CHECK-NEXT:    ptrue p1.d
343; CHECK-NEXT:    punpklo p1.h, p1.b
344; CHECK-NEXT:    ptest p1, p0.b
345; CHECK-NEXT:    cset w0, ne
346; CHECK-NEXT:    ret
347  %res = call i1 @llvm.vector.reduce.umax.i1.nxv1i1(<vscale x 1 x i1> %vec)
348  ret i1 %res
349}
350
351; UMINV
352
353define i1 @reduce_umin_nxv16i1(<vscale x 16 x i1> %vec) {
354; CHECK-LABEL: reduce_umin_nxv16i1:
355; CHECK:       // %bb.0:
356; CHECK-NEXT:    ptrue p1.b
357; CHECK-NEXT:    nots p0.b, p1/z, p0.b
358; CHECK-NEXT:    cset w0, eq
359; CHECK-NEXT:    ret
360  %res = call i1 @llvm.vector.reduce.umin.i1.nxv16i1(<vscale x 16 x i1> %vec)
361  ret i1 %res
362}
363
364define i1 @reduce_umin_nxv8i1(<vscale x 8 x i1> %vec) {
365; CHECK-LABEL: reduce_umin_nxv8i1:
366; CHECK:       // %bb.0:
367; CHECK-NEXT:    ptrue p1.h
368; CHECK-NEXT:    nots p0.b, p1/z, p0.b
369; CHECK-NEXT:    cset w0, eq
370; CHECK-NEXT:    ret
371  %res = call i1 @llvm.vector.reduce.umin.i1.nxv8i1(<vscale x 8 x i1> %vec)
372  ret i1 %res
373}
374
375define i1 @reduce_umin_nxv4i1(<vscale x 4 x i1> %vec) {
376; CHECK-LABEL: reduce_umin_nxv4i1:
377; CHECK:       // %bb.0:
378; CHECK-NEXT:    ptrue p1.s
379; CHECK-NEXT:    nots p0.b, p1/z, p0.b
380; CHECK-NEXT:    cset w0, eq
381; CHECK-NEXT:    ret
382  %res = call i1 @llvm.vector.reduce.umin.i1.nxv4i1(<vscale x 4 x i1> %vec)
383  ret i1 %res
384}
385
386define i1 @reduce_umin_nxv1i1(<vscale x 1 x i1> %vec) {
387; CHECK-LABEL: reduce_umin_nxv1i1:
388; CHECK:       // %bb.0:
389; CHECK-NEXT:    ptrue p1.d
390; CHECK-NEXT:    punpklo p2.h, p1.b
391; CHECK-NEXT:    eor p0.b, p1/z, p0.b, p2.b
392; CHECK-NEXT:    ptest p2, p0.b
393; CHECK-NEXT:    cset w0, eq
394; CHECK-NEXT:    ret
395  %res = call i1 @llvm.vector.reduce.umin.i1.nxv1i1(<vscale x 1 x i1> %vec)
396  ret i1 %res
397}
398
399define i1 @reduce_umin_nxv2i1(<vscale x 2 x i1> %vec) {
400; CHECK-LABEL: reduce_umin_nxv2i1:
401; CHECK:       // %bb.0:
402; CHECK-NEXT:    ptrue p1.d
403; CHECK-NEXT:    nots p0.b, p1/z, p0.b
404; CHECK-NEXT:    cset w0, eq
405; CHECK-NEXT:    ret
406  %res = call i1 @llvm.vector.reduce.umin.i1.nxv2i1(<vscale x 2 x i1> %vec)
407  ret i1 %res
408}
409
410declare i1 @llvm.vector.reduce.and.i1.nxv16i1(<vscale x 16 x i1> %vec)
411declare i1 @llvm.vector.reduce.and.i1.nxv8i1(<vscale x 8 x i1> %vec)
412declare i1 @llvm.vector.reduce.and.i1.nxv4i1(<vscale x 4 x i1> %vec)
413declare i1 @llvm.vector.reduce.and.i1.nxv2i1(<vscale x 2 x i1> %vec)
414declare i1 @llvm.vector.reduce.and.i1.nxv1i1(<vscale x 1 x i1> %vec)
415
416declare i1 @llvm.vector.reduce.or.i1.nxv16i1(<vscale x 16 x i1> %vec)
417declare i1 @llvm.vector.reduce.or.i1.nxv8i1(<vscale x 8 x i1> %vec)
418declare i1 @llvm.vector.reduce.or.i1.nxv4i1(<vscale x 4 x i1> %vec)
419declare i1 @llvm.vector.reduce.or.i1.nxv2i1(<vscale x 2 x i1> %vec)
420declare i1 @llvm.vector.reduce.or.i1.nxv1i1(<vscale x 1 x i1> %vec)
421
422declare i1 @llvm.vector.reduce.xor.i1.nxv16i1(<vscale x 16 x i1> %vec)
423declare i1 @llvm.vector.reduce.xor.i1.nxv8i1(<vscale x 8 x i1> %vec)
424declare i1 @llvm.vector.reduce.xor.i1.nxv4i1(<vscale x 4 x i1> %vec)
425declare i1 @llvm.vector.reduce.xor.i1.nxv2i1(<vscale x 2 x i1> %vec)
426declare i1 @llvm.vector.reduce.xor.i1.nxv1i1(<vscale x 1 x i1> %vec)
427
428declare i1 @llvm.vector.reduce.smin.i1.nxv16i1(<vscale x 16 x i1> %vec)
429declare i1 @llvm.vector.reduce.smin.i1.nxv8i1(<vscale x 8 x i1> %vec)
430declare i1 @llvm.vector.reduce.smin.i1.nxv4i1(<vscale x 4 x i1> %vec)
431declare i1 @llvm.vector.reduce.smin.i1.nxv2i1(<vscale x 2 x i1> %vec)
432declare i1 @llvm.vector.reduce.smin.i1.nxv1i1(<vscale x 1 x i1> %vec)
433
434declare i1 @llvm.vector.reduce.smax.i1.nxv16i1(<vscale x 16 x i1> %vec)
435declare i1 @llvm.vector.reduce.smax.i1.nxv8i1(<vscale x 8 x i1> %vec)
436declare i1 @llvm.vector.reduce.smax.i1.nxv4i1(<vscale x 4 x i1> %vec)
437declare i1 @llvm.vector.reduce.smax.i1.nxv2i1(<vscale x 2 x i1> %vec)
438declare i1 @llvm.vector.reduce.smax.i1.nxv1i1(<vscale x 1 x i1> %vec)
439
440declare i1 @llvm.vector.reduce.umin.i1.nxv16i1(<vscale x 16 x i1> %vec)
441declare i1 @llvm.vector.reduce.umin.i1.nxv8i1(<vscale x 8 x i1> %vec)
442declare i1 @llvm.vector.reduce.umin.i1.nxv4i1(<vscale x 4 x i1> %vec)
443declare i1 @llvm.vector.reduce.umin.i1.nxv2i1(<vscale x 2 x i1> %vec)
444declare i1 @llvm.vector.reduce.umin.i1.nxv1i1(<vscale x 1 x i1> %vec)
445
446declare i1 @llvm.vector.reduce.umax.i1.nxv16i1(<vscale x 16 x i1> %vec)
447declare i1 @llvm.vector.reduce.umax.i1.nxv8i1(<vscale x 8 x i1> %vec)
448declare i1 @llvm.vector.reduce.umax.i1.nxv4i1(<vscale x 4 x i1> %vec)
449declare i1 @llvm.vector.reduce.umax.i1.nxv2i1(<vscale x 2 x i1> %vec)
450declare i1 @llvm.vector.reduce.umax.i1.nxv1i1(<vscale x 1 x i1> %vec)
451