xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-int-log.ll (revision 95e08824faba43a4fa052b9366dcea19e2268541) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
3
4define <vscale x 2 x i64> @and_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
5; CHECK-LABEL: and_d:
6; CHECK:       // %bb.0:
7; CHECK-NEXT:    and z0.d, z0.d, z1.d
8; CHECK-NEXT:    ret
9  %res = and <vscale x 2 x i64> %a, %b
10  ret <vscale x 2 x i64> %res
11}
12
13define <vscale x 4 x i32> @and_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
14; CHECK-LABEL: and_s:
15; CHECK:       // %bb.0:
16; CHECK-NEXT:    and z0.d, z0.d, z1.d
17; CHECK-NEXT:    ret
18  %res = and <vscale x 4 x i32> %a, %b
19  ret <vscale x 4 x i32> %res
20}
21
22define <vscale x 8 x i16> @and_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
23; CHECK-LABEL: and_h:
24; CHECK:       // %bb.0:
25; CHECK-NEXT:    and z0.d, z0.d, z1.d
26; CHECK-NEXT:    ret
27  %res = and <vscale x 8 x i16> %a, %b
28  ret <vscale x 8 x i16> %res
29}
30
31define <vscale x 16 x i8> @and_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
32; CHECK-LABEL: and_b:
33; CHECK:       // %bb.0:
34; CHECK-NEXT:    and z0.d, z0.d, z1.d
35; CHECK-NEXT:    ret
36  %res = and <vscale x 16 x i8> %a, %b
37  ret <vscale x 16 x i8> %res
38}
39
40define <vscale x 16 x i8> @and_b_zero(<vscale x 16 x i8> %a) {
41; CHECK-LABEL: and_b_zero:
42; CHECK:       // %bb.0:
43; CHECK-NEXT:    mov z0.b, #0 // =0x0
44; CHECK-NEXT:    ret
45  %res = and <vscale x 16 x i8> %a, zeroinitializer
46  ret <vscale x 16 x i8> %res
47}
48
49define <vscale x 1 x i1> @and_pred_q(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {
50; CHECK-LABEL: and_pred_q:
51; CHECK:       // %bb.0:
52; CHECK-NEXT:    and p0.b, p0/z, p0.b, p1.b
53; CHECK-NEXT:    ret
54  %res = and <vscale x 1 x i1> %a, %b
55  ret <vscale x 1 x i1> %res
56}
57
58define <vscale x 2 x i1> @and_pred_d(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {
59; CHECK-LABEL: and_pred_d:
60; CHECK:       // %bb.0:
61; CHECK-NEXT:    and p0.b, p0/z, p0.b, p1.b
62; CHECK-NEXT:    ret
63  %res = and <vscale x 2 x i1> %a, %b
64  ret <vscale x 2 x i1> %res
65}
66
67define <vscale x 4 x i1> @and_pred_s(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b) {
68; CHECK-LABEL: and_pred_s:
69; CHECK:       // %bb.0:
70; CHECK-NEXT:    and p0.b, p0/z, p0.b, p1.b
71; CHECK-NEXT:    ret
72  %res = and <vscale x 4 x i1> %a, %b
73  ret <vscale x 4 x i1> %res
74}
75
76define <vscale x 8 x i1> @and_pred_h(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b) {
77; CHECK-LABEL: and_pred_h:
78; CHECK:       // %bb.0:
79; CHECK-NEXT:    and p0.b, p0/z, p0.b, p1.b
80; CHECK-NEXT:    ret
81  %res = and <vscale x 8 x i1> %a, %b
82  ret <vscale x 8 x i1> %res
83}
84
85define <vscale x 16 x i1> @and_pred_b(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
86; CHECK-LABEL: and_pred_b:
87; CHECK:       // %bb.0:
88; CHECK-NEXT:    and p0.b, p0/z, p0.b, p1.b
89; CHECK-NEXT:    ret
90  %res = and <vscale x 16 x i1> %a, %b
91  ret <vscale x 16 x i1> %res
92}
93
94define <vscale x 2 x i64> @bic_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
95; CHECK-LABEL: bic_d:
96; CHECK:       // %bb.0:
97; CHECK-NEXT:    bic z0.d, z0.d, z1.d
98; CHECK-NEXT:    ret
99  %allones = shufflevector <vscale x 2 x i64> insertelement(<vscale x 2 x i64> undef, i64 -1, i32 0), <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
100  %not_b = xor <vscale x 2 x i64> %b, %allones
101  %res = and <vscale x 2 x i64> %a, %not_b
102  ret <vscale x 2 x i64> %res
103}
104
105define <vscale x 4 x i32> @bic_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
106; CHECK-LABEL: bic_s:
107; CHECK:       // %bb.0:
108; CHECK-NEXT:    bic z0.d, z0.d, z1.d
109; CHECK-NEXT:    ret
110  %allones = shufflevector <vscale x 4 x i32> insertelement(<vscale x 4 x i32> undef, i32 -1, i32 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
111  %not_b = xor <vscale x 4 x i32> %b, %allones
112  %res = and <vscale x 4 x i32> %a, %not_b
113  ret <vscale x 4 x i32> %res
114}
115
116define <vscale x 8 x i16> @bic_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
117; CHECK-LABEL: bic_h:
118; CHECK:       // %bb.0:
119; CHECK-NEXT:    bic z0.d, z0.d, z1.d
120; CHECK-NEXT:    ret
121  %allones = shufflevector <vscale x 8 x i16> insertelement(<vscale x 8 x i16> undef, i16 -1, i32 0), <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
122  %not_b = xor <vscale x 8 x i16> %b, %allones
123  %res = and <vscale x 8 x i16> %a, %not_b
124  ret <vscale x 8 x i16> %res
125}
126
127define <vscale x 16 x i8> @bic_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
128; CHECK-LABEL: bic_b:
129; CHECK:       // %bb.0:
130; CHECK-NEXT:    bic z0.d, z0.d, z1.d
131; CHECK-NEXT:    ret
132  %allones = shufflevector <vscale x 16 x i8> insertelement(<vscale x 16 x i8> undef, i8 -1, i32 0), <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
133  %not_b = xor <vscale x 16 x i8> %b, %allones
134  %res = and <vscale x 16 x i8> %a, %not_b
135  ret <vscale x 16 x i8> %res
136}
137
138define <vscale x 1 x i1> @bic_pred_q(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {
139; CHECK-LABEL: bic_pred_q:
140; CHECK:       // %bb.0:
141; CHECK-NEXT:    bic p0.b, p0/z, p0.b, p1.b
142; CHECK-NEXT:    ret
143  %allones = shufflevector <vscale x 1 x i1> insertelement(<vscale x 1 x i1> undef, i1 true, i32 0), <vscale x 1 x i1> undef, <vscale x 1 x i32> zeroinitializer
144  %not_b = xor <vscale x 1 x i1> %b, %allones
145  %res = and <vscale x 1 x i1> %a, %not_b
146  ret <vscale x 1 x i1> %res
147}
148
149define <vscale x 2 x i1> @bic_pred_d(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {
150; CHECK-LABEL: bic_pred_d:
151; CHECK:       // %bb.0:
152; CHECK-NEXT:    bic p0.b, p0/z, p0.b, p1.b
153; CHECK-NEXT:    ret
154  %allones = shufflevector <vscale x 2 x i1> insertelement(<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
155  %not_b = xor <vscale x 2 x i1> %b, %allones
156  %res = and <vscale x 2 x i1> %a, %not_b
157  ret <vscale x 2 x i1> %res
158}
159
160define <vscale x 4 x i1> @bic_pred_s(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b) {
161; CHECK-LABEL: bic_pred_s:
162; CHECK:       // %bb.0:
163; CHECK-NEXT:    bic p0.b, p0/z, p0.b, p1.b
164; CHECK-NEXT:    ret
165  %allones = shufflevector <vscale x 4 x i1> insertelement(<vscale x 4 x i1> undef, i1 true, i32 0), <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
166  %not_b = xor <vscale x 4 x i1> %b, %allones
167  %res = and <vscale x 4 x i1> %a, %not_b
168  ret <vscale x 4 x i1> %res
169}
170
171define <vscale x 8 x i1> @bic_pred_h(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b) {
172; CHECK-LABEL: bic_pred_h:
173; CHECK:       // %bb.0:
174; CHECK-NEXT:    bic p0.b, p0/z, p0.b, p1.b
175; CHECK-NEXT:    ret
176  %allones = shufflevector <vscale x 8 x i1> insertelement(<vscale x 8 x i1> undef, i1 true, i32 0), <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
177  %not_b = xor <vscale x 8 x i1> %b, %allones
178  %res = and <vscale x 8 x i1> %a, %not_b
179  ret <vscale x 8 x i1> %res
180}
181
182define <vscale x 16 x i1> @bic_pred_b(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
183; CHECK-LABEL: bic_pred_b:
184; CHECK:       // %bb.0:
185; CHECK-NEXT:    bic p0.b, p0/z, p0.b, p1.b
186; CHECK-NEXT:    ret
187  %allones = shufflevector <vscale x 16 x i1> insertelement(<vscale x 16 x i1> undef, i1 true, i32 0), <vscale x 16 x i1> undef, <vscale x 16 x i32> zeroinitializer
188  %not_b = xor <vscale x 16 x i1> %b, %allones
189  %res = and <vscale x 16 x i1> %a, %not_b
190  ret <vscale x 16 x i1> %res
191}
192
193define <vscale x 2 x i64> @or_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
194; CHECK-LABEL: or_d:
195; CHECK:       // %bb.0:
196; CHECK-NEXT:    orr z0.d, z0.d, z1.d
197; CHECK-NEXT:    ret
198  %res = or <vscale x 2 x i64> %a, %b
199  ret <vscale x 2 x i64> %res
200}
201
202define <vscale x 4 x i32> @or_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
203; CHECK-LABEL: or_s:
204; CHECK:       // %bb.0:
205; CHECK-NEXT:    orr z0.d, z0.d, z1.d
206; CHECK-NEXT:    ret
207  %res = or <vscale x 4 x i32> %a, %b
208  ret <vscale x 4 x i32> %res
209}
210
211define <vscale x 8 x i16> @or_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
212; CHECK-LABEL: or_h:
213; CHECK:       // %bb.0:
214; CHECK-NEXT:    orr z0.d, z0.d, z1.d
215; CHECK-NEXT:    ret
216  %res = or <vscale x 8 x i16> %a, %b
217  ret <vscale x 8 x i16> %res
218}
219
220define <vscale x 16 x i8> @or_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
221; CHECK-LABEL: or_b:
222; CHECK:       // %bb.0:
223; CHECK-NEXT:    orr z0.d, z0.d, z1.d
224; CHECK-NEXT:    ret
225  %res = or <vscale x 16 x i8> %a, %b
226  ret <vscale x 16 x i8> %res
227}
228
229define <vscale x 16 x i8> @or_b_zero(<vscale x 16 x i8> %a) {
230; CHECK-LABEL: or_b_zero:
231; CHECK:       // %bb.0:
232; CHECK-NEXT:    ret
233  %res = or <vscale x 16 x i8> %a, zeroinitializer
234  ret <vscale x 16 x i8> %res
235}
236
237define <vscale x 1 x i1> @or_pred_q(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {
238; CHECK-LABEL: or_pred_q:
239; CHECK:       // %bb.0:
240; CHECK-NEXT:    sel p0.b, p0, p0.b, p1.b
241; CHECK-NEXT:    ret
242  %res = or <vscale x 1 x i1> %a, %b
243  ret <vscale x 1 x i1> %res
244}
245
246define <vscale x 2 x i1> @or_pred_d(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {
247; CHECK-LABEL: or_pred_d:
248; CHECK:       // %bb.0:
249; CHECK-NEXT:    sel p0.b, p0, p0.b, p1.b
250; CHECK-NEXT:    ret
251  %res = or <vscale x 2 x i1> %a, %b
252  ret <vscale x 2 x i1> %res
253}
254
255define <vscale x 4 x i1> @or_pred_s(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b) {
256; CHECK-LABEL: or_pred_s:
257; CHECK:       // %bb.0:
258; CHECK-NEXT:    sel p0.b, p0, p0.b, p1.b
259; CHECK-NEXT:    ret
260  %res = or <vscale x 4 x i1> %a, %b
261  ret <vscale x 4 x i1> %res
262}
263
264define <vscale x 8 x i1> @or_pred_h(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b) {
265; CHECK-LABEL: or_pred_h:
266; CHECK:       // %bb.0:
267; CHECK-NEXT:    sel p0.b, p0, p0.b, p1.b
268; CHECK-NEXT:    ret
269  %res = or <vscale x 8 x i1> %a, %b
270  ret <vscale x 8 x i1> %res
271}
272
273define <vscale x 16 x i1> @or_pred_b(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
274; CHECK-LABEL: or_pred_b:
275; CHECK:       // %bb.0:
276; CHECK-NEXT:    sel p0.b, p0, p0.b, p1.b
277; CHECK-NEXT:    ret
278  %res = or <vscale x 16 x i1> %a, %b
279  ret <vscale x 16 x i1> %res
280}
281
282define <vscale x 2 x i64> @xor_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
283; CHECK-LABEL: xor_d:
284; CHECK:       // %bb.0:
285; CHECK-NEXT:    eor z0.d, z0.d, z1.d
286; CHECK-NEXT:    ret
287  %res = xor <vscale x 2 x i64> %a, %b
288  ret <vscale x 2 x i64> %res
289}
290
291define <vscale x 4 x i32> @xor_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
292; CHECK-LABEL: xor_s:
293; CHECK:       // %bb.0:
294; CHECK-NEXT:    eor z0.d, z0.d, z1.d
295; CHECK-NEXT:    ret
296  %res = xor <vscale x 4 x i32> %a, %b
297  ret <vscale x 4 x i32> %res
298}
299
300define <vscale x 8 x i16> @xor_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
301; CHECK-LABEL: xor_h:
302; CHECK:       // %bb.0:
303; CHECK-NEXT:    eor z0.d, z0.d, z1.d
304; CHECK-NEXT:    ret
305  %res = xor <vscale x 8 x i16> %a, %b
306  ret <vscale x 8 x i16> %res
307}
308
309define <vscale x 16 x i8> @xor_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
310; CHECK-LABEL: xor_b:
311; CHECK:       // %bb.0:
312; CHECK-NEXT:    eor z0.d, z0.d, z1.d
313; CHECK-NEXT:    ret
314  %res = xor <vscale x 16 x i8> %a, %b
315  ret <vscale x 16 x i8> %res
316}
317
318define <vscale x 16 x i8> @xor_b_zero(<vscale x 16 x i8> %a) {
319; CHECK-LABEL: xor_b_zero:
320; CHECK:       // %bb.0:
321; CHECK-NEXT:    ret
322  %res = xor <vscale x 16 x i8> %a, zeroinitializer
323  ret <vscale x 16 x i8> %res
324}
325
326define <vscale x 1 x i1> @xor_pred_q(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {
327; CHECK-LABEL: xor_pred_q:
328; CHECK:       // %bb.0:
329; CHECK-NEXT:    ptrue p2.d
330; CHECK-NEXT:    eor p0.b, p2/z, p0.b, p1.b
331; CHECK-NEXT:    ret
332  %res = xor <vscale x 1 x i1> %a, %b
333  ret <vscale x 1 x i1> %res
334}
335
336define <vscale x 2 x i1> @xor_pred_d(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {
337; CHECK-LABEL: xor_pred_d:
338; CHECK:       // %bb.0:
339; CHECK-NEXT:    ptrue p2.d
340; CHECK-NEXT:    eor p0.b, p2/z, p0.b, p1.b
341; CHECK-NEXT:    ret
342  %res = xor <vscale x 2 x i1> %a, %b
343  ret <vscale x 2 x i1> %res
344}
345
346define <vscale x 4 x i1> @xor_pred_s(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b) {
347; CHECK-LABEL: xor_pred_s:
348; CHECK:       // %bb.0:
349; CHECK-NEXT:    ptrue p2.s
350; CHECK-NEXT:    eor p0.b, p2/z, p0.b, p1.b
351; CHECK-NEXT:    ret
352  %res = xor <vscale x 4 x i1> %a, %b
353  ret <vscale x 4 x i1> %res
354}
355
356define <vscale x 8 x i1> @xor_pred_h(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b) {
357; CHECK-LABEL: xor_pred_h:
358; CHECK:       // %bb.0:
359; CHECK-NEXT:    ptrue p2.h
360; CHECK-NEXT:    eor p0.b, p2/z, p0.b, p1.b
361; CHECK-NEXT:    ret
362  %res = xor <vscale x 8 x i1> %a, %b
363  ret <vscale x 8 x i1> %res
364}
365
366define <vscale x 16 x i1> @xor_pred_b(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
367; CHECK-LABEL: xor_pred_b:
368; CHECK:       // %bb.0:
369; CHECK-NEXT:    ptrue p2.b
370; CHECK-NEXT:    eor p0.b, p2/z, p0.b, p1.b
371; CHECK-NEXT:    ret
372  %res = xor <vscale x 16 x i1> %a, %b
373  ret <vscale x 16 x i1> %res
374}
375