xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-insr.ll (revision 354604a2a7149b5efd52134efa4765cf8c32e386) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu < %s | FileCheck %s
3
4define <vscale x 16 x i8> @insr_zpr_only_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
5; CHECK-LABEL: insr_zpr_only_nxv16i8:
6; CHECK:       // %bb.0:
7; CHECK-NEXT:    insr z0.b, b1
8; CHECK-NEXT:    ret
9  %t0 = extractelement <vscale x 16 x i8> %b, i64 0
10  %t1 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.insr.nxv16i8(<vscale x 16 x i8> %a, i8 %t0)
11  ret <vscale x 16 x i8> %t1
12}
13
14define <vscale x 8 x i16> @insr_zpr_only_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
15; CHECK-LABEL: insr_zpr_only_nxv8i16:
16; CHECK:       // %bb.0:
17; CHECK-NEXT:    insr z0.h, h1
18; CHECK-NEXT:    ret
19  %t0 = extractelement <vscale x 8 x i16> %b, i64 0
20  %t1 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.insr.nxv8i16(<vscale x 8 x i16> %a, i16 %t0)
21  ret <vscale x 8 x i16> %t1
22}
23
24define <vscale x 4 x i32> @insr_zpr_only_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
25; CHECK-LABEL: insr_zpr_only_nxv4i32:
26; CHECK:       // %bb.0:
27; CHECK-NEXT:    insr z0.s, s1
28; CHECK-NEXT:    ret
29  %t0 = extractelement <vscale x 4 x i32> %b, i64 0
30  %t1 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.insr.nxv4i32(<vscale x 4 x i32> %a, i32 %t0)
31  ret <vscale x 4 x i32> %t1
32}
33
34define <vscale x 2 x i64> @insr_zpr_only_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
35; CHECK-LABEL: insr_zpr_only_nxv2i64:
36; CHECK:       // %bb.0:
37; CHECK-NEXT:    insr z0.d, d1
38; CHECK-NEXT:    ret
39  %t0 = extractelement <vscale x 2 x i64> %b, i64 0
40  %t1 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.insr.nxv2i64(<vscale x 2 x i64> %a, i64 %t0)
41  ret <vscale x 2 x i64> %t1
42}
43
44declare <vscale x 16 x i8> @llvm.aarch64.sve.insr.nxv16i8(<vscale x 16 x i8>, i8)
45declare <vscale x 8 x i16> @llvm.aarch64.sve.insr.nxv8i16(<vscale x 8 x i16>, i16)
46declare <vscale x 4 x i32> @llvm.aarch64.sve.insr.nxv4i32(<vscale x 4 x i32>, i32)
47declare <vscale x 2 x i64> @llvm.aarch64.sve.insr.nxv2i64(<vscale x 2 x i64>, i64)
48
49attributes #0 = { "target-features"="+sve" }
50