1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s 3 4; 128-bit vectors 5 6define <16 x i8> @v16i8() #0 { 7; CHECK-LABEL: v16i8: 8; CHECK: // %bb.0: 9; CHECK-NEXT: index z0.b, #0, #1 10; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 11; CHECK-NEXT: ret 12 ret <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15> 13} 14 15define <8 x i16> @v8i16() #0 { 16; CHECK-LABEL: v8i16: 17; CHECK: // %bb.0: 18; CHECK-NEXT: index z0.h, #0, #1 19; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 20; CHECK-NEXT: ret 21 ret <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7> 22} 23 24define <4 x i32> @v4i32() #0 { 25; CHECK-LABEL: v4i32: 26; CHECK: // %bb.0: 27; CHECK-NEXT: index z0.s, #0, #1 28; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 29; CHECK-NEXT: ret 30 ret <4 x i32> <i32 0, i32 1, i32 2, i32 3> 31} 32 33define <2 x i64> @v2i64() #0 { 34; CHECK-LABEL: v2i64: 35; CHECK: // %bb.0: 36; CHECK-NEXT: index z0.d, #0, #1 37; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 38; CHECK-NEXT: ret 39 ret <2 x i64> <i64 0, i64 1> 40} 41 42; 64-bit vectors 43 44define <8 x i8> @v8i8() #0 { 45; CHECK-LABEL: v8i8: 46; CHECK: // %bb.0: 47; CHECK-NEXT: index z0.b, #0, #1 48; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 49; CHECK-NEXT: ret 50 ret <8 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7> 51} 52 53define <4 x i16> @v4i16() #0 { 54; CHECK-LABEL: v4i16: 55; CHECK: // %bb.0: 56; CHECK-NEXT: index z0.h, #0, #1 57; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 58; CHECK-NEXT: ret 59 ret <4 x i16> <i16 0, i16 1, i16 2, i16 3> 60} 61 62define <2 x i32> @v2i32() #0 { 63; CHECK-LABEL: v2i32: 64; CHECK: // %bb.0: 65; CHECK-NEXT: index z0.s, #0, #1 66; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 67; CHECK-NEXT: ret 68 ret <2 x i32> <i32 0, i32 1> 69} 70 71; Positive test, non-zero start and non-unitary step. 72; Note: This should be INDEX z0.s, #1, #2 (without the ORR). 73define <4 x i32> @v4i32_non_zero_non_one() #0 { 74; CHECK-LABEL: v4i32_non_zero_non_one: 75; CHECK: // %bb.0: 76; CHECK-NEXT: index z0.s, #0, #2 77; CHECK-NEXT: orr z0.s, z0.s, #0x1 78; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 79; CHECK-NEXT: ret 80 ret <4 x i32> <i32 1, i32 3, i32 5, i32 7> 81} 82 83; Positive test, same as above but negative immediates. 84define <4 x i32> @v4i32_neg_immediates() #0 { 85; CHECK-LABEL: v4i32_neg_immediates: 86; CHECK: // %bb.0: 87; CHECK-NEXT: index z0.s, #-1, #-2 88; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 89; CHECK-NEXT: ret 90 ret <4 x i32> <i32 -1, i32 -3, i32 -5, i32 -7> 91} 92 93; Positive test, out of imm range start. 94define <4 x i32> @v4i32_out_range_start() #0 { 95; CHECK-LABEL: v4i32_out_range_start: 96; CHECK: // %bb.0: 97; CHECK-NEXT: index z0.s, #0, #1 98; CHECK-NEXT: add z0.s, z0.s, #16 // =0x10 99; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 100; CHECK-NEXT: ret 101 ret <4 x i32> <i32 16, i32 17, i32 18, i32 19> 102} 103 104; Positive test, out of imm range step. 105define <4 x i32> @v4i32_out_range_step() #0 { 106; CHECK-LABEL: v4i32_out_range_step: 107; CHECK: // %bb.0: 108; CHECK-NEXT: mov w8, #16 // =0x10 109; CHECK-NEXT: index z0.s, #0, w8 110; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 111; CHECK-NEXT: ret 112 ret <4 x i32> <i32 0, i32 16, i32 32, i32 48> 113} 114 115; Positive test, out of imm range start and step. 116define <4 x i32> @v4i32_out_range_start_step() #0 { 117; CHECK-LABEL: v4i32_out_range_start_step: 118; CHECK: // %bb.0: 119; CHECK-NEXT: mov w8, #16 // =0x10 120; CHECK-NEXT: index z0.s, #0, w8 121; CHECK-NEXT: add z0.s, z0.s, #16 // =0x10 122; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 123; CHECK-NEXT: ret 124 ret <4 x i32> <i32 16, i32 32, i32 48, i32 64> 125} 126 127; Negative test, non sequential. 128define <4 x i32> @v4i32_non_sequential() #0 { 129; CHECK-LABEL: v4i32_non_sequential: 130; CHECK: // %bb.0: 131; CHECK-NEXT: adrp x8, .LCPI12_0 132; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI12_0] 133; CHECK-NEXT: ret 134 ret <4 x i32> <i32 0, i32 2, i32 2, i32 3> 135} 136