1 2; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mcpu=neoverse-v1 -O3 -aarch64-sve-vector-bits-min=256 -verify-machineinstrs | FileCheck %s --check-prefixes=SVE256 3; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mcpu=neoverse-v1 -O3 -aarch64-sve-vector-bits-min=128 -verify-machineinstrs | FileCheck %s --check-prefixes=NEON 4; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mcpu=neoverse-n1 -O3 -verify-machineinstrs | FileCheck %s --check-prefixes=NEON 5; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mcpu=neoverse-v2 -O3 -verify-machineinstrs | FileCheck %s --check-prefixes=NEON 6 7define internal i32 @test(ptr nocapture readonly %p1, i32 %i1, ptr nocapture readonly %p2, i32 %i2) { 8; SVE256-LABEL: test: 9; SVE256: ld1b { z0.h }, p0/z, 10; SVE256: ld1b { z1.h }, p0/z, 11; SVE256: sub z0.h, z0.h, z1.h 12; SVE256-NEXT: sunpklo z1.s, z0.h 13; SVE256-NEXT: ext z0.b, z0.b, z0.b, #16 14; SVE256-NEXT: sunpklo z0.s, z0.h 15; SVE256-NEXT: add z0.s, z1.s, z0.s 16; SVE256-NEXT: uaddv d0, p1, z0.s 17 18; NEON-LABEL: test: 19; NEON: ldr q0, [x0, w9, sxtw] 20; NEON: ldr q1, [x2, w10, sxtw] 21; NEON: usubl2 v2.8h, v0.16b, v1.16b 22; NEON-NEXT: usubl v0.8h, v0.8b, v1.8b 23; NEON: saddl2 v1.4s, v0.8h, v2.8h 24; NEON-NEXT: saddl v0.4s, v0.4h, v2.4h 25; NEON-NEXT: add v0.4s, v0.4s, v1.4s 26; NEON-NEXT: addv s0, v0.4s 27 28L.entry: 29 br label %L1 30 31L1: ; preds = %L1, %L.entry 32 %a = phi i32 [ 16, %L.entry ], [ %14, %L1 ] 33 %b = phi i32 [ 0, %L.entry ], [ %13, %L1 ] 34 %i = phi i32 [ 0, %L.entry ], [ %12, %L1 ] 35 %0 = mul i32 %b, %i1 36 %1 = sext i32 %0 to i64 37 %2 = getelementptr i8, ptr %p1, i64 %1 38 %3 = mul i32 %b, %i2 39 %4 = sext i32 %3 to i64 40 %5 = getelementptr i8, ptr %p2, i64 %4 41 %6 = load <16 x i8>, ptr %2, align 1 42 %7 = zext <16 x i8> %6 to <16 x i32> 43 %8 = load <16 x i8>, ptr %5, align 1 44 %9 = zext <16 x i8> %8 to <16 x i32> 45 %10 = sub nsw <16 x i32> %7, %9 46 %11 = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %10) 47 %12 = add i32 %11, %i 48 %13 = add nuw nsw i32 %b, 1 49 %14 = add nsw i32 %a, -1 50 %.not = icmp eq i32 %14, 0 51 br i1 %.not, label %L2, label %L1 52 53L2: ; preds = %L1 54 ret i32 %12 55} 56 57declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>) 58