xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-fixed-vector-lrint.ll (revision 109ede496ecf6de5dabace08d73ec7604b343a6b) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=aarch64 -mattr=+sve \
3; RUN:   -aarch64-sve-vector-bits-min=256 | FileCheck --check-prefixes=CHECK-i32 %s
4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=aarch64 -mattr=+sve \
5; RUN:   -aarch64-sve-vector-bits-min=256 | FileCheck --check-prefixes=CHECK-i64 %s
6
7define <1 x iXLen> @lrint_v1f16(<1 x half> %x) {
8; CHECK-i32-LABEL: lrint_v1f16:
9; CHECK-i32:       // %bb.0:
10; CHECK-i32-NEXT:    frintx h0, h0
11; CHECK-i32-NEXT:    fcvtzs w8, h0
12; CHECK-i32-NEXT:    fmov s0, w8
13; CHECK-i32-NEXT:    ret
14;
15; CHECK-i64-LABEL: lrint_v1f16:
16; CHECK-i64:       // %bb.0:
17; CHECK-i64-NEXT:    frintx h0, h0
18; CHECK-i64-NEXT:    fcvtzs x8, h0
19; CHECK-i64-NEXT:    fmov d0, x8
20; CHECK-i64-NEXT:    ret
21  %a = call <1 x iXLen> @llvm.lrint.v1iXLen.v1f16(<1 x half> %x)
22  ret <1 x iXLen> %a
23}
24declare <1 x iXLen> @llvm.lrint.v1iXLen.v1f16(<1 x half>)
25
26define <2 x iXLen> @lrint_v2f16(<2 x half> %x) {
27; CHECK-i32-LABEL: lrint_v2f16:
28; CHECK-i32:       // %bb.0:
29; CHECK-i32-NEXT:    // kill: def $d0 killed $d0 def $q0
30; CHECK-i32-NEXT:    mov h1, v0.h[1]
31; CHECK-i32-NEXT:    frintx h0, h0
32; CHECK-i32-NEXT:    frintx h1, h1
33; CHECK-i32-NEXT:    fcvtzs w8, h0
34; CHECK-i32-NEXT:    fcvtzs w9, h1
35; CHECK-i32-NEXT:    fmov s0, w8
36; CHECK-i32-NEXT:    mov v0.s[1], w9
37; CHECK-i32-NEXT:    // kill: def $d0 killed $d0 killed $q0
38; CHECK-i32-NEXT:    ret
39;
40; CHECK-i64-LABEL: lrint_v2f16:
41; CHECK-i64:       // %bb.0:
42; CHECK-i64-NEXT:    // kill: def $d0 killed $d0 def $q0
43; CHECK-i64-NEXT:    mov h1, v0.h[1]
44; CHECK-i64-NEXT:    frintx h0, h0
45; CHECK-i64-NEXT:    frintx h1, h1
46; CHECK-i64-NEXT:    fcvtzs x8, h0
47; CHECK-i64-NEXT:    fcvtzs x9, h1
48; CHECK-i64-NEXT:    fmov d0, x8
49; CHECK-i64-NEXT:    mov v0.d[1], x9
50; CHECK-i64-NEXT:    ret
51  %a = call <2 x iXLen> @llvm.lrint.v2iXLen.v2f16(<2 x half> %x)
52  ret <2 x iXLen> %a
53}
54declare <2 x iXLen> @llvm.lrint.v2iXLen.v2f16(<2 x half>)
55
56define <4 x iXLen> @lrint_v4f16(<4 x half> %x) {
57; CHECK-i32-LABEL: lrint_v4f16:
58; CHECK-i32:       // %bb.0:
59; CHECK-i32-NEXT:    frintx v0.4h, v0.4h
60; CHECK-i32-NEXT:    fcvtl v0.4s, v0.4h
61; CHECK-i32-NEXT:    fcvtzs v0.4s, v0.4s
62; CHECK-i32-NEXT:    ret
63;
64; CHECK-i64-LABEL: lrint_v4f16:
65; CHECK-i64:       // %bb.0:
66; CHECK-i64-NEXT:    frintx v0.4h, v0.4h
67; CHECK-i64-NEXT:    mov h1, v0.h[2]
68; CHECK-i64-NEXT:    mov h2, v0.h[3]
69; CHECK-i64-NEXT:    mov h3, v0.h[1]
70; CHECK-i64-NEXT:    fcvtzs x9, h0
71; CHECK-i64-NEXT:    fcvtzs x8, h1
72; CHECK-i64-NEXT:    fcvtzs x10, h2
73; CHECK-i64-NEXT:    fcvtzs x11, h3
74; CHECK-i64-NEXT:    fmov d0, x9
75; CHECK-i64-NEXT:    fmov d1, x8
76; CHECK-i64-NEXT:    mov v0.d[1], x11
77; CHECK-i64-NEXT:    mov v1.d[1], x10
78; CHECK-i64-NEXT:    ret
79  %a = call <4 x iXLen> @llvm.lrint.v4iXLen.v4f16(<4 x half> %x)
80  ret <4 x iXLen> %a
81}
82declare <4 x iXLen> @llvm.lrint.v4iXLen.v4f16(<4 x half>)
83
84define <8 x iXLen> @lrint_v8f16(<8 x half> %x) {
85; CHECK-i32-LABEL: lrint_v8f16:
86; CHECK-i32:       // %bb.0:
87; CHECK-i32-NEXT:    frintx v2.8h, v0.8h
88; CHECK-i32-NEXT:    mov h0, v2.h[4]
89; CHECK-i32-NEXT:    mov h1, v2.h[5]
90; CHECK-i32-NEXT:    mov h3, v2.h[1]
91; CHECK-i32-NEXT:    fcvtzs w9, h2
92; CHECK-i32-NEXT:    mov h4, v2.h[6]
93; CHECK-i32-NEXT:    fcvtzs w8, h0
94; CHECK-i32-NEXT:    mov h0, v2.h[2]
95; CHECK-i32-NEXT:    fcvtzs w10, h1
96; CHECK-i32-NEXT:    fcvtzs w11, h3
97; CHECK-i32-NEXT:    mov h3, v2.h[7]
98; CHECK-i32-NEXT:    fcvtzs w12, h4
99; CHECK-i32-NEXT:    mov h2, v2.h[3]
100; CHECK-i32-NEXT:    fcvtzs w13, h0
101; CHECK-i32-NEXT:    fmov s0, w9
102; CHECK-i32-NEXT:    fmov s1, w8
103; CHECK-i32-NEXT:    fcvtzs w8, h3
104; CHECK-i32-NEXT:    fcvtzs w9, h2
105; CHECK-i32-NEXT:    mov v0.s[1], w11
106; CHECK-i32-NEXT:    mov v1.s[1], w10
107; CHECK-i32-NEXT:    mov v0.s[2], w13
108; CHECK-i32-NEXT:    mov v1.s[2], w12
109; CHECK-i32-NEXT:    mov v0.s[3], w9
110; CHECK-i32-NEXT:    mov v1.s[3], w8
111; CHECK-i32-NEXT:    ret
112;
113; CHECK-i64-LABEL: lrint_v8f16:
114; CHECK-i64:       // %bb.0:
115; CHECK-i64-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
116; CHECK-i64-NEXT:    frintx v0.4h, v0.4h
117; CHECK-i64-NEXT:    frintx v1.4h, v1.4h
118; CHECK-i64-NEXT:    mov h4, v0.h[2]
119; CHECK-i64-NEXT:    mov h2, v0.h[1]
120; CHECK-i64-NEXT:    mov h7, v0.h[3]
121; CHECK-i64-NEXT:    fcvtzs x8, h0
122; CHECK-i64-NEXT:    mov h3, v1.h[2]
123; CHECK-i64-NEXT:    mov h5, v1.h[3]
124; CHECK-i64-NEXT:    mov h6, v1.h[1]
125; CHECK-i64-NEXT:    fcvtzs x11, h1
126; CHECK-i64-NEXT:    fcvtzs x12, h4
127; CHECK-i64-NEXT:    fcvtzs x9, h2
128; CHECK-i64-NEXT:    fcvtzs x15, h7
129; CHECK-i64-NEXT:    fmov d0, x8
130; CHECK-i64-NEXT:    fcvtzs x10, h3
131; CHECK-i64-NEXT:    fcvtzs x13, h5
132; CHECK-i64-NEXT:    fcvtzs x14, h6
133; CHECK-i64-NEXT:    fmov d1, x12
134; CHECK-i64-NEXT:    fmov d2, x11
135; CHECK-i64-NEXT:    mov v0.d[1], x9
136; CHECK-i64-NEXT:    fmov d3, x10
137; CHECK-i64-NEXT:    mov v1.d[1], x15
138; CHECK-i64-NEXT:    mov v2.d[1], x14
139; CHECK-i64-NEXT:    mov v3.d[1], x13
140; CHECK-i64-NEXT:    ret
141  %a = call <8 x iXLen> @llvm.lrint.v8iXLen.v8f16(<8 x half> %x)
142  ret <8 x iXLen> %a
143}
144declare <8 x iXLen> @llvm.lrint.v8iXLen.v8f16(<8 x half>)
145
146define <16 x iXLen> @lrint_v16f16(<16 x half> %x) {
147; CHECK-i32-LABEL: lrint_v16f16:
148; CHECK-i32:       // %bb.0:
149; CHECK-i32-NEXT:    frintx v1.8h, v1.8h
150; CHECK-i32-NEXT:    frintx v0.8h, v0.8h
151; CHECK-i32-NEXT:    mov h3, v1.h[4]
152; CHECK-i32-NEXT:    mov h2, v1.h[5]
153; CHECK-i32-NEXT:    mov h5, v0.h[4]
154; CHECK-i32-NEXT:    mov h4, v1.h[1]
155; CHECK-i32-NEXT:    mov h6, v0.h[1]
156; CHECK-i32-NEXT:    fcvtzs w11, h0
157; CHECK-i32-NEXT:    fcvtzs w14, h1
158; CHECK-i32-NEXT:    mov h7, v1.h[6]
159; CHECK-i32-NEXT:    mov h16, v1.h[3]
160; CHECK-i32-NEXT:    mov h17, v0.h[7]
161; CHECK-i32-NEXT:    mov h18, v0.h[3]
162; CHECK-i32-NEXT:    fcvtzs w9, h3
163; CHECK-i32-NEXT:    mov h3, v0.h[5]
164; CHECK-i32-NEXT:    fcvtzs w8, h2
165; CHECK-i32-NEXT:    mov h2, v1.h[2]
166; CHECK-i32-NEXT:    fcvtzs w12, h5
167; CHECK-i32-NEXT:    fcvtzs w10, h4
168; CHECK-i32-NEXT:    mov h4, v0.h[6]
169; CHECK-i32-NEXT:    mov h5, v0.h[2]
170; CHECK-i32-NEXT:    fcvtzs w13, h6
171; CHECK-i32-NEXT:    mov h6, v1.h[7]
172; CHECK-i32-NEXT:    fmov s0, w11
173; CHECK-i32-NEXT:    fcvtzs w16, h7
174; CHECK-i32-NEXT:    fcvtzs w15, h3
175; CHECK-i32-NEXT:    fmov s3, w9
176; CHECK-i32-NEXT:    fcvtzs w9, h16
177; CHECK-i32-NEXT:    fcvtzs w17, h2
178; CHECK-i32-NEXT:    fmov s1, w12
179; CHECK-i32-NEXT:    fmov s2, w14
180; CHECK-i32-NEXT:    fcvtzs w11, h4
181; CHECK-i32-NEXT:    fcvtzs w18, h5
182; CHECK-i32-NEXT:    mov v0.s[1], w13
183; CHECK-i32-NEXT:    mov v3.s[1], w8
184; CHECK-i32-NEXT:    fcvtzs w8, h6
185; CHECK-i32-NEXT:    fcvtzs w12, h18
186; CHECK-i32-NEXT:    mov v1.s[1], w15
187; CHECK-i32-NEXT:    mov v2.s[1], w10
188; CHECK-i32-NEXT:    fcvtzs w10, h17
189; CHECK-i32-NEXT:    mov v0.s[2], w18
190; CHECK-i32-NEXT:    mov v3.s[2], w16
191; CHECK-i32-NEXT:    mov v1.s[2], w11
192; CHECK-i32-NEXT:    mov v2.s[2], w17
193; CHECK-i32-NEXT:    mov v0.s[3], w12
194; CHECK-i32-NEXT:    mov v3.s[3], w8
195; CHECK-i32-NEXT:    mov v1.s[3], w10
196; CHECK-i32-NEXT:    mov v2.s[3], w9
197; CHECK-i32-NEXT:    ret
198;
199; CHECK-i64-LABEL: lrint_v16f16:
200; CHECK-i64:       // %bb.0:
201; CHECK-i64-NEXT:    ext v2.16b, v1.16b, v1.16b, #8
202; CHECK-i64-NEXT:    frintx v1.4h, v1.4h
203; CHECK-i64-NEXT:    frintx v3.4h, v0.4h
204; CHECK-i64-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
205; CHECK-i64-NEXT:    frintx v2.4h, v2.4h
206; CHECK-i64-NEXT:    mov h4, v1.h[2]
207; CHECK-i64-NEXT:    mov h5, v3.h[2]
208; CHECK-i64-NEXT:    frintx v0.4h, v0.4h
209; CHECK-i64-NEXT:    mov h6, v3.h[1]
210; CHECK-i64-NEXT:    fcvtzs x9, h3
211; CHECK-i64-NEXT:    mov h16, v1.h[1]
212; CHECK-i64-NEXT:    fcvtzs x12, h1
213; CHECK-i64-NEXT:    mov h3, v3.h[3]
214; CHECK-i64-NEXT:    mov h17, v1.h[3]
215; CHECK-i64-NEXT:    mov h7, v2.h[3]
216; CHECK-i64-NEXT:    fcvtzs x8, h4
217; CHECK-i64-NEXT:    fcvtzs x10, h5
218; CHECK-i64-NEXT:    mov h4, v2.h[2]
219; CHECK-i64-NEXT:    mov h5, v0.h[2]
220; CHECK-i64-NEXT:    fcvtzs x11, h6
221; CHECK-i64-NEXT:    mov h6, v0.h[3]
222; CHECK-i64-NEXT:    fcvtzs x15, h2
223; CHECK-i64-NEXT:    mov h2, v2.h[1]
224; CHECK-i64-NEXT:    fcvtzs x14, h0
225; CHECK-i64-NEXT:    fcvtzs x17, h3
226; CHECK-i64-NEXT:    fcvtzs x0, h17
227; CHECK-i64-NEXT:    fcvtzs x13, h7
228; CHECK-i64-NEXT:    mov h7, v0.h[1]
229; CHECK-i64-NEXT:    fmov d0, x9
230; CHECK-i64-NEXT:    fcvtzs x16, h4
231; CHECK-i64-NEXT:    fcvtzs x9, h5
232; CHECK-i64-NEXT:    fmov d4, x12
233; CHECK-i64-NEXT:    fcvtzs x12, h16
234; CHECK-i64-NEXT:    fmov d1, x10
235; CHECK-i64-NEXT:    fcvtzs x10, h6
236; CHECK-i64-NEXT:    fmov d5, x8
237; CHECK-i64-NEXT:    fcvtzs x8, h2
238; CHECK-i64-NEXT:    fmov d2, x14
239; CHECK-i64-NEXT:    fcvtzs x18, h7
240; CHECK-i64-NEXT:    fmov d6, x15
241; CHECK-i64-NEXT:    mov v0.d[1], x11
242; CHECK-i64-NEXT:    fmov d3, x9
243; CHECK-i64-NEXT:    fmov d7, x16
244; CHECK-i64-NEXT:    mov v1.d[1], x17
245; CHECK-i64-NEXT:    mov v4.d[1], x12
246; CHECK-i64-NEXT:    mov v5.d[1], x0
247; CHECK-i64-NEXT:    mov v6.d[1], x8
248; CHECK-i64-NEXT:    mov v2.d[1], x18
249; CHECK-i64-NEXT:    mov v3.d[1], x10
250; CHECK-i64-NEXT:    mov v7.d[1], x13
251; CHECK-i64-NEXT:    ret
252  %a = call <16 x iXLen> @llvm.lrint.v16iXLen.v16f16(<16 x half> %x)
253  ret <16 x iXLen> %a
254}
255declare <16 x iXLen> @llvm.lrint.v16iXLen.v16f16(<16 x half>)
256
257define <32 x iXLen> @lrint_v32f16(<32 x half> %x) {
258; CHECK-i32-LABEL: lrint_v32f16:
259; CHECK-i32:       // %bb.0:
260; CHECK-i32-NEXT:    stp x26, x25, [sp, #-64]! // 16-byte Folded Spill
261; CHECK-i32-NEXT:    stp x24, x23, [sp, #16] // 16-byte Folded Spill
262; CHECK-i32-NEXT:    stp x22, x21, [sp, #32] // 16-byte Folded Spill
263; CHECK-i32-NEXT:    stp x20, x19, [sp, #48] // 16-byte Folded Spill
264; CHECK-i32-NEXT:    .cfi_def_cfa_offset 64
265; CHECK-i32-NEXT:    .cfi_offset w19, -8
266; CHECK-i32-NEXT:    .cfi_offset w20, -16
267; CHECK-i32-NEXT:    .cfi_offset w21, -24
268; CHECK-i32-NEXT:    .cfi_offset w22, -32
269; CHECK-i32-NEXT:    .cfi_offset w23, -40
270; CHECK-i32-NEXT:    .cfi_offset w24, -48
271; CHECK-i32-NEXT:    .cfi_offset w25, -56
272; CHECK-i32-NEXT:    .cfi_offset w26, -64
273; CHECK-i32-NEXT:    frintx v3.8h, v3.8h
274; CHECK-i32-NEXT:    frintx v2.8h, v2.8h
275; CHECK-i32-NEXT:    frintx v1.8h, v1.8h
276; CHECK-i32-NEXT:    frintx v0.8h, v0.8h
277; CHECK-i32-NEXT:    mov h4, v3.h[7]
278; CHECK-i32-NEXT:    mov h5, v3.h[6]
279; CHECK-i32-NEXT:    mov h6, v3.h[5]
280; CHECK-i32-NEXT:    mov h7, v3.h[4]
281; CHECK-i32-NEXT:    mov h16, v3.h[3]
282; CHECK-i32-NEXT:    mov h17, v3.h[2]
283; CHECK-i32-NEXT:    mov h18, v3.h[1]
284; CHECK-i32-NEXT:    mov h19, v2.h[7]
285; CHECK-i32-NEXT:    fcvtzs w1, h3
286; CHECK-i32-NEXT:    mov h3, v1.h[6]
287; CHECK-i32-NEXT:    fcvtzs w7, h2
288; CHECK-i32-NEXT:    fcvtzs w22, h0
289; CHECK-i32-NEXT:    fcvtzs w8, h4
290; CHECK-i32-NEXT:    mov h4, v2.h[6]
291; CHECK-i32-NEXT:    fcvtzs w10, h5
292; CHECK-i32-NEXT:    mov h5, v2.h[5]
293; CHECK-i32-NEXT:    fcvtzs w12, h6
294; CHECK-i32-NEXT:    mov h6, v2.h[4]
295; CHECK-i32-NEXT:    fcvtzs w13, h7
296; CHECK-i32-NEXT:    mov h7, v2.h[3]
297; CHECK-i32-NEXT:    fcvtzs w9, h16
298; CHECK-i32-NEXT:    fcvtzs w11, h17
299; CHECK-i32-NEXT:    mov h16, v2.h[2]
300; CHECK-i32-NEXT:    mov h17, v2.h[1]
301; CHECK-i32-NEXT:    fcvtzs w17, h4
302; CHECK-i32-NEXT:    mov h4, v1.h[5]
303; CHECK-i32-NEXT:    mov h2, v0.h[5]
304; CHECK-i32-NEXT:    fcvtzs w0, h5
305; CHECK-i32-NEXT:    fcvtzs w3, h6
306; CHECK-i32-NEXT:    mov h5, v1.h[4]
307; CHECK-i32-NEXT:    mov h6, v0.h[4]
308; CHECK-i32-NEXT:    fcvtzs w16, h7
309; CHECK-i32-NEXT:    mov h7, v0.h[1]
310; CHECK-i32-NEXT:    fcvtzs w15, h18
311; CHECK-i32-NEXT:    fcvtzs w2, h3
312; CHECK-i32-NEXT:    mov h3, v1.h[2]
313; CHECK-i32-NEXT:    fcvtzs w19, h4
314; CHECK-i32-NEXT:    mov h4, v1.h[1]
315; CHECK-i32-NEXT:    mov h18, v0.h[6]
316; CHECK-i32-NEXT:    fcvtzs w20, h5
317; CHECK-i32-NEXT:    fcvtzs w23, h2
318; CHECK-i32-NEXT:    mov h2, v0.h[2]
319; CHECK-i32-NEXT:    fcvtzs w21, h6
320; CHECK-i32-NEXT:    fcvtzs w25, h1
321; CHECK-i32-NEXT:    fcvtzs w4, h17
322; CHECK-i32-NEXT:    fcvtzs w24, h7
323; CHECK-i32-NEXT:    fcvtzs w14, h19
324; CHECK-i32-NEXT:    fcvtzs w18, h16
325; CHECK-i32-NEXT:    fcvtzs w26, h4
326; CHECK-i32-NEXT:    mov h16, v1.h[7]
327; CHECK-i32-NEXT:    mov h17, v1.h[3]
328; CHECK-i32-NEXT:    fcvtzs w5, h3
329; CHECK-i32-NEXT:    mov h19, v0.h[7]
330; CHECK-i32-NEXT:    fcvtzs w6, h18
331; CHECK-i32-NEXT:    mov h18, v0.h[3]
332; CHECK-i32-NEXT:    fmov s0, w22
333; CHECK-i32-NEXT:    fmov s1, w21
334; CHECK-i32-NEXT:    fcvtzs w21, h2
335; CHECK-i32-NEXT:    fmov s2, w25
336; CHECK-i32-NEXT:    fmov s3, w20
337; CHECK-i32-NEXT:    fmov s4, w7
338; CHECK-i32-NEXT:    fmov s5, w3
339; CHECK-i32-NEXT:    fmov s6, w1
340; CHECK-i32-NEXT:    fmov s7, w13
341; CHECK-i32-NEXT:    mov v0.s[1], w24
342; CHECK-i32-NEXT:    mov v1.s[1], w23
343; CHECK-i32-NEXT:    ldp x24, x23, [sp, #16] // 16-byte Folded Reload
344; CHECK-i32-NEXT:    mov v2.s[1], w26
345; CHECK-i32-NEXT:    mov v3.s[1], w19
346; CHECK-i32-NEXT:    ldp x20, x19, [sp, #48] // 16-byte Folded Reload
347; CHECK-i32-NEXT:    mov v4.s[1], w4
348; CHECK-i32-NEXT:    mov v5.s[1], w0
349; CHECK-i32-NEXT:    mov v6.s[1], w15
350; CHECK-i32-NEXT:    mov v7.s[1], w12
351; CHECK-i32-NEXT:    fcvtzs w12, h16
352; CHECK-i32-NEXT:    fcvtzs w13, h17
353; CHECK-i32-NEXT:    fcvtzs w15, h19
354; CHECK-i32-NEXT:    fcvtzs w0, h18
355; CHECK-i32-NEXT:    mov v0.s[2], w21
356; CHECK-i32-NEXT:    ldp x22, x21, [sp, #32] // 16-byte Folded Reload
357; CHECK-i32-NEXT:    mov v1.s[2], w6
358; CHECK-i32-NEXT:    mov v2.s[2], w5
359; CHECK-i32-NEXT:    mov v3.s[2], w2
360; CHECK-i32-NEXT:    mov v4.s[2], w18
361; CHECK-i32-NEXT:    mov v5.s[2], w17
362; CHECK-i32-NEXT:    mov v6.s[2], w11
363; CHECK-i32-NEXT:    mov v7.s[2], w10
364; CHECK-i32-NEXT:    mov v0.s[3], w0
365; CHECK-i32-NEXT:    mov v1.s[3], w15
366; CHECK-i32-NEXT:    mov v2.s[3], w13
367; CHECK-i32-NEXT:    mov v3.s[3], w12
368; CHECK-i32-NEXT:    mov v4.s[3], w16
369; CHECK-i32-NEXT:    mov v5.s[3], w14
370; CHECK-i32-NEXT:    mov v6.s[3], w9
371; CHECK-i32-NEXT:    mov v7.s[3], w8
372; CHECK-i32-NEXT:    ldp x26, x25, [sp], #64 // 16-byte Folded Reload
373; CHECK-i32-NEXT:    ret
374;
375; CHECK-i64-LABEL: lrint_v32f16:
376; CHECK-i64:       // %bb.0:
377; CHECK-i64-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
378; CHECK-i64-NEXT:    sub x9, sp, #272
379; CHECK-i64-NEXT:    mov x29, sp
380; CHECK-i64-NEXT:    and sp, x9, #0xffffffffffffffe0
381; CHECK-i64-NEXT:    .cfi_def_cfa w29, 16
382; CHECK-i64-NEXT:    .cfi_offset w30, -8
383; CHECK-i64-NEXT:    .cfi_offset w29, -16
384; CHECK-i64-NEXT:    frintx v5.4h, v0.4h
385; CHECK-i64-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
386; CHECK-i64-NEXT:    ext v4.16b, v1.16b, v1.16b, #8
387; CHECK-i64-NEXT:    ext v17.16b, v2.16b, v2.16b, #8
388; CHECK-i64-NEXT:    frintx v1.4h, v1.4h
389; CHECK-i64-NEXT:    frintx v2.4h, v2.4h
390; CHECK-i64-NEXT:    ptrue p0.d, vl4
391; CHECK-i64-NEXT:    mov h6, v5.h[3]
392; CHECK-i64-NEXT:    frintx v0.4h, v0.4h
393; CHECK-i64-NEXT:    mov h7, v5.h[2]
394; CHECK-i64-NEXT:    mov h16, v5.h[1]
395; CHECK-i64-NEXT:    frintx v4.4h, v4.4h
396; CHECK-i64-NEXT:    fcvtzs x12, h5
397; CHECK-i64-NEXT:    ext v5.16b, v3.16b, v3.16b, #8
398; CHECK-i64-NEXT:    frintx v17.4h, v17.4h
399; CHECK-i64-NEXT:    frintx v3.4h, v3.4h
400; CHECK-i64-NEXT:    fcvtzs x9, h6
401; CHECK-i64-NEXT:    mov h6, v0.h[3]
402; CHECK-i64-NEXT:    fcvtzs x10, h7
403; CHECK-i64-NEXT:    mov h7, v0.h[2]
404; CHECK-i64-NEXT:    fcvtzs x11, h16
405; CHECK-i64-NEXT:    mov h16, v0.h[1]
406; CHECK-i64-NEXT:    fcvtzs x13, h6
407; CHECK-i64-NEXT:    mov h6, v4.h[3]
408; CHECK-i64-NEXT:    stp x10, x9, [sp, #48]
409; CHECK-i64-NEXT:    fcvtzs x9, h7
410; CHECK-i64-NEXT:    mov h7, v4.h[2]
411; CHECK-i64-NEXT:    fcvtzs x10, h16
412; CHECK-i64-NEXT:    mov h16, v4.h[1]
413; CHECK-i64-NEXT:    stp x12, x11, [sp, #32]
414; CHECK-i64-NEXT:    fcvtzs x11, h0
415; CHECK-i64-NEXT:    frintx v0.4h, v5.4h
416; CHECK-i64-NEXT:    mov h5, v17.h[3]
417; CHECK-i64-NEXT:    fcvtzs x12, h6
418; CHECK-i64-NEXT:    mov h6, v17.h[2]
419; CHECK-i64-NEXT:    stp x9, x13, [sp, #16]
420; CHECK-i64-NEXT:    fcvtzs x13, h7
421; CHECK-i64-NEXT:    mov h7, v17.h[1]
422; CHECK-i64-NEXT:    fcvtzs x9, h16
423; CHECK-i64-NEXT:    stp x11, x10, [sp]
424; CHECK-i64-NEXT:    fcvtzs x10, h4
425; CHECK-i64-NEXT:    fcvtzs x11, h5
426; CHECK-i64-NEXT:    mov h4, v0.h[3]
427; CHECK-i64-NEXT:    mov h5, v0.h[2]
428; CHECK-i64-NEXT:    stp x13, x12, [sp, #80]
429; CHECK-i64-NEXT:    fcvtzs x12, h6
430; CHECK-i64-NEXT:    fcvtzs x13, h7
431; CHECK-i64-NEXT:    mov h6, v0.h[1]
432; CHECK-i64-NEXT:    stp x10, x9, [sp, #64]
433; CHECK-i64-NEXT:    fcvtzs x9, h17
434; CHECK-i64-NEXT:    mov h7, v1.h[3]
435; CHECK-i64-NEXT:    fcvtzs x10, h4
436; CHECK-i64-NEXT:    mov h4, v1.h[2]
437; CHECK-i64-NEXT:    stp x12, x11, [sp, #144]
438; CHECK-i64-NEXT:    fcvtzs x11, h5
439; CHECK-i64-NEXT:    mov h5, v1.h[1]
440; CHECK-i64-NEXT:    fcvtzs x12, h6
441; CHECK-i64-NEXT:    stp x9, x13, [sp, #128]
442; CHECK-i64-NEXT:    fcvtzs x9, h0
443; CHECK-i64-NEXT:    fcvtzs x13, h7
444; CHECK-i64-NEXT:    mov h0, v2.h[3]
445; CHECK-i64-NEXT:    stp x11, x10, [sp, #208]
446; CHECK-i64-NEXT:    fcvtzs x10, h4
447; CHECK-i64-NEXT:    mov h4, v2.h[2]
448; CHECK-i64-NEXT:    fcvtzs x11, h5
449; CHECK-i64-NEXT:    mov h5, v2.h[1]
450; CHECK-i64-NEXT:    stp x9, x12, [sp, #192]
451; CHECK-i64-NEXT:    fcvtzs x9, h1
452; CHECK-i64-NEXT:    fcvtzs x12, h0
453; CHECK-i64-NEXT:    mov h0, v3.h[3]
454; CHECK-i64-NEXT:    mov h1, v3.h[2]
455; CHECK-i64-NEXT:    stp x10, x13, [sp, #112]
456; CHECK-i64-NEXT:    fcvtzs x10, h4
457; CHECK-i64-NEXT:    mov h4, v3.h[1]
458; CHECK-i64-NEXT:    fcvtzs x13, h5
459; CHECK-i64-NEXT:    stp x9, x11, [sp, #96]
460; CHECK-i64-NEXT:    fcvtzs x9, h2
461; CHECK-i64-NEXT:    fcvtzs x11, h0
462; CHECK-i64-NEXT:    stp x10, x12, [sp, #176]
463; CHECK-i64-NEXT:    fcvtzs x10, h1
464; CHECK-i64-NEXT:    fcvtzs x12, h4
465; CHECK-i64-NEXT:    stp x9, x13, [sp, #160]
466; CHECK-i64-NEXT:    fcvtzs x9, h3
467; CHECK-i64-NEXT:    stp x10, x11, [sp, #240]
468; CHECK-i64-NEXT:    add x10, sp, #64
469; CHECK-i64-NEXT:    stp x9, x12, [sp, #224]
470; CHECK-i64-NEXT:    add x9, sp, #32
471; CHECK-i64-NEXT:    ld1d { z0.d }, p0/z, [x9]
472; CHECK-i64-NEXT:    mov x9, sp
473; CHECK-i64-NEXT:    ld1d { z2.d }, p0/z, [x10]
474; CHECK-i64-NEXT:    ld1d { z1.d }, p0/z, [x9]
475; CHECK-i64-NEXT:    add x9, sp, #224
476; CHECK-i64-NEXT:    add x10, sp, #128
477; CHECK-i64-NEXT:    ld1d { z3.d }, p0/z, [x9]
478; CHECK-i64-NEXT:    add x9, sp, #160
479; CHECK-i64-NEXT:    ld1d { z4.d }, p0/z, [x10]
480; CHECK-i64-NEXT:    add x10, sp, #96
481; CHECK-i64-NEXT:    ld1d { z5.d }, p0/z, [x9]
482; CHECK-i64-NEXT:    add x9, sp, #192
483; CHECK-i64-NEXT:    ld1d { z6.d }, p0/z, [x10]
484; CHECK-i64-NEXT:    mov x10, #24 // =0x18
485; CHECK-i64-NEXT:    ld1d { z7.d }, p0/z, [x9]
486; CHECK-i64-NEXT:    mov x9, #16 // =0x10
487; CHECK-i64-NEXT:    st1d { z3.d }, p0, [x8, x10, lsl #3]
488; CHECK-i64-NEXT:    st1d { z5.d }, p0, [x8, x9, lsl #3]
489; CHECK-i64-NEXT:    mov x9, #8 // =0x8
490; CHECK-i64-NEXT:    st1d { z6.d }, p0, [x8, x9, lsl #3]
491; CHECK-i64-NEXT:    mov x9, #28 // =0x1c
492; CHECK-i64-NEXT:    st1d { z7.d }, p0, [x8, x9, lsl #3]
493; CHECK-i64-NEXT:    mov x9, #20 // =0x14
494; CHECK-i64-NEXT:    st1d { z4.d }, p0, [x8, x9, lsl #3]
495; CHECK-i64-NEXT:    mov x9, #12 // =0xc
496; CHECK-i64-NEXT:    st1d { z2.d }, p0, [x8, x9, lsl #3]
497; CHECK-i64-NEXT:    mov x9, #4 // =0x4
498; CHECK-i64-NEXT:    st1d { z1.d }, p0, [x8, x9, lsl #3]
499; CHECK-i64-NEXT:    st1d { z0.d }, p0, [x8]
500; CHECK-i64-NEXT:    mov sp, x29
501; CHECK-i64-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload
502; CHECK-i64-NEXT:    ret
503  %a = call <32 x iXLen> @llvm.lrint.v32iXLen.v32f16(<32 x half> %x)
504  ret <32 x iXLen> %a
505}
506declare <32 x iXLen> @llvm.lrint.v32iXLen.v32f16(<32 x half>)
507
508define <1 x iXLen> @lrint_v1f32(<1 x float> %x) {
509; CHECK-i32-LABEL: lrint_v1f32:
510; CHECK-i32:       // %bb.0:
511; CHECK-i32-NEXT:    frintx v0.2s, v0.2s
512; CHECK-i32-NEXT:    fcvtzs v0.2s, v0.2s
513; CHECK-i32-NEXT:    ret
514;
515; CHECK-i64-LABEL: lrint_v1f32:
516; CHECK-i64:       // %bb.0:
517; CHECK-i64-NEXT:    // kill: def $d0 killed $d0 def $q0
518; CHECK-i64-NEXT:    frintx s0, s0
519; CHECK-i64-NEXT:    fcvtzs x8, s0
520; CHECK-i64-NEXT:    fmov d0, x8
521; CHECK-i64-NEXT:    ret
522  %a = call <1 x iXLen> @llvm.lrint.v1iXLen.v1f32(<1 x float> %x)
523  ret <1 x iXLen> %a
524}
525declare <1 x iXLen> @llvm.lrint.v1iXLen.v1f32(<1 x float>)
526
527define <2 x iXLen> @lrint_v2f32(<2 x float> %x) {
528; CHECK-i32-LABEL: lrint_v2f32:
529; CHECK-i32:       // %bb.0:
530; CHECK-i32-NEXT:    frintx v0.2s, v0.2s
531; CHECK-i32-NEXT:    fcvtzs v0.2s, v0.2s
532; CHECK-i32-NEXT:    ret
533;
534; CHECK-i64-LABEL: lrint_v2f32:
535; CHECK-i64:       // %bb.0:
536; CHECK-i64-NEXT:    frintx v0.2s, v0.2s
537; CHECK-i64-NEXT:    fcvtl v0.2d, v0.2s
538; CHECK-i64-NEXT:    fcvtzs v0.2d, v0.2d
539; CHECK-i64-NEXT:    ret
540  %a = call <2 x iXLen> @llvm.lrint.v2iXLen.v2f32(<2 x float> %x)
541  ret <2 x iXLen> %a
542}
543declare <2 x iXLen> @llvm.lrint.v2iXLen.v2f32(<2 x float>)
544
545define <4 x iXLen> @lrint_v4f32(<4 x float> %x) {
546; CHECK-i32-LABEL: lrint_v4f32:
547; CHECK-i32:       // %bb.0:
548; CHECK-i32-NEXT:    frintx v0.4s, v0.4s
549; CHECK-i32-NEXT:    fcvtzs v0.4s, v0.4s
550; CHECK-i32-NEXT:    ret
551;
552; CHECK-i64-LABEL: lrint_v4f32:
553; CHECK-i64:       // %bb.0:
554; CHECK-i64-NEXT:    frintx v0.4s, v0.4s
555; CHECK-i64-NEXT:    mov s1, v0.s[2]
556; CHECK-i64-NEXT:    mov s2, v0.s[3]
557; CHECK-i64-NEXT:    mov s3, v0.s[1]
558; CHECK-i64-NEXT:    fcvtzs x9, s0
559; CHECK-i64-NEXT:    fcvtzs x8, s1
560; CHECK-i64-NEXT:    fcvtzs x10, s2
561; CHECK-i64-NEXT:    fcvtzs x11, s3
562; CHECK-i64-NEXT:    fmov d0, x9
563; CHECK-i64-NEXT:    fmov d1, x8
564; CHECK-i64-NEXT:    mov v0.d[1], x11
565; CHECK-i64-NEXT:    mov v1.d[1], x10
566; CHECK-i64-NEXT:    ret
567  %a = call <4 x iXLen> @llvm.lrint.v4iXLen.v4f32(<4 x float> %x)
568  ret <4 x iXLen> %a
569}
570declare <4 x iXLen> @llvm.lrint.v4iXLen.v4f32(<4 x float>)
571
572define <8 x iXLen> @lrint_v8f32(<8 x float> %x) {
573; CHECK-i32-LABEL: lrint_v8f32:
574; CHECK-i32:       // %bb.0:
575; CHECK-i32-NEXT:    ptrue p0.d, vl2
576; CHECK-i32-NEXT:    // kill: def $q0 killed $q0 def $z0
577; CHECK-i32-NEXT:    // kill: def $q1 killed $q1 def $z1
578; CHECK-i32-NEXT:    splice z0.d, p0, z0.d, z1.d
579; CHECK-i32-NEXT:    ptrue p0.s, vl8
580; CHECK-i32-NEXT:    movprfx z2, z0
581; CHECK-i32-NEXT:    frintx z2.s, p0/m, z0.s
582; CHECK-i32-NEXT:    mov z0.s, z2.s[4]
583; CHECK-i32-NEXT:    mov z1.s, z2.s[5]
584; CHECK-i32-NEXT:    mov z3.s, z2.s[1]
585; CHECK-i32-NEXT:    fcvtzs w9, s2
586; CHECK-i32-NEXT:    fcvtzs w8, s0
587; CHECK-i32-NEXT:    mov z0.s, z2.s[6]
588; CHECK-i32-NEXT:    fcvtzs w10, s1
589; CHECK-i32-NEXT:    mov z1.s, z2.s[2]
590; CHECK-i32-NEXT:    fcvtzs w11, s3
591; CHECK-i32-NEXT:    mov z3.s, z2.s[7]
592; CHECK-i32-NEXT:    mov z2.s, z2.s[3]
593; CHECK-i32-NEXT:    fcvtzs w12, s0
594; CHECK-i32-NEXT:    fmov s0, w9
595; CHECK-i32-NEXT:    fcvtzs w13, s1
596; CHECK-i32-NEXT:    fmov s1, w8
597; CHECK-i32-NEXT:    fcvtzs w8, s3
598; CHECK-i32-NEXT:    fcvtzs w9, s2
599; CHECK-i32-NEXT:    mov v0.s[1], w11
600; CHECK-i32-NEXT:    mov v1.s[1], w10
601; CHECK-i32-NEXT:    mov v0.s[2], w13
602; CHECK-i32-NEXT:    mov v1.s[2], w12
603; CHECK-i32-NEXT:    mov v0.s[3], w9
604; CHECK-i32-NEXT:    mov v1.s[3], w8
605; CHECK-i32-NEXT:    ret
606;
607; CHECK-i64-LABEL: lrint_v8f32:
608; CHECK-i64:       // %bb.0:
609; CHECK-i64-NEXT:    frintx v0.4s, v0.4s
610; CHECK-i64-NEXT:    frintx v1.4s, v1.4s
611; CHECK-i64-NEXT:    mov s3, v1.s[2]
612; CHECK-i64-NEXT:    mov s4, v0.s[2]
613; CHECK-i64-NEXT:    mov s2, v0.s[1]
614; CHECK-i64-NEXT:    mov s5, v1.s[3]
615; CHECK-i64-NEXT:    mov s6, v1.s[1]
616; CHECK-i64-NEXT:    mov s7, v0.s[3]
617; CHECK-i64-NEXT:    fcvtzs x8, s0
618; CHECK-i64-NEXT:    fcvtzs x10, s1
619; CHECK-i64-NEXT:    fcvtzs x11, s3
620; CHECK-i64-NEXT:    fcvtzs x12, s4
621; CHECK-i64-NEXT:    fcvtzs x9, s2
622; CHECK-i64-NEXT:    fcvtzs x13, s5
623; CHECK-i64-NEXT:    fcvtzs x14, s6
624; CHECK-i64-NEXT:    fcvtzs x15, s7
625; CHECK-i64-NEXT:    fmov d0, x8
626; CHECK-i64-NEXT:    fmov d2, x10
627; CHECK-i64-NEXT:    fmov d1, x12
628; CHECK-i64-NEXT:    fmov d3, x11
629; CHECK-i64-NEXT:    mov v0.d[1], x9
630; CHECK-i64-NEXT:    mov v2.d[1], x14
631; CHECK-i64-NEXT:    mov v1.d[1], x15
632; CHECK-i64-NEXT:    mov v3.d[1], x13
633; CHECK-i64-NEXT:    ret
634  %a = call <8 x iXLen> @llvm.lrint.v8iXLen.v8f32(<8 x float> %x)
635  ret <8 x iXLen> %a
636}
637declare <8 x iXLen> @llvm.lrint.v8iXLen.v8f32(<8 x float>)
638
639define <16 x iXLen> @lrint_v16f32(<16 x float> %x) {
640; CHECK-i32-LABEL: lrint_v16f32:
641; CHECK-i32:       // %bb.0:
642; CHECK-i32-NEXT:    ptrue p0.d, vl2
643; CHECK-i32-NEXT:    // kill: def $q2 killed $q2 def $z2
644; CHECK-i32-NEXT:    // kill: def $q3 killed $q3 def $z3
645; CHECK-i32-NEXT:    // kill: def $q0 killed $q0 def $z0
646; CHECK-i32-NEXT:    // kill: def $q1 killed $q1 def $z1
647; CHECK-i32-NEXT:    splice z2.d, p0, z2.d, z3.d
648; CHECK-i32-NEXT:    splice z0.d, p0, z0.d, z1.d
649; CHECK-i32-NEXT:    ptrue p0.s, vl8
650; CHECK-i32-NEXT:    movprfx z1, z2
651; CHECK-i32-NEXT:    frintx z1.s, p0/m, z2.s
652; CHECK-i32-NEXT:    frintx z0.s, p0/m, z0.s
653; CHECK-i32-NEXT:    mov z2.s, z1.s[5]
654; CHECK-i32-NEXT:    mov z3.s, z1.s[4]
655; CHECK-i32-NEXT:    mov z5.s, z0.s[5]
656; CHECK-i32-NEXT:    mov z7.s, z0.s[1]
657; CHECK-i32-NEXT:    fcvtzs w11, s0
658; CHECK-i32-NEXT:    fcvtzs w13, s1
659; CHECK-i32-NEXT:    mov z4.s, z1.s[7]
660; CHECK-i32-NEXT:    mov z6.s, z1.s[6]
661; CHECK-i32-NEXT:    mov z16.s, z0.s[7]
662; CHECK-i32-NEXT:    fcvtzs w8, s2
663; CHECK-i32-NEXT:    mov z2.s, z0.s[4]
664; CHECK-i32-NEXT:    fcvtzs w9, s3
665; CHECK-i32-NEXT:    mov z3.s, z1.s[1]
666; CHECK-i32-NEXT:    fcvtzs w10, s5
667; CHECK-i32-NEXT:    fcvtzs w12, s7
668; CHECK-i32-NEXT:    mov z5.s, z0.s[6]
669; CHECK-i32-NEXT:    mov z7.s, z1.s[2]
670; CHECK-i32-NEXT:    mov z17.s, z1.s[3]
671; CHECK-i32-NEXT:    fcvtzs w14, s2
672; CHECK-i32-NEXT:    mov z2.s, z0.s[2]
673; CHECK-i32-NEXT:    mov z18.s, z0.s[3]
674; CHECK-i32-NEXT:    fcvtzs w15, s3
675; CHECK-i32-NEXT:    fmov s0, w11
676; CHECK-i32-NEXT:    fmov s3, w9
677; CHECK-i32-NEXT:    fcvtzs w16, s6
678; CHECK-i32-NEXT:    fcvtzs w17, s5
679; CHECK-i32-NEXT:    fcvtzs w11, s7
680; CHECK-i32-NEXT:    fcvtzs w18, s2
681; CHECK-i32-NEXT:    fmov s2, w13
682; CHECK-i32-NEXT:    fcvtzs w9, s16
683; CHECK-i32-NEXT:    fmov s1, w14
684; CHECK-i32-NEXT:    mov v0.s[1], w12
685; CHECK-i32-NEXT:    mov v3.s[1], w8
686; CHECK-i32-NEXT:    fcvtzs w8, s4
687; CHECK-i32-NEXT:    fcvtzs w12, s18
688; CHECK-i32-NEXT:    mov v2.s[1], w15
689; CHECK-i32-NEXT:    mov v1.s[1], w10
690; CHECK-i32-NEXT:    fcvtzs w10, s17
691; CHECK-i32-NEXT:    mov v0.s[2], w18
692; CHECK-i32-NEXT:    mov v3.s[2], w16
693; CHECK-i32-NEXT:    mov v2.s[2], w11
694; CHECK-i32-NEXT:    mov v1.s[2], w17
695; CHECK-i32-NEXT:    mov v0.s[3], w12
696; CHECK-i32-NEXT:    mov v3.s[3], w8
697; CHECK-i32-NEXT:    mov v2.s[3], w10
698; CHECK-i32-NEXT:    mov v1.s[3], w9
699; CHECK-i32-NEXT:    ret
700;
701; CHECK-i64-LABEL: lrint_v16f32:
702; CHECK-i64:       // %bb.0:
703; CHECK-i64-NEXT:    frintx v3.4s, v3.4s
704; CHECK-i64-NEXT:    frintx v2.4s, v2.4s
705; CHECK-i64-NEXT:    frintx v1.4s, v1.4s
706; CHECK-i64-NEXT:    frintx v0.4s, v0.4s
707; CHECK-i64-NEXT:    mov s4, v3.s[2]
708; CHECK-i64-NEXT:    mov s5, v2.s[2]
709; CHECK-i64-NEXT:    mov s6, v1.s[2]
710; CHECK-i64-NEXT:    mov s7, v0.s[2]
711; CHECK-i64-NEXT:    fcvtzs x10, s1
712; CHECK-i64-NEXT:    fcvtzs x11, s0
713; CHECK-i64-NEXT:    mov s16, v0.s[1]
714; CHECK-i64-NEXT:    mov s17, v1.s[1]
715; CHECK-i64-NEXT:    mov s18, v3.s[1]
716; CHECK-i64-NEXT:    fcvtzs x14, s3
717; CHECK-i64-NEXT:    fcvtzs x16, s2
718; CHECK-i64-NEXT:    fcvtzs x8, s4
719; CHECK-i64-NEXT:    mov s4, v2.s[1]
720; CHECK-i64-NEXT:    fcvtzs x9, s5
721; CHECK-i64-NEXT:    mov s5, v1.s[3]
722; CHECK-i64-NEXT:    fcvtzs x12, s6
723; CHECK-i64-NEXT:    mov s6, v0.s[3]
724; CHECK-i64-NEXT:    fcvtzs x13, s7
725; CHECK-i64-NEXT:    mov s7, v3.s[3]
726; CHECK-i64-NEXT:    fmov d0, x11
727; CHECK-i64-NEXT:    fcvtzs x17, s16
728; CHECK-i64-NEXT:    fcvtzs x18, s18
729; CHECK-i64-NEXT:    fcvtzs x15, s4
730; CHECK-i64-NEXT:    mov s4, v2.s[3]
731; CHECK-i64-NEXT:    fmov d2, x10
732; CHECK-i64-NEXT:    fcvtzs x11, s5
733; CHECK-i64-NEXT:    fcvtzs x10, s6
734; CHECK-i64-NEXT:    fmov d3, x12
735; CHECK-i64-NEXT:    fmov d1, x13
736; CHECK-i64-NEXT:    fcvtzs x12, s17
737; CHECK-i64-NEXT:    fcvtzs x13, s7
738; CHECK-i64-NEXT:    fmov d5, x9
739; CHECK-i64-NEXT:    fmov d6, x14
740; CHECK-i64-NEXT:    fmov d7, x8
741; CHECK-i64-NEXT:    fcvtzs x0, s4
742; CHECK-i64-NEXT:    fmov d4, x16
743; CHECK-i64-NEXT:    mov v0.d[1], x17
744; CHECK-i64-NEXT:    mov v1.d[1], x10
745; CHECK-i64-NEXT:    mov v3.d[1], x11
746; CHECK-i64-NEXT:    mov v2.d[1], x12
747; CHECK-i64-NEXT:    mov v6.d[1], x18
748; CHECK-i64-NEXT:    mov v7.d[1], x13
749; CHECK-i64-NEXT:    mov v4.d[1], x15
750; CHECK-i64-NEXT:    mov v5.d[1], x0
751; CHECK-i64-NEXT:    ret
752  %a = call <16 x iXLen> @llvm.lrint.v16iXLen.v16f32(<16 x float> %x)
753  ret <16 x iXLen> %a
754}
755declare <16 x iXLen> @llvm.lrint.v16iXLen.v16f32(<16 x float>)
756
757define <32 x iXLen> @lrint_v32f32(<32 x float> %x) {
758; CHECK-i32-LABEL: lrint_v32f32:
759; CHECK-i32:       // %bb.0:
760; CHECK-i32-NEXT:    str x27, [sp, #-80]! // 8-byte Folded Spill
761; CHECK-i32-NEXT:    stp x26, x25, [sp, #16] // 16-byte Folded Spill
762; CHECK-i32-NEXT:    stp x24, x23, [sp, #32] // 16-byte Folded Spill
763; CHECK-i32-NEXT:    stp x22, x21, [sp, #48] // 16-byte Folded Spill
764; CHECK-i32-NEXT:    stp x20, x19, [sp, #64] // 16-byte Folded Spill
765; CHECK-i32-NEXT:    .cfi_def_cfa_offset 80
766; CHECK-i32-NEXT:    .cfi_offset w19, -8
767; CHECK-i32-NEXT:    .cfi_offset w20, -16
768; CHECK-i32-NEXT:    .cfi_offset w21, -24
769; CHECK-i32-NEXT:    .cfi_offset w22, -32
770; CHECK-i32-NEXT:    .cfi_offset w23, -40
771; CHECK-i32-NEXT:    .cfi_offset w24, -48
772; CHECK-i32-NEXT:    .cfi_offset w25, -56
773; CHECK-i32-NEXT:    .cfi_offset w26, -64
774; CHECK-i32-NEXT:    .cfi_offset w27, -80
775; CHECK-i32-NEXT:    ptrue p1.d, vl2
776; CHECK-i32-NEXT:    // kill: def $q6 killed $q6 def $z6
777; CHECK-i32-NEXT:    // kill: def $q7 killed $q7 def $z7
778; CHECK-i32-NEXT:    // kill: def $q2 killed $q2 def $z2
779; CHECK-i32-NEXT:    // kill: def $q4 killed $q4 def $z4
780; CHECK-i32-NEXT:    // kill: def $q3 killed $q3 def $z3
781; CHECK-i32-NEXT:    // kill: def $q5 killed $q5 def $z5
782; CHECK-i32-NEXT:    // kill: def $q1 killed $q1 def $z1
783; CHECK-i32-NEXT:    // kill: def $q0 killed $q0 def $z0
784; CHECK-i32-NEXT:    ptrue p0.s, vl8
785; CHECK-i32-NEXT:    splice z6.d, p1, z6.d, z7.d
786; CHECK-i32-NEXT:    splice z2.d, p1, z2.d, z3.d
787; CHECK-i32-NEXT:    splice z4.d, p1, z4.d, z5.d
788; CHECK-i32-NEXT:    splice z0.d, p1, z0.d, z1.d
789; CHECK-i32-NEXT:    movprfx z3, z6
790; CHECK-i32-NEXT:    frintx z3.s, p0/m, z6.s
791; CHECK-i32-NEXT:    frintx z2.s, p0/m, z2.s
792; CHECK-i32-NEXT:    movprfx z1, z4
793; CHECK-i32-NEXT:    frintx z1.s, p0/m, z4.s
794; CHECK-i32-NEXT:    frintx z0.s, p0/m, z0.s
795; CHECK-i32-NEXT:    mov z4.s, z3.s[7]
796; CHECK-i32-NEXT:    mov z5.s, z3.s[6]
797; CHECK-i32-NEXT:    mov z6.s, z3.s[5]
798; CHECK-i32-NEXT:    mov z16.s, z1.s[7]
799; CHECK-i32-NEXT:    mov z7.s, z3.s[4]
800; CHECK-i32-NEXT:    mov z17.s, z1.s[6]
801; CHECK-i32-NEXT:    mov z18.s, z1.s[5]
802; CHECK-i32-NEXT:    mov z19.s, z1.s[4]
803; CHECK-i32-NEXT:    fcvtzs w7, s3
804; CHECK-i32-NEXT:    fcvtzs w8, s4
805; CHECK-i32-NEXT:    mov z4.s, z2.s[7]
806; CHECK-i32-NEXT:    fcvtzs w10, s5
807; CHECK-i32-NEXT:    mov z5.s, z2.s[6]
808; CHECK-i32-NEXT:    fcvtzs w13, s6
809; CHECK-i32-NEXT:    fcvtzs w9, s16
810; CHECK-i32-NEXT:    mov z6.s, z2.s[4]
811; CHECK-i32-NEXT:    mov z16.s, z0.s[6]
812; CHECK-i32-NEXT:    fcvtzs w14, s7
813; CHECK-i32-NEXT:    fcvtzs w11, s4
814; CHECK-i32-NEXT:    mov z4.s, z2.s[5]
815; CHECK-i32-NEXT:    mov z7.s, z0.s[7]
816; CHECK-i32-NEXT:    fcvtzs w16, s5
817; CHECK-i32-NEXT:    mov z5.s, z0.s[4]
818; CHECK-i32-NEXT:    fcvtzs w12, s17
819; CHECK-i32-NEXT:    fcvtzs w15, s18
820; CHECK-i32-NEXT:    fcvtzs w17, s19
821; CHECK-i32-NEXT:    mov z17.s, z0.s[5]
822; CHECK-i32-NEXT:    fcvtzs w3, s4
823; CHECK-i32-NEXT:    mov z4.s, z3.s[1]
824; CHECK-i32-NEXT:    mov z18.s, z3.s[2]
825; CHECK-i32-NEXT:    fcvtzs w4, s6
826; CHECK-i32-NEXT:    fcvtzs w0, s16
827; CHECK-i32-NEXT:    fcvtzs w6, s5
828; CHECK-i32-NEXT:    mov z16.s, z3.s[3]
829; CHECK-i32-NEXT:    mov z3.s, z0.s[1]
830; CHECK-i32-NEXT:    mov z5.s, z1.s[1]
831; CHECK-i32-NEXT:    mov z6.s, z2.s[1]
832; CHECK-i32-NEXT:    fcvtzs w21, s1
833; CHECK-i32-NEXT:    fcvtzs w22, s0
834; CHECK-i32-NEXT:    fcvtzs w23, s2
835; CHECK-i32-NEXT:    fcvtzs w18, s7
836; CHECK-i32-NEXT:    fcvtzs w2, s4
837; CHECK-i32-NEXT:    mov z4.s, z1.s[2]
838; CHECK-i32-NEXT:    mov z7.s, z2.s[2]
839; CHECK-i32-NEXT:    fcvtzs w5, s17
840; CHECK-i32-NEXT:    fcvtzs w24, s3
841; CHECK-i32-NEXT:    fcvtzs w25, s5
842; CHECK-i32-NEXT:    fcvtzs w26, s6
843; CHECK-i32-NEXT:    fcvtzs w1, s18
844; CHECK-i32-NEXT:    mov z18.s, z0.s[2]
845; CHECK-i32-NEXT:    mov z17.s, z1.s[3]
846; CHECK-i32-NEXT:    fcvtzs w19, s4
847; CHECK-i32-NEXT:    mov z19.s, z2.s[3]
848; CHECK-i32-NEXT:    fcvtzs w20, s7
849; CHECK-i32-NEXT:    mov z20.s, z0.s[3]
850; CHECK-i32-NEXT:    fmov s0, w22
851; CHECK-i32-NEXT:    fmov s2, w23
852; CHECK-i32-NEXT:    fmov s4, w21
853; CHECK-i32-NEXT:    ldp x22, x21, [sp, #48] // 16-byte Folded Reload
854; CHECK-i32-NEXT:    fmov s1, w6
855; CHECK-i32-NEXT:    fmov s6, w7
856; CHECK-i32-NEXT:    fmov s3, w4
857; CHECK-i32-NEXT:    fmov s5, w17
858; CHECK-i32-NEXT:    fmov s7, w14
859; CHECK-i32-NEXT:    fcvtzs w27, s18
860; CHECK-i32-NEXT:    mov v0.s[1], w24
861; CHECK-i32-NEXT:    ldp x24, x23, [sp, #32] // 16-byte Folded Reload
862; CHECK-i32-NEXT:    mov v2.s[1], w26
863; CHECK-i32-NEXT:    mov v4.s[1], w25
864; CHECK-i32-NEXT:    mov v1.s[1], w5
865; CHECK-i32-NEXT:    ldp x26, x25, [sp, #16] // 16-byte Folded Reload
866; CHECK-i32-NEXT:    mov v3.s[1], w3
867; CHECK-i32-NEXT:    mov v6.s[1], w2
868; CHECK-i32-NEXT:    mov v5.s[1], w15
869; CHECK-i32-NEXT:    mov v7.s[1], w13
870; CHECK-i32-NEXT:    fcvtzs w13, s16
871; CHECK-i32-NEXT:    fcvtzs w14, s17
872; CHECK-i32-NEXT:    fcvtzs w15, s19
873; CHECK-i32-NEXT:    fcvtzs w17, s20
874; CHECK-i32-NEXT:    mov v0.s[2], w27
875; CHECK-i32-NEXT:    mov v1.s[2], w0
876; CHECK-i32-NEXT:    mov v2.s[2], w20
877; CHECK-i32-NEXT:    mov v4.s[2], w19
878; CHECK-i32-NEXT:    mov v3.s[2], w16
879; CHECK-i32-NEXT:    ldp x20, x19, [sp, #64] // 16-byte Folded Reload
880; CHECK-i32-NEXT:    mov v6.s[2], w1
881; CHECK-i32-NEXT:    mov v5.s[2], w12
882; CHECK-i32-NEXT:    mov v7.s[2], w10
883; CHECK-i32-NEXT:    mov v0.s[3], w17
884; CHECK-i32-NEXT:    mov v1.s[3], w18
885; CHECK-i32-NEXT:    mov v2.s[3], w15
886; CHECK-i32-NEXT:    mov v4.s[3], w14
887; CHECK-i32-NEXT:    mov v3.s[3], w11
888; CHECK-i32-NEXT:    mov v6.s[3], w13
889; CHECK-i32-NEXT:    mov v5.s[3], w9
890; CHECK-i32-NEXT:    mov v7.s[3], w8
891; CHECK-i32-NEXT:    ldr x27, [sp], #80 // 8-byte Folded Reload
892; CHECK-i32-NEXT:    ret
893;
894; CHECK-i64-LABEL: lrint_v32f32:
895; CHECK-i64:       // %bb.0:
896; CHECK-i64-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
897; CHECK-i64-NEXT:    sub x9, sp, #272
898; CHECK-i64-NEXT:    mov x29, sp
899; CHECK-i64-NEXT:    and sp, x9, #0xffffffffffffffe0
900; CHECK-i64-NEXT:    .cfi_def_cfa w29, 16
901; CHECK-i64-NEXT:    .cfi_offset w30, -8
902; CHECK-i64-NEXT:    .cfi_offset w29, -16
903; CHECK-i64-NEXT:    frintx v0.4s, v0.4s
904; CHECK-i64-NEXT:    frintx v1.4s, v1.4s
905; CHECK-i64-NEXT:    frintx v2.4s, v2.4s
906; CHECK-i64-NEXT:    ptrue p0.d, vl4
907; CHECK-i64-NEXT:    mov s16, v0.s[3]
908; CHECK-i64-NEXT:    mov s17, v0.s[2]
909; CHECK-i64-NEXT:    mov s18, v0.s[1]
910; CHECK-i64-NEXT:    fcvtzs x12, s0
911; CHECK-i64-NEXT:    frintx v0.4s, v3.4s
912; CHECK-i64-NEXT:    mov s3, v2.s[3]
913; CHECK-i64-NEXT:    fcvtzs x9, s16
914; CHECK-i64-NEXT:    mov s16, v1.s[3]
915; CHECK-i64-NEXT:    fcvtzs x10, s17
916; CHECK-i64-NEXT:    mov s17, v1.s[2]
917; CHECK-i64-NEXT:    fcvtzs x11, s18
918; CHECK-i64-NEXT:    mov s18, v1.s[1]
919; CHECK-i64-NEXT:    fcvtzs x13, s16
920; CHECK-i64-NEXT:    stp x10, x9, [sp, #16]
921; CHECK-i64-NEXT:    mov s16, v2.s[2]
922; CHECK-i64-NEXT:    fcvtzs x9, s17
923; CHECK-i64-NEXT:    fcvtzs x10, s18
924; CHECK-i64-NEXT:    mov s17, v2.s[1]
925; CHECK-i64-NEXT:    stp x12, x11, [sp]
926; CHECK-i64-NEXT:    fcvtzs x11, s1
927; CHECK-i64-NEXT:    frintx v1.4s, v4.4s
928; CHECK-i64-NEXT:    fcvtzs x12, s3
929; CHECK-i64-NEXT:    mov s3, v0.s[3]
930; CHECK-i64-NEXT:    mov s4, v0.s[2]
931; CHECK-i64-NEXT:    stp x9, x13, [sp, #48]
932; CHECK-i64-NEXT:    fcvtzs x13, s16
933; CHECK-i64-NEXT:    fcvtzs x9, s17
934; CHECK-i64-NEXT:    mov s16, v0.s[1]
935; CHECK-i64-NEXT:    stp x11, x10, [sp, #32]
936; CHECK-i64-NEXT:    fcvtzs x10, s2
937; CHECK-i64-NEXT:    frintx v2.4s, v5.4s
938; CHECK-i64-NEXT:    fcvtzs x11, s3
939; CHECK-i64-NEXT:    mov s3, v1.s[3]
940; CHECK-i64-NEXT:    mov s5, v1.s[1]
941; CHECK-i64-NEXT:    stp x13, x12, [sp, #80]
942; CHECK-i64-NEXT:    fcvtzs x12, s4
943; CHECK-i64-NEXT:    mov s4, v1.s[2]
944; CHECK-i64-NEXT:    fcvtzs x13, s16
945; CHECK-i64-NEXT:    stp x10, x9, [sp, #64]
946; CHECK-i64-NEXT:    fcvtzs x9, s0
947; CHECK-i64-NEXT:    mov s0, v2.s[3]
948; CHECK-i64-NEXT:    fcvtzs x10, s3
949; CHECK-i64-NEXT:    frintx v3.4s, v6.4s
950; CHECK-i64-NEXT:    stp x12, x11, [sp, #112]
951; CHECK-i64-NEXT:    fcvtzs x11, s4
952; CHECK-i64-NEXT:    mov s4, v2.s[2]
953; CHECK-i64-NEXT:    fcvtzs x12, s5
954; CHECK-i64-NEXT:    mov s5, v2.s[1]
955; CHECK-i64-NEXT:    stp x9, x13, [sp, #96]
956; CHECK-i64-NEXT:    fcvtzs x9, s1
957; CHECK-i64-NEXT:    fcvtzs x13, s0
958; CHECK-i64-NEXT:    mov s0, v3.s[3]
959; CHECK-i64-NEXT:    frintx v1.4s, v7.4s
960; CHECK-i64-NEXT:    stp x11, x10, [sp, #144]
961; CHECK-i64-NEXT:    fcvtzs x10, s4
962; CHECK-i64-NEXT:    mov s4, v3.s[2]
963; CHECK-i64-NEXT:    fcvtzs x11, s5
964; CHECK-i64-NEXT:    mov s5, v3.s[1]
965; CHECK-i64-NEXT:    stp x9, x12, [sp, #128]
966; CHECK-i64-NEXT:    fcvtzs x9, s2
967; CHECK-i64-NEXT:    fcvtzs x12, s0
968; CHECK-i64-NEXT:    mov s0, v1.s[3]
969; CHECK-i64-NEXT:    mov s2, v1.s[2]
970; CHECK-i64-NEXT:    stp x10, x13, [sp, #176]
971; CHECK-i64-NEXT:    fcvtzs x10, s4
972; CHECK-i64-NEXT:    mov s4, v1.s[1]
973; CHECK-i64-NEXT:    fcvtzs x13, s5
974; CHECK-i64-NEXT:    stp x9, x11, [sp, #160]
975; CHECK-i64-NEXT:    fcvtzs x9, s3
976; CHECK-i64-NEXT:    fcvtzs x11, s0
977; CHECK-i64-NEXT:    stp x10, x12, [sp, #208]
978; CHECK-i64-NEXT:    fcvtzs x10, s2
979; CHECK-i64-NEXT:    fcvtzs x12, s4
980; CHECK-i64-NEXT:    stp x9, x13, [sp, #192]
981; CHECK-i64-NEXT:    fcvtzs x9, s1
982; CHECK-i64-NEXT:    stp x10, x11, [sp, #240]
983; CHECK-i64-NEXT:    add x10, sp, #64
984; CHECK-i64-NEXT:    stp x9, x12, [sp, #224]
985; CHECK-i64-NEXT:    mov x9, sp
986; CHECK-i64-NEXT:    ld1d { z0.d }, p0/z, [x9]
987; CHECK-i64-NEXT:    add x9, sp, #32
988; CHECK-i64-NEXT:    ld1d { z2.d }, p0/z, [x10]
989; CHECK-i64-NEXT:    ld1d { z1.d }, p0/z, [x9]
990; CHECK-i64-NEXT:    add x9, sp, #224
991; CHECK-i64-NEXT:    add x10, sp, #96
992; CHECK-i64-NEXT:    ld1d { z3.d }, p0/z, [x9]
993; CHECK-i64-NEXT:    add x9, sp, #192
994; CHECK-i64-NEXT:    ld1d { z4.d }, p0/z, [x10]
995; CHECK-i64-NEXT:    add x10, sp, #160
996; CHECK-i64-NEXT:    ld1d { z5.d }, p0/z, [x9]
997; CHECK-i64-NEXT:    add x9, sp, #128
998; CHECK-i64-NEXT:    ld1d { z6.d }, p0/z, [x10]
999; CHECK-i64-NEXT:    mov x10, #28 // =0x1c
1000; CHECK-i64-NEXT:    ld1d { z7.d }, p0/z, [x9]
1001; CHECK-i64-NEXT:    mov x9, #24 // =0x18
1002; CHECK-i64-NEXT:    st1d { z3.d }, p0, [x8, x10, lsl #3]
1003; CHECK-i64-NEXT:    st1d { z5.d }, p0, [x8, x9, lsl #3]
1004; CHECK-i64-NEXT:    mov x9, #20 // =0x14
1005; CHECK-i64-NEXT:    st1d { z6.d }, p0, [x8, x9, lsl #3]
1006; CHECK-i64-NEXT:    mov x9, #16 // =0x10
1007; CHECK-i64-NEXT:    st1d { z7.d }, p0, [x8, x9, lsl #3]
1008; CHECK-i64-NEXT:    mov x9, #12 // =0xc
1009; CHECK-i64-NEXT:    st1d { z4.d }, p0, [x8, x9, lsl #3]
1010; CHECK-i64-NEXT:    mov x9, #8 // =0x8
1011; CHECK-i64-NEXT:    st1d { z2.d }, p0, [x8, x9, lsl #3]
1012; CHECK-i64-NEXT:    mov x9, #4 // =0x4
1013; CHECK-i64-NEXT:    st1d { z1.d }, p0, [x8, x9, lsl #3]
1014; CHECK-i64-NEXT:    st1d { z0.d }, p0, [x8]
1015; CHECK-i64-NEXT:    mov sp, x29
1016; CHECK-i64-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload
1017; CHECK-i64-NEXT:    ret
1018  %a = call <32 x iXLen> @llvm.lrint.v32iXLen.v32f32(<32 x float> %x)
1019  ret <32 x iXLen> %a
1020}
1021declare <32 x iXLen> @llvm.lrint.v32iXLen.v32f32(<32 x float>)
1022
1023define <1 x iXLen> @lrint_v1f64(<1 x double> %x) {
1024; CHECK-i32-LABEL: lrint_v1f64:
1025; CHECK-i32:       // %bb.0:
1026; CHECK-i32-NEXT:    frintx d0, d0
1027; CHECK-i32-NEXT:    fcvtzs w8, d0
1028; CHECK-i32-NEXT:    fmov s0, w8
1029; CHECK-i32-NEXT:    ret
1030;
1031; CHECK-i64-LABEL: lrint_v1f64:
1032; CHECK-i64:       // %bb.0:
1033; CHECK-i64-NEXT:    frintx d0, d0
1034; CHECK-i64-NEXT:    fcvtzs x8, d0
1035; CHECK-i64-NEXT:    fmov d0, x8
1036; CHECK-i64-NEXT:    ret
1037  %a = call <1 x iXLen> @llvm.lrint.v1iXLen.v1f64(<1 x double> %x)
1038  ret <1 x iXLen> %a
1039}
1040declare <1 x iXLen> @llvm.lrint.v1iXLen.v1f64(<1 x double>)
1041
1042define <2 x iXLen> @lrint_v2f64(<2 x double> %x) {
1043; CHECK-i32-LABEL: lrint_v2f64:
1044; CHECK-i32:       // %bb.0:
1045; CHECK-i32-NEXT:    frintx v0.2d, v0.2d
1046; CHECK-i32-NEXT:    mov d1, v0.d[1]
1047; CHECK-i32-NEXT:    fcvtzs w8, d0
1048; CHECK-i32-NEXT:    fcvtzs w9, d1
1049; CHECK-i32-NEXT:    fmov s0, w8
1050; CHECK-i32-NEXT:    mov v0.s[1], w9
1051; CHECK-i32-NEXT:    // kill: def $d0 killed $d0 killed $q0
1052; CHECK-i32-NEXT:    ret
1053;
1054; CHECK-i64-LABEL: lrint_v2f64:
1055; CHECK-i64:       // %bb.0:
1056; CHECK-i64-NEXT:    frintx v0.2d, v0.2d
1057; CHECK-i64-NEXT:    fcvtzs v0.2d, v0.2d
1058; CHECK-i64-NEXT:    ret
1059  %a = call <2 x iXLen> @llvm.lrint.v2iXLen.v2f64(<2 x double> %x)
1060  ret <2 x iXLen> %a
1061}
1062declare <2 x iXLen> @llvm.lrint.v2iXLen.v2f64(<2 x double>)
1063
1064define <4 x iXLen> @lrint_v4f64(<4 x double> %x) {
1065; CHECK-i32-LABEL: lrint_v4f64:
1066; CHECK-i32:       // %bb.0:
1067; CHECK-i32-NEXT:    ptrue p0.d, vl2
1068; CHECK-i32-NEXT:    // kill: def $q0 killed $q0 def $z0
1069; CHECK-i32-NEXT:    // kill: def $q1 killed $q1 def $z1
1070; CHECK-i32-NEXT:    splice z0.d, p0, z0.d, z1.d
1071; CHECK-i32-NEXT:    ptrue p0.d, vl4
1072; CHECK-i32-NEXT:    movprfx z1, z0
1073; CHECK-i32-NEXT:    frintx z1.d, p0/m, z0.d
1074; CHECK-i32-NEXT:    mov z0.d, z1.d[1]
1075; CHECK-i32-NEXT:    fcvtzs w8, d1
1076; CHECK-i32-NEXT:    mov z2.d, z1.d[2]
1077; CHECK-i32-NEXT:    mov z1.d, z1.d[3]
1078; CHECK-i32-NEXT:    fcvtzs w9, d0
1079; CHECK-i32-NEXT:    fmov s0, w8
1080; CHECK-i32-NEXT:    fcvtzs w8, d2
1081; CHECK-i32-NEXT:    mov v0.s[1], w9
1082; CHECK-i32-NEXT:    mov v0.s[2], w8
1083; CHECK-i32-NEXT:    fcvtzs w8, d1
1084; CHECK-i32-NEXT:    mov v0.s[3], w8
1085; CHECK-i32-NEXT:    ret
1086;
1087; CHECK-i64-LABEL: lrint_v4f64:
1088; CHECK-i64:       // %bb.0:
1089; CHECK-i64-NEXT:    ptrue p0.d, vl2
1090; CHECK-i64-NEXT:    // kill: def $q0 killed $q0 def $z0
1091; CHECK-i64-NEXT:    // kill: def $q1 killed $q1 def $z1
1092; CHECK-i64-NEXT:    splice z0.d, p0, z0.d, z1.d
1093; CHECK-i64-NEXT:    ptrue p0.d, vl4
1094; CHECK-i64-NEXT:    frintx z0.d, p0/m, z0.d
1095; CHECK-i64-NEXT:    mov z1.d, z0.d[2]
1096; CHECK-i64-NEXT:    mov z2.d, z0.d[3]
1097; CHECK-i64-NEXT:    mov z3.d, z0.d[1]
1098; CHECK-i64-NEXT:    fcvtzs x9, d0
1099; CHECK-i64-NEXT:    fcvtzs x8, d1
1100; CHECK-i64-NEXT:    fcvtzs x10, d2
1101; CHECK-i64-NEXT:    fcvtzs x11, d3
1102; CHECK-i64-NEXT:    fmov d0, x9
1103; CHECK-i64-NEXT:    fmov d1, x8
1104; CHECK-i64-NEXT:    mov v0.d[1], x11
1105; CHECK-i64-NEXT:    mov v1.d[1], x10
1106; CHECK-i64-NEXT:    ret
1107  %a = call <4 x iXLen> @llvm.lrint.v4iXLen.v4f64(<4 x double> %x)
1108  ret <4 x iXLen> %a
1109}
1110declare <4 x iXLen> @llvm.lrint.v4iXLen.v4f64(<4 x double>)
1111
1112define <8 x iXLen> @lrint_v8f64(<8 x double> %x) {
1113; CHECK-i32-LABEL: lrint_v8f64:
1114; CHECK-i32:       // %bb.0:
1115; CHECK-i32-NEXT:    ptrue p0.d, vl2
1116; CHECK-i32-NEXT:    // kill: def $q2 killed $q2 def $z2
1117; CHECK-i32-NEXT:    // kill: def $q0 killed $q0 def $z0
1118; CHECK-i32-NEXT:    // kill: def $q3 killed $q3 def $z3
1119; CHECK-i32-NEXT:    // kill: def $q1 killed $q1 def $z1
1120; CHECK-i32-NEXT:    splice z0.d, p0, z0.d, z1.d
1121; CHECK-i32-NEXT:    splice z2.d, p0, z2.d, z3.d
1122; CHECK-i32-NEXT:    ptrue p0.d, vl4
1123; CHECK-i32-NEXT:    movprfx z3, z0
1124; CHECK-i32-NEXT:    frintx z3.d, p0/m, z0.d
1125; CHECK-i32-NEXT:    frintx z2.d, p0/m, z2.d
1126; CHECK-i32-NEXT:    mov z0.d, z3.d[1]
1127; CHECK-i32-NEXT:    mov z1.d, z2.d[1]
1128; CHECK-i32-NEXT:    fcvtzs w8, d3
1129; CHECK-i32-NEXT:    fcvtzs w9, d2
1130; CHECK-i32-NEXT:    mov z4.d, z3.d[2]
1131; CHECK-i32-NEXT:    mov z5.d, z2.d[2]
1132; CHECK-i32-NEXT:    mov z3.d, z3.d[3]
1133; CHECK-i32-NEXT:    mov z2.d, z2.d[3]
1134; CHECK-i32-NEXT:    fcvtzs w10, d0
1135; CHECK-i32-NEXT:    fcvtzs w11, d1
1136; CHECK-i32-NEXT:    fmov s0, w8
1137; CHECK-i32-NEXT:    fcvtzs w8, d4
1138; CHECK-i32-NEXT:    fmov s1, w9
1139; CHECK-i32-NEXT:    fcvtzs w9, d5
1140; CHECK-i32-NEXT:    mov v0.s[1], w10
1141; CHECK-i32-NEXT:    mov v1.s[1], w11
1142; CHECK-i32-NEXT:    mov v0.s[2], w8
1143; CHECK-i32-NEXT:    fcvtzs w8, d3
1144; CHECK-i32-NEXT:    mov v1.s[2], w9
1145; CHECK-i32-NEXT:    fcvtzs w9, d2
1146; CHECK-i32-NEXT:    mov v0.s[3], w8
1147; CHECK-i32-NEXT:    mov v1.s[3], w9
1148; CHECK-i32-NEXT:    ret
1149;
1150; CHECK-i64-LABEL: lrint_v8f64:
1151; CHECK-i64:       // %bb.0:
1152; CHECK-i64-NEXT:    ptrue p0.d, vl2
1153; CHECK-i64-NEXT:    // kill: def $q2 killed $q2 def $z2
1154; CHECK-i64-NEXT:    // kill: def $q0 killed $q0 def $z0
1155; CHECK-i64-NEXT:    // kill: def $q3 killed $q3 def $z3
1156; CHECK-i64-NEXT:    // kill: def $q1 killed $q1 def $z1
1157; CHECK-i64-NEXT:    splice z0.d, p0, z0.d, z1.d
1158; CHECK-i64-NEXT:    splice z2.d, p0, z2.d, z3.d
1159; CHECK-i64-NEXT:    ptrue p0.d, vl4
1160; CHECK-i64-NEXT:    frintx z0.d, p0/m, z0.d
1161; CHECK-i64-NEXT:    movprfx z1, z2
1162; CHECK-i64-NEXT:    frintx z1.d, p0/m, z2.d
1163; CHECK-i64-NEXT:    mov z4.d, z1.d[2]
1164; CHECK-i64-NEXT:    mov z5.d, z0.d[2]
1165; CHECK-i64-NEXT:    mov z2.d, z0.d[1]
1166; CHECK-i64-NEXT:    mov z3.d, z1.d[3]
1167; CHECK-i64-NEXT:    mov z6.d, z0.d[3]
1168; CHECK-i64-NEXT:    fcvtzs x8, d0
1169; CHECK-i64-NEXT:    mov z0.d, z1.d[1]
1170; CHECK-i64-NEXT:    fcvtzs x10, d1
1171; CHECK-i64-NEXT:    fcvtzs x11, d4
1172; CHECK-i64-NEXT:    fcvtzs x12, d5
1173; CHECK-i64-NEXT:    fcvtzs x9, d2
1174; CHECK-i64-NEXT:    fcvtzs x13, d3
1175; CHECK-i64-NEXT:    fcvtzs x14, d6
1176; CHECK-i64-NEXT:    fcvtzs x15, d0
1177; CHECK-i64-NEXT:    fmov d0, x8
1178; CHECK-i64-NEXT:    fmov d2, x10
1179; CHECK-i64-NEXT:    fmov d1, x12
1180; CHECK-i64-NEXT:    fmov d3, x11
1181; CHECK-i64-NEXT:    mov v0.d[1], x9
1182; CHECK-i64-NEXT:    mov v2.d[1], x15
1183; CHECK-i64-NEXT:    mov v1.d[1], x14
1184; CHECK-i64-NEXT:    mov v3.d[1], x13
1185; CHECK-i64-NEXT:    ret
1186  %a = call <8 x iXLen> @llvm.lrint.v8iXLen.v8f64(<8 x double> %x)
1187  ret <8 x iXLen> %a
1188}
1189declare <8 x iXLen> @llvm.lrint.v8iXLen.v8f64(<8 x double>)
1190
1191define <16 x iXLen> @lrint_v16f64(<16 x double> %x) {
1192; CHECK-i32-LABEL: lrint_v16f64:
1193; CHECK-i32:       // %bb.0:
1194; CHECK-i32-NEXT:    ptrue p1.d, vl2
1195; CHECK-i32-NEXT:    // kill: def $q0 killed $q0 def $z0
1196; CHECK-i32-NEXT:    // kill: def $q6 killed $q6 def $z6
1197; CHECK-i32-NEXT:    // kill: def $q4 killed $q4 def $z4
1198; CHECK-i32-NEXT:    // kill: def $q2 killed $q2 def $z2
1199; CHECK-i32-NEXT:    // kill: def $q1 killed $q1 def $z1
1200; CHECK-i32-NEXT:    // kill: def $q7 killed $q7 def $z7
1201; CHECK-i32-NEXT:    // kill: def $q5 killed $q5 def $z5
1202; CHECK-i32-NEXT:    // kill: def $q3 killed $q3 def $z3
1203; CHECK-i32-NEXT:    ptrue p0.d, vl4
1204; CHECK-i32-NEXT:    splice z0.d, p1, z0.d, z1.d
1205; CHECK-i32-NEXT:    splice z2.d, p1, z2.d, z3.d
1206; CHECK-i32-NEXT:    splice z4.d, p1, z4.d, z5.d
1207; CHECK-i32-NEXT:    splice z6.d, p1, z6.d, z7.d
1208; CHECK-i32-NEXT:    movprfx z5, z0
1209; CHECK-i32-NEXT:    frintx z5.d, p0/m, z0.d
1210; CHECK-i32-NEXT:    movprfx z7, z2
1211; CHECK-i32-NEXT:    frintx z7.d, p0/m, z2.d
1212; CHECK-i32-NEXT:    frintx z4.d, p0/m, z4.d
1213; CHECK-i32-NEXT:    frintx z6.d, p0/m, z6.d
1214; CHECK-i32-NEXT:    fcvtzs w8, d5
1215; CHECK-i32-NEXT:    mov z0.d, z5.d[1]
1216; CHECK-i32-NEXT:    mov z1.d, z7.d[1]
1217; CHECK-i32-NEXT:    fcvtzs w9, d7
1218; CHECK-i32-NEXT:    mov z3.d, z4.d[1]
1219; CHECK-i32-NEXT:    fcvtzs w10, d4
1220; CHECK-i32-NEXT:    mov z16.d, z6.d[1]
1221; CHECK-i32-NEXT:    fcvtzs w12, d6
1222; CHECK-i32-NEXT:    mov z2.d, z5.d[2]
1223; CHECK-i32-NEXT:    fcvtzs w11, d0
1224; CHECK-i32-NEXT:    fcvtzs w13, d1
1225; CHECK-i32-NEXT:    mov z17.d, z7.d[2]
1226; CHECK-i32-NEXT:    fcvtzs w14, d3
1227; CHECK-i32-NEXT:    fmov s0, w8
1228; CHECK-i32-NEXT:    mov z18.d, z4.d[2]
1229; CHECK-i32-NEXT:    fcvtzs w8, d16
1230; CHECK-i32-NEXT:    mov z19.d, z6.d[2]
1231; CHECK-i32-NEXT:    fcvtzs w15, d2
1232; CHECK-i32-NEXT:    fmov s1, w9
1233; CHECK-i32-NEXT:    fmov s2, w10
1234; CHECK-i32-NEXT:    fmov s3, w12
1235; CHECK-i32-NEXT:    fcvtzs w9, d17
1236; CHECK-i32-NEXT:    fcvtzs w10, d18
1237; CHECK-i32-NEXT:    mov v0.s[1], w11
1238; CHECK-i32-NEXT:    fcvtzs w11, d19
1239; CHECK-i32-NEXT:    mov z5.d, z5.d[3]
1240; CHECK-i32-NEXT:    mov z7.d, z7.d[3]
1241; CHECK-i32-NEXT:    mov v1.s[1], w13
1242; CHECK-i32-NEXT:    mov v2.s[1], w14
1243; CHECK-i32-NEXT:    mov v3.s[1], w8
1244; CHECK-i32-NEXT:    mov z4.d, z4.d[3]
1245; CHECK-i32-NEXT:    mov z6.d, z6.d[3]
1246; CHECK-i32-NEXT:    mov v0.s[2], w15
1247; CHECK-i32-NEXT:    fcvtzs w8, d5
1248; CHECK-i32-NEXT:    mov v1.s[2], w9
1249; CHECK-i32-NEXT:    fcvtzs w9, d7
1250; CHECK-i32-NEXT:    mov v2.s[2], w10
1251; CHECK-i32-NEXT:    fcvtzs w10, d4
1252; CHECK-i32-NEXT:    mov v3.s[2], w11
1253; CHECK-i32-NEXT:    fcvtzs w11, d6
1254; CHECK-i32-NEXT:    mov v0.s[3], w8
1255; CHECK-i32-NEXT:    mov v1.s[3], w9
1256; CHECK-i32-NEXT:    mov v2.s[3], w10
1257; CHECK-i32-NEXT:    mov v3.s[3], w11
1258; CHECK-i32-NEXT:    ret
1259;
1260; CHECK-i64-LABEL: lrint_v16f64:
1261; CHECK-i64:       // %bb.0:
1262; CHECK-i64-NEXT:    ptrue p1.d, vl2
1263; CHECK-i64-NEXT:    // kill: def $q6 killed $q6 def $z6
1264; CHECK-i64-NEXT:    // kill: def $q4 killed $q4 def $z4
1265; CHECK-i64-NEXT:    // kill: def $q7 killed $q7 def $z7
1266; CHECK-i64-NEXT:    // kill: def $q5 killed $q5 def $z5
1267; CHECK-i64-NEXT:    // kill: def $q2 killed $q2 def $z2
1268; CHECK-i64-NEXT:    // kill: def $q0 killed $q0 def $z0
1269; CHECK-i64-NEXT:    // kill: def $q3 killed $q3 def $z3
1270; CHECK-i64-NEXT:    // kill: def $q1 killed $q1 def $z1
1271; CHECK-i64-NEXT:    ptrue p0.d, vl4
1272; CHECK-i64-NEXT:    splice z6.d, p1, z6.d, z7.d
1273; CHECK-i64-NEXT:    splice z4.d, p1, z4.d, z5.d
1274; CHECK-i64-NEXT:    splice z2.d, p1, z2.d, z3.d
1275; CHECK-i64-NEXT:    splice z0.d, p1, z0.d, z1.d
1276; CHECK-i64-NEXT:    movprfx z3, z6
1277; CHECK-i64-NEXT:    frintx z3.d, p0/m, z6.d
1278; CHECK-i64-NEXT:    movprfx z1, z4
1279; CHECK-i64-NEXT:    frintx z1.d, p0/m, z4.d
1280; CHECK-i64-NEXT:    frintx z2.d, p0/m, z2.d
1281; CHECK-i64-NEXT:    frintx z0.d, p0/m, z0.d
1282; CHECK-i64-NEXT:    mov z4.d, z3.d[2]
1283; CHECK-i64-NEXT:    mov z5.d, z1.d[2]
1284; CHECK-i64-NEXT:    mov z6.d, z2.d[3]
1285; CHECK-i64-NEXT:    fcvtzs x11, d0
1286; CHECK-i64-NEXT:    fcvtzs x12, d1
1287; CHECK-i64-NEXT:    fcvtzs x13, d2
1288; CHECK-i64-NEXT:    fcvtzs x14, d3
1289; CHECK-i64-NEXT:    mov z7.d, z3.d[3]
1290; CHECK-i64-NEXT:    mov z16.d, z1.d[3]
1291; CHECK-i64-NEXT:    fcvtzs x9, d4
1292; CHECK-i64-NEXT:    fcvtzs x10, d5
1293; CHECK-i64-NEXT:    mov z4.d, z2.d[2]
1294; CHECK-i64-NEXT:    mov z5.d, z0.d[2]
1295; CHECK-i64-NEXT:    fcvtzs x8, d6
1296; CHECK-i64-NEXT:    mov z2.d, z2.d[1]
1297; CHECK-i64-NEXT:    mov z6.d, z0.d[3]
1298; CHECK-i64-NEXT:    mov z1.d, z1.d[1]
1299; CHECK-i64-NEXT:    mov z3.d, z3.d[1]
1300; CHECK-i64-NEXT:    fcvtzs x15, d4
1301; CHECK-i64-NEXT:    mov z4.d, z0.d[1]
1302; CHECK-i64-NEXT:    fmov d0, x11
1303; CHECK-i64-NEXT:    fcvtzs x16, d5
1304; CHECK-i64-NEXT:    fcvtzs x11, d2
1305; CHECK-i64-NEXT:    fmov d2, x13
1306; CHECK-i64-NEXT:    fcvtzs x17, d7
1307; CHECK-i64-NEXT:    fcvtzs x18, d16
1308; CHECK-i64-NEXT:    fcvtzs x0, d3
1309; CHECK-i64-NEXT:    fcvtzs x13, d4
1310; CHECK-i64-NEXT:    fmov d4, x12
1311; CHECK-i64-NEXT:    fcvtzs x12, d6
1312; CHECK-i64-NEXT:    fmov d6, x14
1313; CHECK-i64-NEXT:    fcvtzs x14, d1
1314; CHECK-i64-NEXT:    fmov d3, x15
1315; CHECK-i64-NEXT:    fmov d1, x16
1316; CHECK-i64-NEXT:    fmov d5, x10
1317; CHECK-i64-NEXT:    fmov d7, x9
1318; CHECK-i64-NEXT:    mov v2.d[1], x11
1319; CHECK-i64-NEXT:    mov v0.d[1], x13
1320; CHECK-i64-NEXT:    mov v3.d[1], x8
1321; CHECK-i64-NEXT:    mov v6.d[1], x0
1322; CHECK-i64-NEXT:    mov v4.d[1], x14
1323; CHECK-i64-NEXT:    mov v1.d[1], x12
1324; CHECK-i64-NEXT:    mov v5.d[1], x18
1325; CHECK-i64-NEXT:    mov v7.d[1], x17
1326; CHECK-i64-NEXT:    ret
1327  %a = call <16 x iXLen> @llvm.lrint.v16iXLen.v16f64(<16 x double> %x)
1328  ret <16 x iXLen> %a
1329}
1330declare <16 x iXLen> @llvm.lrint.v16iXLen.v16f64(<16 x double>)
1331
1332define <32 x iXLen> @lrint_v32f64(<32 x double> %x) {
1333; CHECK-i32-LABEL: lrint_v32f64:
1334; CHECK-i32:       // %bb.0:
1335; CHECK-i32-NEXT:    ptrue p1.d, vl2
1336; CHECK-i32-NEXT:    // kill: def $q0 killed $q0 def $z0
1337; CHECK-i32-NEXT:    // kill: def $q1 killed $q1 def $z1
1338; CHECK-i32-NEXT:    // kill: def $q3 killed $q3 def $z3
1339; CHECK-i32-NEXT:    // kill: def $q2 killed $q2 def $z2
1340; CHECK-i32-NEXT:    // kill: def $q4 killed $q4 def $z4
1341; CHECK-i32-NEXT:    // kill: def $q5 killed $q5 def $z5
1342; CHECK-i32-NEXT:    // kill: def $q7 killed $q7 def $z7
1343; CHECK-i32-NEXT:    // kill: def $q6 killed $q6 def $z6
1344; CHECK-i32-NEXT:    ptrue p0.d, vl4
1345; CHECK-i32-NEXT:    splice z0.d, p1, z0.d, z1.d
1346; CHECK-i32-NEXT:    splice z2.d, p1, z2.d, z3.d
1347; CHECK-i32-NEXT:    splice z4.d, p1, z4.d, z5.d
1348; CHECK-i32-NEXT:    ldp q1, q3, [sp]
1349; CHECK-i32-NEXT:    splice z6.d, p1, z6.d, z7.d
1350; CHECK-i32-NEXT:    frintx z0.d, p0/m, z0.d
1351; CHECK-i32-NEXT:    splice z1.d, p1, z1.d, z3.d
1352; CHECK-i32-NEXT:    movprfx z18, z2
1353; CHECK-i32-NEXT:    frintx z18.d, p0/m, z2.d
1354; CHECK-i32-NEXT:    ldp q5, q3, [sp, #96]
1355; CHECK-i32-NEXT:    ldp q2, q7, [sp, #64]
1356; CHECK-i32-NEXT:    splice z5.d, p1, z5.d, z3.d
1357; CHECK-i32-NEXT:    movprfx z3, z4
1358; CHECK-i32-NEXT:    frintx z3.d, p0/m, z4.d
1359; CHECK-i32-NEXT:    mov z4.d, z0.d[1]
1360; CHECK-i32-NEXT:    fcvtzs w8, d0
1361; CHECK-i32-NEXT:    splice z2.d, p1, z2.d, z7.d
1362; CHECK-i32-NEXT:    mov z19.d, z18.d[1]
1363; CHECK-i32-NEXT:    ldp q7, q16, [sp, #32]
1364; CHECK-i32-NEXT:    movprfx z17, z1
1365; CHECK-i32-NEXT:    frintx z17.d, p0/m, z1.d
1366; CHECK-i32-NEXT:    fcvtzs w10, d4
1367; CHECK-i32-NEXT:    mov z1.d, z0.d[2]
1368; CHECK-i32-NEXT:    fcvtzs w9, d18
1369; CHECK-i32-NEXT:    mov z4.d, z0.d[3]
1370; CHECK-i32-NEXT:    fcvtzs w11, d19
1371; CHECK-i32-NEXT:    mov z20.d, z18.d[3]
1372; CHECK-i32-NEXT:    fmov s0, w8
1373; CHECK-i32-NEXT:    splice z7.d, p1, z7.d, z16.d
1374; CHECK-i32-NEXT:    movprfx z16, z6
1375; CHECK-i32-NEXT:    frintx z16.d, p0/m, z6.d
1376; CHECK-i32-NEXT:    mov z6.d, z18.d[2]
1377; CHECK-i32-NEXT:    mov z18.d, z3.d[1]
1378; CHECK-i32-NEXT:    fcvtzs w12, d3
1379; CHECK-i32-NEXT:    fcvtzs w13, d1
1380; CHECK-i32-NEXT:    fmov s1, w9
1381; CHECK-i32-NEXT:    movprfx z19, z2
1382; CHECK-i32-NEXT:    frintx z19.d, p0/m, z2.d
1383; CHECK-i32-NEXT:    mov v0.s[1], w10
1384; CHECK-i32-NEXT:    mov z21.d, z3.d[2]
1385; CHECK-i32-NEXT:    fcvtzs w8, d4
1386; CHECK-i32-NEXT:    fcvtzs w14, d6
1387; CHECK-i32-NEXT:    mov z6.d, z16.d[1]
1388; CHECK-i32-NEXT:    fcvtzs w15, d18
1389; CHECK-i32-NEXT:    movprfx z18, z7
1390; CHECK-i32-NEXT:    frintx z18.d, p0/m, z7.d
1391; CHECK-i32-NEXT:    mov v1.s[1], w11
1392; CHECK-i32-NEXT:    fmov s2, w12
1393; CHECK-i32-NEXT:    mov z7.d, z17.d[1]
1394; CHECK-i32-NEXT:    mov z4.d, z16.d[2]
1395; CHECK-i32-NEXT:    fcvtzs w16, d16
1396; CHECK-i32-NEXT:    mov v0.s[2], w13
1397; CHECK-i32-NEXT:    fcvtzs w13, d17
1398; CHECK-i32-NEXT:    fcvtzs w12, d6
1399; CHECK-i32-NEXT:    mov z6.d, z19.d[1]
1400; CHECK-i32-NEXT:    fcvtzs w11, d21
1401; CHECK-i32-NEXT:    movprfx z21, z5
1402; CHECK-i32-NEXT:    frintx z21.d, p0/m, z5.d
1403; CHECK-i32-NEXT:    mov z3.d, z3.d[3]
1404; CHECK-i32-NEXT:    mov v2.s[1], w15
1405; CHECK-i32-NEXT:    mov z5.d, z18.d[1]
1406; CHECK-i32-NEXT:    fcvtzs w15, d7
1407; CHECK-i32-NEXT:    fcvtzs w0, d19
1408; CHECK-i32-NEXT:    mov v1.s[2], w14
1409; CHECK-i32-NEXT:    fcvtzs w14, d4
1410; CHECK-i32-NEXT:    mov z7.d, z18.d[2]
1411; CHECK-i32-NEXT:    fmov s4, w13
1412; CHECK-i32-NEXT:    fcvtzs w13, d6
1413; CHECK-i32-NEXT:    mov z6.d, z19.d[2]
1414; CHECK-i32-NEXT:    fcvtzs w10, d3
1415; CHECK-i32-NEXT:    fmov s3, w16
1416; CHECK-i32-NEXT:    fcvtzs w17, d18
1417; CHECK-i32-NEXT:    fcvtzs w18, d5
1418; CHECK-i32-NEXT:    mov z5.d, z21.d[1]
1419; CHECK-i32-NEXT:    fcvtzs w2, d21
1420; CHECK-i32-NEXT:    fcvtzs w1, d7
1421; CHECK-i32-NEXT:    mov z7.d, z21.d[2]
1422; CHECK-i32-NEXT:    mov v4.s[1], w15
1423; CHECK-i32-NEXT:    fcvtzs w15, d6
1424; CHECK-i32-NEXT:    fmov s6, w0
1425; CHECK-i32-NEXT:    mov v3.s[1], w12
1426; CHECK-i32-NEXT:    fcvtzs w9, d20
1427; CHECK-i32-NEXT:    fcvtzs w12, d5
1428; CHECK-i32-NEXT:    mov z20.d, z17.d[2]
1429; CHECK-i32-NEXT:    fmov s5, w17
1430; CHECK-i32-NEXT:    mov z16.d, z16.d[3]
1431; CHECK-i32-NEXT:    mov z17.d, z17.d[3]
1432; CHECK-i32-NEXT:    mov z18.d, z18.d[3]
1433; CHECK-i32-NEXT:    mov v6.s[1], w13
1434; CHECK-i32-NEXT:    fcvtzs w13, d7
1435; CHECK-i32-NEXT:    fmov s7, w2
1436; CHECK-i32-NEXT:    fcvtzs w16, d20
1437; CHECK-i32-NEXT:    mov v5.s[1], w18
1438; CHECK-i32-NEXT:    mov z19.d, z19.d[3]
1439; CHECK-i32-NEXT:    mov z20.d, z21.d[3]
1440; CHECK-i32-NEXT:    mov v2.s[2], w11
1441; CHECK-i32-NEXT:    mov v3.s[2], w14
1442; CHECK-i32-NEXT:    mov v7.s[1], w12
1443; CHECK-i32-NEXT:    fcvtzs w11, d16
1444; CHECK-i32-NEXT:    fcvtzs w12, d17
1445; CHECK-i32-NEXT:    fcvtzs w14, d18
1446; CHECK-i32-NEXT:    mov v6.s[2], w15
1447; CHECK-i32-NEXT:    fcvtzs w15, d19
1448; CHECK-i32-NEXT:    mov v4.s[2], w16
1449; CHECK-i32-NEXT:    mov v5.s[2], w1
1450; CHECK-i32-NEXT:    mov v0.s[3], w8
1451; CHECK-i32-NEXT:    mov v1.s[3], w9
1452; CHECK-i32-NEXT:    mov v2.s[3], w10
1453; CHECK-i32-NEXT:    mov v7.s[2], w13
1454; CHECK-i32-NEXT:    fcvtzs w13, d20
1455; CHECK-i32-NEXT:    mov v3.s[3], w11
1456; CHECK-i32-NEXT:    mov v6.s[3], w15
1457; CHECK-i32-NEXT:    mov v4.s[3], w12
1458; CHECK-i32-NEXT:    mov v5.s[3], w14
1459; CHECK-i32-NEXT:    mov v7.s[3], w13
1460; CHECK-i32-NEXT:    ret
1461;
1462; CHECK-i64-LABEL: lrint_v32f64:
1463; CHECK-i64:       // %bb.0:
1464; CHECK-i64-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
1465; CHECK-i64-NEXT:    sub x9, sp, #272
1466; CHECK-i64-NEXT:    mov x29, sp
1467; CHECK-i64-NEXT:    and sp, x9, #0xffffffffffffffe0
1468; CHECK-i64-NEXT:    .cfi_def_cfa w29, 16
1469; CHECK-i64-NEXT:    .cfi_offset w30, -8
1470; CHECK-i64-NEXT:    .cfi_offset w29, -16
1471; CHECK-i64-NEXT:    ptrue p1.d, vl2
1472; CHECK-i64-NEXT:    // kill: def $q0 killed $q0 def $z0
1473; CHECK-i64-NEXT:    // kill: def $q1 killed $q1 def $z1
1474; CHECK-i64-NEXT:    // kill: def $q3 killed $q3 def $z3
1475; CHECK-i64-NEXT:    // kill: def $q2 killed $q2 def $z2
1476; CHECK-i64-NEXT:    // kill: def $q7 killed $q7 def $z7
1477; CHECK-i64-NEXT:    // kill: def $q6 killed $q6 def $z6
1478; CHECK-i64-NEXT:    // kill: def $q4 killed $q4 def $z4
1479; CHECK-i64-NEXT:    // kill: def $q5 killed $q5 def $z5
1480; CHECK-i64-NEXT:    ptrue p0.d, vl4
1481; CHECK-i64-NEXT:    splice z0.d, p1, z0.d, z1.d
1482; CHECK-i64-NEXT:    splice z2.d, p1, z2.d, z3.d
1483; CHECK-i64-NEXT:    splice z4.d, p1, z4.d, z5.d
1484; CHECK-i64-NEXT:    splice z6.d, p1, z6.d, z7.d
1485; CHECK-i64-NEXT:    ldp q5, q19, [x29, #16]
1486; CHECK-i64-NEXT:    movprfx z3, z0
1487; CHECK-i64-NEXT:    frintx z3.d, p0/m, z0.d
1488; CHECK-i64-NEXT:    movprfx z16, z2
1489; CHECK-i64-NEXT:    frintx z16.d, p0/m, z2.d
1490; CHECK-i64-NEXT:    frintx z4.d, p0/m, z4.d
1491; CHECK-i64-NEXT:    splice z5.d, p1, z5.d, z19.d
1492; CHECK-i64-NEXT:    frintx z6.d, p0/m, z6.d
1493; CHECK-i64-NEXT:    ldp q2, q17, [x29, #48]
1494; CHECK-i64-NEXT:    ldp q0, q1, [x29, #112]
1495; CHECK-i64-NEXT:    mov z18.d, z3.d[3]
1496; CHECK-i64-NEXT:    mov z7.d, z3.d[2]
1497; CHECK-i64-NEXT:    fcvtzs x9, d3
1498; CHECK-i64-NEXT:    mov z3.d, z3.d[1]
1499; CHECK-i64-NEXT:    mov z20.d, z16.d[3]
1500; CHECK-i64-NEXT:    fcvtzs x12, d16
1501; CHECK-i64-NEXT:    splice z2.d, p1, z2.d, z17.d
1502; CHECK-i64-NEXT:    frintx z5.d, p0/m, z5.d
1503; CHECK-i64-NEXT:    splice z0.d, p1, z0.d, z1.d
1504; CHECK-i64-NEXT:    fcvtzs x10, d18
1505; CHECK-i64-NEXT:    fcvtzs x11, d7
1506; CHECK-i64-NEXT:    mov z18.d, z16.d[2]
1507; CHECK-i64-NEXT:    mov z7.d, z16.d[1]
1508; CHECK-i64-NEXT:    fcvtzs x13, d3
1509; CHECK-i64-NEXT:    fcvtzs x14, d20
1510; CHECK-i64-NEXT:    str x9, [sp, #128]
1511; CHECK-i64-NEXT:    mov z16.d, z4.d[3]
1512; CHECK-i64-NEXT:    fcvtzs x9, d18
1513; CHECK-i64-NEXT:    mov z18.d, z4.d[2]
1514; CHECK-i64-NEXT:    frintx z2.d, p0/m, z2.d
1515; CHECK-i64-NEXT:    stp x11, x10, [sp, #144]
1516; CHECK-i64-NEXT:    fcvtzs x10, d7
1517; CHECK-i64-NEXT:    mov z7.d, z4.d[1]
1518; CHECK-i64-NEXT:    str x13, [sp, #136]
1519; CHECK-i64-NEXT:    fcvtzs x11, d16
1520; CHECK-i64-NEXT:    mov z16.d, z6.d[3]
1521; CHECK-i64-NEXT:    fcvtzs x13, d18
1522; CHECK-i64-NEXT:    ldp q3, q19, [x29, #80]
1523; CHECK-i64-NEXT:    stp x9, x14, [sp, #176]
1524; CHECK-i64-NEXT:    fcvtzs x9, d4
1525; CHECK-i64-NEXT:    mov z4.d, z6.d[2]
1526; CHECK-i64-NEXT:    stp x12, x10, [sp, #160]
1527; CHECK-i64-NEXT:    fcvtzs x10, d7
1528; CHECK-i64-NEXT:    mov z7.d, z6.d[1]
1529; CHECK-i64-NEXT:    fcvtzs x12, d6
1530; CHECK-i64-NEXT:    splice z3.d, p1, z3.d, z19.d
1531; CHECK-i64-NEXT:    mov z6.d, z5.d[2]
1532; CHECK-i64-NEXT:    stp x13, x11, [sp, #208]
1533; CHECK-i64-NEXT:    fcvtzs x11, d16
1534; CHECK-i64-NEXT:    fcvtzs x13, d4
1535; CHECK-i64-NEXT:    mov z4.d, z5.d[3]
1536; CHECK-i64-NEXT:    mov z1.d, z5.d[1]
1537; CHECK-i64-NEXT:    frintx z0.d, p0/m, z0.d
1538; CHECK-i64-NEXT:    stp x9, x10, [sp, #192]
1539; CHECK-i64-NEXT:    fcvtzs x9, d7
1540; CHECK-i64-NEXT:    frintx z3.d, p0/m, z3.d
1541; CHECK-i64-NEXT:    fcvtzs x10, d4
1542; CHECK-i64-NEXT:    stp x13, x11, [sp, #240]
1543; CHECK-i64-NEXT:    fcvtzs x11, d6
1544; CHECK-i64-NEXT:    mov z4.d, z2.d[3]
1545; CHECK-i64-NEXT:    fcvtzs x13, d2
1546; CHECK-i64-NEXT:    stp x12, x9, [sp, #224]
1547; CHECK-i64-NEXT:    fcvtzs x9, d5
1548; CHECK-i64-NEXT:    fcvtzs x12, d1
1549; CHECK-i64-NEXT:    mov z5.d, z2.d[2]
1550; CHECK-i64-NEXT:    mov z1.d, z2.d[1]
1551; CHECK-i64-NEXT:    mov z2.d, z3.d[2]
1552; CHECK-i64-NEXT:    stp x11, x10, [sp, #16]
1553; CHECK-i64-NEXT:    fcvtzs x10, d4
1554; CHECK-i64-NEXT:    mov z4.d, z3.d[3]
1555; CHECK-i64-NEXT:    fcvtzs x11, d5
1556; CHECK-i64-NEXT:    stp x9, x12, [sp]
1557; CHECK-i64-NEXT:    fcvtzs x9, d1
1558; CHECK-i64-NEXT:    mov z1.d, z3.d[1]
1559; CHECK-i64-NEXT:    fcvtzs x12, d4
1560; CHECK-i64-NEXT:    stp x11, x10, [sp, #48]
1561; CHECK-i64-NEXT:    fcvtzs x10, d2
1562; CHECK-i64-NEXT:    fcvtzs x11, d3
1563; CHECK-i64-NEXT:    stp x13, x9, [sp, #32]
1564; CHECK-i64-NEXT:    fcvtzs x9, d1
1565; CHECK-i64-NEXT:    mov z2.d, z0.d[3]
1566; CHECK-i64-NEXT:    mov z3.d, z0.d[2]
1567; CHECK-i64-NEXT:    mov z1.d, z0.d[1]
1568; CHECK-i64-NEXT:    fcvtzs x13, d2
1569; CHECK-i64-NEXT:    stp x10, x12, [sp, #80]
1570; CHECK-i64-NEXT:    fcvtzs x12, d0
1571; CHECK-i64-NEXT:    fcvtzs x10, d3
1572; CHECK-i64-NEXT:    stp x11, x9, [sp, #64]
1573; CHECK-i64-NEXT:    fcvtzs x9, d1
1574; CHECK-i64-NEXT:    stp x10, x13, [sp, #112]
1575; CHECK-i64-NEXT:    add x10, sp, #192
1576; CHECK-i64-NEXT:    stp x12, x9, [sp, #96]
1577; CHECK-i64-NEXT:    add x9, sp, #128
1578; CHECK-i64-NEXT:    ld1d { z0.d }, p0/z, [x9]
1579; CHECK-i64-NEXT:    add x9, sp, #160
1580; CHECK-i64-NEXT:    ld1d { z2.d }, p0/z, [x10]
1581; CHECK-i64-NEXT:    ld1d { z1.d }, p0/z, [x9]
1582; CHECK-i64-NEXT:    add x9, sp, #96
1583; CHECK-i64-NEXT:    add x10, sp, #224
1584; CHECK-i64-NEXT:    ld1d { z3.d }, p0/z, [x9]
1585; CHECK-i64-NEXT:    add x9, sp, #64
1586; CHECK-i64-NEXT:    ld1d { z4.d }, p0/z, [x10]
1587; CHECK-i64-NEXT:    add x10, sp, #32
1588; CHECK-i64-NEXT:    ld1d { z5.d }, p0/z, [x9]
1589; CHECK-i64-NEXT:    mov x9, sp
1590; CHECK-i64-NEXT:    ld1d { z6.d }, p0/z, [x10]
1591; CHECK-i64-NEXT:    mov x10, #28 // =0x1c
1592; CHECK-i64-NEXT:    ld1d { z7.d }, p0/z, [x9]
1593; CHECK-i64-NEXT:    mov x9, #24 // =0x18
1594; CHECK-i64-NEXT:    st1d { z3.d }, p0, [x8, x10, lsl #3]
1595; CHECK-i64-NEXT:    st1d { z5.d }, p0, [x8, x9, lsl #3]
1596; CHECK-i64-NEXT:    mov x9, #20 // =0x14
1597; CHECK-i64-NEXT:    st1d { z6.d }, p0, [x8, x9, lsl #3]
1598; CHECK-i64-NEXT:    mov x9, #16 // =0x10
1599; CHECK-i64-NEXT:    st1d { z7.d }, p0, [x8, x9, lsl #3]
1600; CHECK-i64-NEXT:    mov x9, #12 // =0xc
1601; CHECK-i64-NEXT:    st1d { z4.d }, p0, [x8, x9, lsl #3]
1602; CHECK-i64-NEXT:    mov x9, #8 // =0x8
1603; CHECK-i64-NEXT:    st1d { z2.d }, p0, [x8, x9, lsl #3]
1604; CHECK-i64-NEXT:    mov x9, #4 // =0x4
1605; CHECK-i64-NEXT:    st1d { z1.d }, p0, [x8, x9, lsl #3]
1606; CHECK-i64-NEXT:    st1d { z0.d }, p0, [x8]
1607; CHECK-i64-NEXT:    mov sp, x29
1608; CHECK-i64-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload
1609; CHECK-i64-NEXT:    ret
1610  %a = call <32 x iXLen> @llvm.lrint.v32iXLen.v16f64(<32 x double> %x)
1611  ret <32 x iXLen> %a
1612}
1613declare <32 x iXLen> @llvm.lrint.v32iXLen.v32f64(<32 x double>)
1614