xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-fixed-vector-llrint.ll (revision 109ede496ecf6de5dabace08d73ec7604b343a6b) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=aarch64 -mattr=+sve -aarch64-sve-vector-bits-min=256 | FileCheck %s
3
4define <1 x i64> @llrint_v1i64_v1f16(<1 x half> %x) {
5; CHECK-LABEL: llrint_v1i64_v1f16:
6; CHECK:       // %bb.0:
7; CHECK-NEXT:    frintx h0, h0
8; CHECK-NEXT:    fcvtzs x8, h0
9; CHECK-NEXT:    fmov d0, x8
10; CHECK-NEXT:    ret
11  %a = call <1 x i64> @llvm.llrint.v1i64.v1f16(<1 x half> %x)
12  ret <1 x i64> %a
13}
14declare <1 x i64> @llvm.llrint.v1i64.v1f16(<1 x half>)
15
16define <2 x i64> @llrint_v1i64_v2f16(<2 x half> %x) {
17; CHECK-LABEL: llrint_v1i64_v2f16:
18; CHECK:       // %bb.0:
19; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
20; CHECK-NEXT:    mov h1, v0.h[1]
21; CHECK-NEXT:    frintx h0, h0
22; CHECK-NEXT:    frintx h1, h1
23; CHECK-NEXT:    fcvtzs x8, h0
24; CHECK-NEXT:    fcvtzs x9, h1
25; CHECK-NEXT:    fmov d0, x8
26; CHECK-NEXT:    mov v0.d[1], x9
27; CHECK-NEXT:    ret
28  %a = call <2 x i64> @llvm.llrint.v2i64.v2f16(<2 x half> %x)
29  ret <2 x i64> %a
30}
31declare <2 x i64> @llvm.llrint.v2i64.v2f16(<2 x half>)
32
33define <4 x i64> @llrint_v4i64_v4f16(<4 x half> %x) {
34; CHECK-LABEL: llrint_v4i64_v4f16:
35; CHECK:       // %bb.0:
36; CHECK-NEXT:    frintx v0.4h, v0.4h
37; CHECK-NEXT:    mov h1, v0.h[2]
38; CHECK-NEXT:    mov h2, v0.h[3]
39; CHECK-NEXT:    mov h3, v0.h[1]
40; CHECK-NEXT:    fcvtzs x9, h0
41; CHECK-NEXT:    fcvtzs x8, h1
42; CHECK-NEXT:    fcvtzs x10, h2
43; CHECK-NEXT:    fcvtzs x11, h3
44; CHECK-NEXT:    fmov d0, x9
45; CHECK-NEXT:    fmov d1, x8
46; CHECK-NEXT:    mov v0.d[1], x11
47; CHECK-NEXT:    mov v1.d[1], x10
48; CHECK-NEXT:    ret
49  %a = call <4 x i64> @llvm.llrint.v4i64.v4f16(<4 x half> %x)
50  ret <4 x i64> %a
51}
52declare <4 x i64> @llvm.llrint.v4i64.v4f16(<4 x half>)
53
54define <8 x i64> @llrint_v8i64_v8f16(<8 x half> %x) {
55; CHECK-LABEL: llrint_v8i64_v8f16:
56; CHECK:       // %bb.0:
57; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
58; CHECK-NEXT:    frintx v0.4h, v0.4h
59; CHECK-NEXT:    frintx v1.4h, v1.4h
60; CHECK-NEXT:    mov h4, v0.h[2]
61; CHECK-NEXT:    mov h2, v0.h[1]
62; CHECK-NEXT:    mov h7, v0.h[3]
63; CHECK-NEXT:    fcvtzs x8, h0
64; CHECK-NEXT:    mov h3, v1.h[2]
65; CHECK-NEXT:    mov h5, v1.h[3]
66; CHECK-NEXT:    mov h6, v1.h[1]
67; CHECK-NEXT:    fcvtzs x11, h1
68; CHECK-NEXT:    fcvtzs x12, h4
69; CHECK-NEXT:    fcvtzs x9, h2
70; CHECK-NEXT:    fcvtzs x15, h7
71; CHECK-NEXT:    fmov d0, x8
72; CHECK-NEXT:    fcvtzs x10, h3
73; CHECK-NEXT:    fcvtzs x13, h5
74; CHECK-NEXT:    fcvtzs x14, h6
75; CHECK-NEXT:    fmov d1, x12
76; CHECK-NEXT:    fmov d2, x11
77; CHECK-NEXT:    mov v0.d[1], x9
78; CHECK-NEXT:    fmov d3, x10
79; CHECK-NEXT:    mov v1.d[1], x15
80; CHECK-NEXT:    mov v2.d[1], x14
81; CHECK-NEXT:    mov v3.d[1], x13
82; CHECK-NEXT:    ret
83  %a = call <8 x i64> @llvm.llrint.v8i64.v8f16(<8 x half> %x)
84  ret <8 x i64> %a
85}
86declare <8 x i64> @llvm.llrint.v8i64.v8f16(<8 x half>)
87
88define <16 x i64> @llrint_v16i64_v16f16(<16 x half> %x) {
89; CHECK-LABEL: llrint_v16i64_v16f16:
90; CHECK:       // %bb.0:
91; CHECK-NEXT:    ext v2.16b, v1.16b, v1.16b, #8
92; CHECK-NEXT:    frintx v1.4h, v1.4h
93; CHECK-NEXT:    frintx v3.4h, v0.4h
94; CHECK-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
95; CHECK-NEXT:    frintx v2.4h, v2.4h
96; CHECK-NEXT:    mov h4, v1.h[2]
97; CHECK-NEXT:    mov h5, v3.h[2]
98; CHECK-NEXT:    frintx v0.4h, v0.4h
99; CHECK-NEXT:    mov h6, v3.h[1]
100; CHECK-NEXT:    fcvtzs x9, h3
101; CHECK-NEXT:    mov h16, v1.h[1]
102; CHECK-NEXT:    fcvtzs x12, h1
103; CHECK-NEXT:    mov h3, v3.h[3]
104; CHECK-NEXT:    mov h17, v1.h[3]
105; CHECK-NEXT:    mov h7, v2.h[3]
106; CHECK-NEXT:    fcvtzs x8, h4
107; CHECK-NEXT:    fcvtzs x10, h5
108; CHECK-NEXT:    mov h4, v2.h[2]
109; CHECK-NEXT:    mov h5, v0.h[2]
110; CHECK-NEXT:    fcvtzs x11, h6
111; CHECK-NEXT:    mov h6, v0.h[3]
112; CHECK-NEXT:    fcvtzs x15, h2
113; CHECK-NEXT:    mov h2, v2.h[1]
114; CHECK-NEXT:    fcvtzs x14, h0
115; CHECK-NEXT:    fcvtzs x17, h3
116; CHECK-NEXT:    fcvtzs x0, h17
117; CHECK-NEXT:    fcvtzs x13, h7
118; CHECK-NEXT:    mov h7, v0.h[1]
119; CHECK-NEXT:    fmov d0, x9
120; CHECK-NEXT:    fcvtzs x16, h4
121; CHECK-NEXT:    fcvtzs x9, h5
122; CHECK-NEXT:    fmov d4, x12
123; CHECK-NEXT:    fcvtzs x12, h16
124; CHECK-NEXT:    fmov d1, x10
125; CHECK-NEXT:    fcvtzs x10, h6
126; CHECK-NEXT:    fmov d5, x8
127; CHECK-NEXT:    fcvtzs x8, h2
128; CHECK-NEXT:    fmov d2, x14
129; CHECK-NEXT:    fcvtzs x18, h7
130; CHECK-NEXT:    fmov d6, x15
131; CHECK-NEXT:    mov v0.d[1], x11
132; CHECK-NEXT:    fmov d3, x9
133; CHECK-NEXT:    fmov d7, x16
134; CHECK-NEXT:    mov v1.d[1], x17
135; CHECK-NEXT:    mov v4.d[1], x12
136; CHECK-NEXT:    mov v5.d[1], x0
137; CHECK-NEXT:    mov v6.d[1], x8
138; CHECK-NEXT:    mov v2.d[1], x18
139; CHECK-NEXT:    mov v3.d[1], x10
140; CHECK-NEXT:    mov v7.d[1], x13
141; CHECK-NEXT:    ret
142  %a = call <16 x i64> @llvm.llrint.v16i64.v16f16(<16 x half> %x)
143  ret <16 x i64> %a
144}
145declare <16 x i64> @llvm.llrint.v16i64.v16f16(<16 x half>)
146
147define <32 x i64> @llrint_v32i64_v32f16(<32 x half> %x) {
148; CHECK-LABEL: llrint_v32i64_v32f16:
149; CHECK:       // %bb.0:
150; CHECK-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
151; CHECK-NEXT:    sub x9, sp, #272
152; CHECK-NEXT:    mov x29, sp
153; CHECK-NEXT:    and sp, x9, #0xffffffffffffffe0
154; CHECK-NEXT:    .cfi_def_cfa w29, 16
155; CHECK-NEXT:    .cfi_offset w30, -8
156; CHECK-NEXT:    .cfi_offset w29, -16
157; CHECK-NEXT:    frintx v5.4h, v0.4h
158; CHECK-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
159; CHECK-NEXT:    ext v4.16b, v1.16b, v1.16b, #8
160; CHECK-NEXT:    ext v17.16b, v2.16b, v2.16b, #8
161; CHECK-NEXT:    frintx v1.4h, v1.4h
162; CHECK-NEXT:    frintx v2.4h, v2.4h
163; CHECK-NEXT:    ptrue p0.d, vl4
164; CHECK-NEXT:    mov h6, v5.h[3]
165; CHECK-NEXT:    frintx v0.4h, v0.4h
166; CHECK-NEXT:    mov h7, v5.h[2]
167; CHECK-NEXT:    mov h16, v5.h[1]
168; CHECK-NEXT:    frintx v4.4h, v4.4h
169; CHECK-NEXT:    fcvtzs x12, h5
170; CHECK-NEXT:    ext v5.16b, v3.16b, v3.16b, #8
171; CHECK-NEXT:    frintx v17.4h, v17.4h
172; CHECK-NEXT:    frintx v3.4h, v3.4h
173; CHECK-NEXT:    fcvtzs x9, h6
174; CHECK-NEXT:    mov h6, v0.h[3]
175; CHECK-NEXT:    fcvtzs x10, h7
176; CHECK-NEXT:    mov h7, v0.h[2]
177; CHECK-NEXT:    fcvtzs x11, h16
178; CHECK-NEXT:    mov h16, v0.h[1]
179; CHECK-NEXT:    fcvtzs x13, h6
180; CHECK-NEXT:    mov h6, v4.h[3]
181; CHECK-NEXT:    stp x10, x9, [sp, #48]
182; CHECK-NEXT:    fcvtzs x9, h7
183; CHECK-NEXT:    mov h7, v4.h[2]
184; CHECK-NEXT:    fcvtzs x10, h16
185; CHECK-NEXT:    mov h16, v4.h[1]
186; CHECK-NEXT:    stp x12, x11, [sp, #32]
187; CHECK-NEXT:    fcvtzs x11, h0
188; CHECK-NEXT:    frintx v0.4h, v5.4h
189; CHECK-NEXT:    mov h5, v17.h[3]
190; CHECK-NEXT:    fcvtzs x12, h6
191; CHECK-NEXT:    mov h6, v17.h[2]
192; CHECK-NEXT:    stp x9, x13, [sp, #16]
193; CHECK-NEXT:    fcvtzs x13, h7
194; CHECK-NEXT:    mov h7, v17.h[1]
195; CHECK-NEXT:    fcvtzs x9, h16
196; CHECK-NEXT:    stp x11, x10, [sp]
197; CHECK-NEXT:    fcvtzs x10, h4
198; CHECK-NEXT:    fcvtzs x11, h5
199; CHECK-NEXT:    mov h4, v0.h[3]
200; CHECK-NEXT:    mov h5, v0.h[2]
201; CHECK-NEXT:    stp x13, x12, [sp, #80]
202; CHECK-NEXT:    fcvtzs x12, h6
203; CHECK-NEXT:    fcvtzs x13, h7
204; CHECK-NEXT:    mov h6, v0.h[1]
205; CHECK-NEXT:    stp x10, x9, [sp, #64]
206; CHECK-NEXT:    fcvtzs x9, h17
207; CHECK-NEXT:    mov h7, v1.h[3]
208; CHECK-NEXT:    fcvtzs x10, h4
209; CHECK-NEXT:    mov h4, v1.h[2]
210; CHECK-NEXT:    stp x12, x11, [sp, #144]
211; CHECK-NEXT:    fcvtzs x11, h5
212; CHECK-NEXT:    mov h5, v1.h[1]
213; CHECK-NEXT:    fcvtzs x12, h6
214; CHECK-NEXT:    stp x9, x13, [sp, #128]
215; CHECK-NEXT:    fcvtzs x9, h0
216; CHECK-NEXT:    fcvtzs x13, h7
217; CHECK-NEXT:    mov h0, v2.h[3]
218; CHECK-NEXT:    stp x11, x10, [sp, #208]
219; CHECK-NEXT:    fcvtzs x10, h4
220; CHECK-NEXT:    mov h4, v2.h[2]
221; CHECK-NEXT:    fcvtzs x11, h5
222; CHECK-NEXT:    mov h5, v2.h[1]
223; CHECK-NEXT:    stp x9, x12, [sp, #192]
224; CHECK-NEXT:    fcvtzs x9, h1
225; CHECK-NEXT:    fcvtzs x12, h0
226; CHECK-NEXT:    mov h0, v3.h[3]
227; CHECK-NEXT:    mov h1, v3.h[2]
228; CHECK-NEXT:    stp x10, x13, [sp, #112]
229; CHECK-NEXT:    fcvtzs x10, h4
230; CHECK-NEXT:    mov h4, v3.h[1]
231; CHECK-NEXT:    fcvtzs x13, h5
232; CHECK-NEXT:    stp x9, x11, [sp, #96]
233; CHECK-NEXT:    fcvtzs x9, h2
234; CHECK-NEXT:    fcvtzs x11, h0
235; CHECK-NEXT:    stp x10, x12, [sp, #176]
236; CHECK-NEXT:    fcvtzs x10, h1
237; CHECK-NEXT:    fcvtzs x12, h4
238; CHECK-NEXT:    stp x9, x13, [sp, #160]
239; CHECK-NEXT:    fcvtzs x9, h3
240; CHECK-NEXT:    stp x10, x11, [sp, #240]
241; CHECK-NEXT:    add x10, sp, #64
242; CHECK-NEXT:    stp x9, x12, [sp, #224]
243; CHECK-NEXT:    add x9, sp, #32
244; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x9]
245; CHECK-NEXT:    mov x9, sp
246; CHECK-NEXT:    ld1d { z2.d }, p0/z, [x10]
247; CHECK-NEXT:    ld1d { z1.d }, p0/z, [x9]
248; CHECK-NEXT:    add x9, sp, #224
249; CHECK-NEXT:    add x10, sp, #128
250; CHECK-NEXT:    ld1d { z3.d }, p0/z, [x9]
251; CHECK-NEXT:    add x9, sp, #160
252; CHECK-NEXT:    ld1d { z4.d }, p0/z, [x10]
253; CHECK-NEXT:    add x10, sp, #96
254; CHECK-NEXT:    ld1d { z5.d }, p0/z, [x9]
255; CHECK-NEXT:    add x9, sp, #192
256; CHECK-NEXT:    ld1d { z6.d }, p0/z, [x10]
257; CHECK-NEXT:    mov x10, #24 // =0x18
258; CHECK-NEXT:    ld1d { z7.d }, p0/z, [x9]
259; CHECK-NEXT:    mov x9, #16 // =0x10
260; CHECK-NEXT:    st1d { z3.d }, p0, [x8, x10, lsl #3]
261; CHECK-NEXT:    st1d { z5.d }, p0, [x8, x9, lsl #3]
262; CHECK-NEXT:    mov x9, #8 // =0x8
263; CHECK-NEXT:    st1d { z6.d }, p0, [x8, x9, lsl #3]
264; CHECK-NEXT:    mov x9, #28 // =0x1c
265; CHECK-NEXT:    st1d { z7.d }, p0, [x8, x9, lsl #3]
266; CHECK-NEXT:    mov x9, #20 // =0x14
267; CHECK-NEXT:    st1d { z4.d }, p0, [x8, x9, lsl #3]
268; CHECK-NEXT:    mov x9, #12 // =0xc
269; CHECK-NEXT:    st1d { z2.d }, p0, [x8, x9, lsl #3]
270; CHECK-NEXT:    mov x9, #4 // =0x4
271; CHECK-NEXT:    st1d { z1.d }, p0, [x8, x9, lsl #3]
272; CHECK-NEXT:    st1d { z0.d }, p0, [x8]
273; CHECK-NEXT:    mov sp, x29
274; CHECK-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload
275; CHECK-NEXT:    ret
276  %a = call <32 x i64> @llvm.llrint.v32i64.v32f16(<32 x half> %x)
277  ret <32 x i64> %a
278}
279declare <32 x i64> @llvm.llrint.v32i64.v32f16(<32 x half>)
280
281define <1 x i64> @llrint_v1i64_v1f32(<1 x float> %x) {
282; CHECK-LABEL: llrint_v1i64_v1f32:
283; CHECK:       // %bb.0:
284; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
285; CHECK-NEXT:    frintx s0, s0
286; CHECK-NEXT:    fcvtzs x8, s0
287; CHECK-NEXT:    fmov d0, x8
288; CHECK-NEXT:    ret
289  %a = call <1 x i64> @llvm.llrint.v1i64.v1f32(<1 x float> %x)
290  ret <1 x i64> %a
291}
292declare <1 x i64> @llvm.llrint.v1i64.v1f32(<1 x float>)
293
294define <2 x i64> @llrint_v2i64_v2f32(<2 x float> %x) {
295; CHECK-LABEL: llrint_v2i64_v2f32:
296; CHECK:       // %bb.0:
297; CHECK-NEXT:    frintx v0.2s, v0.2s
298; CHECK-NEXT:    fcvtl v0.2d, v0.2s
299; CHECK-NEXT:    fcvtzs v0.2d, v0.2d
300; CHECK-NEXT:    ret
301  %a = call <2 x i64> @llvm.llrint.v2i64.v2f32(<2 x float> %x)
302  ret <2 x i64> %a
303}
304declare <2 x i64> @llvm.llrint.v2i64.v2f32(<2 x float>)
305
306define <4 x i64> @llrint_v4i64_v4f32(<4 x float> %x) {
307; CHECK-LABEL: llrint_v4i64_v4f32:
308; CHECK:       // %bb.0:
309; CHECK-NEXT:    frintx v0.4s, v0.4s
310; CHECK-NEXT:    mov s1, v0.s[2]
311; CHECK-NEXT:    mov s2, v0.s[3]
312; CHECK-NEXT:    mov s3, v0.s[1]
313; CHECK-NEXT:    fcvtzs x9, s0
314; CHECK-NEXT:    fcvtzs x8, s1
315; CHECK-NEXT:    fcvtzs x10, s2
316; CHECK-NEXT:    fcvtzs x11, s3
317; CHECK-NEXT:    fmov d0, x9
318; CHECK-NEXT:    fmov d1, x8
319; CHECK-NEXT:    mov v0.d[1], x11
320; CHECK-NEXT:    mov v1.d[1], x10
321; CHECK-NEXT:    ret
322  %a = call <4 x i64> @llvm.llrint.v4i64.v4f32(<4 x float> %x)
323  ret <4 x i64> %a
324}
325declare <4 x i64> @llvm.llrint.v4i64.v4f32(<4 x float>)
326
327define <8 x i64> @llrint_v8i64_v8f32(<8 x float> %x) {
328; CHECK-LABEL: llrint_v8i64_v8f32:
329; CHECK:       // %bb.0:
330; CHECK-NEXT:    frintx v0.4s, v0.4s
331; CHECK-NEXT:    frintx v1.4s, v1.4s
332; CHECK-NEXT:    mov s3, v1.s[2]
333; CHECK-NEXT:    mov s4, v0.s[2]
334; CHECK-NEXT:    mov s2, v0.s[1]
335; CHECK-NEXT:    mov s5, v1.s[3]
336; CHECK-NEXT:    mov s6, v1.s[1]
337; CHECK-NEXT:    mov s7, v0.s[3]
338; CHECK-NEXT:    fcvtzs x8, s0
339; CHECK-NEXT:    fcvtzs x10, s1
340; CHECK-NEXT:    fcvtzs x11, s3
341; CHECK-NEXT:    fcvtzs x12, s4
342; CHECK-NEXT:    fcvtzs x9, s2
343; CHECK-NEXT:    fcvtzs x13, s5
344; CHECK-NEXT:    fcvtzs x14, s6
345; CHECK-NEXT:    fcvtzs x15, s7
346; CHECK-NEXT:    fmov d0, x8
347; CHECK-NEXT:    fmov d2, x10
348; CHECK-NEXT:    fmov d1, x12
349; CHECK-NEXT:    fmov d3, x11
350; CHECK-NEXT:    mov v0.d[1], x9
351; CHECK-NEXT:    mov v2.d[1], x14
352; CHECK-NEXT:    mov v1.d[1], x15
353; CHECK-NEXT:    mov v3.d[1], x13
354; CHECK-NEXT:    ret
355  %a = call <8 x i64> @llvm.llrint.v8i64.v8f32(<8 x float> %x)
356  ret <8 x i64> %a
357}
358declare <8 x i64> @llvm.llrint.v8i64.v8f32(<8 x float>)
359
360define <16 x i64> @llrint_v16i64_v16f32(<16 x float> %x) {
361; CHECK-LABEL: llrint_v16i64_v16f32:
362; CHECK:       // %bb.0:
363; CHECK-NEXT:    frintx v3.4s, v3.4s
364; CHECK-NEXT:    frintx v2.4s, v2.4s
365; CHECK-NEXT:    frintx v1.4s, v1.4s
366; CHECK-NEXT:    frintx v0.4s, v0.4s
367; CHECK-NEXT:    mov s4, v3.s[2]
368; CHECK-NEXT:    mov s5, v2.s[2]
369; CHECK-NEXT:    mov s6, v1.s[2]
370; CHECK-NEXT:    mov s7, v0.s[2]
371; CHECK-NEXT:    fcvtzs x10, s1
372; CHECK-NEXT:    fcvtzs x11, s0
373; CHECK-NEXT:    mov s16, v0.s[1]
374; CHECK-NEXT:    mov s17, v1.s[1]
375; CHECK-NEXT:    mov s18, v3.s[1]
376; CHECK-NEXT:    fcvtzs x14, s3
377; CHECK-NEXT:    fcvtzs x16, s2
378; CHECK-NEXT:    fcvtzs x8, s4
379; CHECK-NEXT:    mov s4, v2.s[1]
380; CHECK-NEXT:    fcvtzs x9, s5
381; CHECK-NEXT:    mov s5, v1.s[3]
382; CHECK-NEXT:    fcvtzs x12, s6
383; CHECK-NEXT:    mov s6, v0.s[3]
384; CHECK-NEXT:    fcvtzs x13, s7
385; CHECK-NEXT:    mov s7, v3.s[3]
386; CHECK-NEXT:    fmov d0, x11
387; CHECK-NEXT:    fcvtzs x17, s16
388; CHECK-NEXT:    fcvtzs x18, s18
389; CHECK-NEXT:    fcvtzs x15, s4
390; CHECK-NEXT:    mov s4, v2.s[3]
391; CHECK-NEXT:    fmov d2, x10
392; CHECK-NEXT:    fcvtzs x11, s5
393; CHECK-NEXT:    fcvtzs x10, s6
394; CHECK-NEXT:    fmov d3, x12
395; CHECK-NEXT:    fmov d1, x13
396; CHECK-NEXT:    fcvtzs x12, s17
397; CHECK-NEXT:    fcvtzs x13, s7
398; CHECK-NEXT:    fmov d5, x9
399; CHECK-NEXT:    fmov d6, x14
400; CHECK-NEXT:    fmov d7, x8
401; CHECK-NEXT:    fcvtzs x0, s4
402; CHECK-NEXT:    fmov d4, x16
403; CHECK-NEXT:    mov v0.d[1], x17
404; CHECK-NEXT:    mov v1.d[1], x10
405; CHECK-NEXT:    mov v3.d[1], x11
406; CHECK-NEXT:    mov v2.d[1], x12
407; CHECK-NEXT:    mov v6.d[1], x18
408; CHECK-NEXT:    mov v7.d[1], x13
409; CHECK-NEXT:    mov v4.d[1], x15
410; CHECK-NEXT:    mov v5.d[1], x0
411; CHECK-NEXT:    ret
412  %a = call <16 x i64> @llvm.llrint.v16i64.v16f32(<16 x float> %x)
413  ret <16 x i64> %a
414}
415declare <16 x i64> @llvm.llrint.v16i64.v16f32(<16 x float>)
416
417define <32 x i64> @llrint_v32i64_v32f32(<32 x float> %x) {
418; CHECK-LABEL: llrint_v32i64_v32f32:
419; CHECK:       // %bb.0:
420; CHECK-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
421; CHECK-NEXT:    sub x9, sp, #272
422; CHECK-NEXT:    mov x29, sp
423; CHECK-NEXT:    and sp, x9, #0xffffffffffffffe0
424; CHECK-NEXT:    .cfi_def_cfa w29, 16
425; CHECK-NEXT:    .cfi_offset w30, -8
426; CHECK-NEXT:    .cfi_offset w29, -16
427; CHECK-NEXT:    frintx v0.4s, v0.4s
428; CHECK-NEXT:    frintx v1.4s, v1.4s
429; CHECK-NEXT:    frintx v2.4s, v2.4s
430; CHECK-NEXT:    ptrue p0.d, vl4
431; CHECK-NEXT:    mov s16, v0.s[3]
432; CHECK-NEXT:    mov s17, v0.s[2]
433; CHECK-NEXT:    mov s18, v0.s[1]
434; CHECK-NEXT:    fcvtzs x12, s0
435; CHECK-NEXT:    frintx v0.4s, v3.4s
436; CHECK-NEXT:    mov s3, v2.s[3]
437; CHECK-NEXT:    fcvtzs x9, s16
438; CHECK-NEXT:    mov s16, v1.s[3]
439; CHECK-NEXT:    fcvtzs x10, s17
440; CHECK-NEXT:    mov s17, v1.s[2]
441; CHECK-NEXT:    fcvtzs x11, s18
442; CHECK-NEXT:    mov s18, v1.s[1]
443; CHECK-NEXT:    fcvtzs x13, s16
444; CHECK-NEXT:    stp x10, x9, [sp, #16]
445; CHECK-NEXT:    mov s16, v2.s[2]
446; CHECK-NEXT:    fcvtzs x9, s17
447; CHECK-NEXT:    fcvtzs x10, s18
448; CHECK-NEXT:    mov s17, v2.s[1]
449; CHECK-NEXT:    stp x12, x11, [sp]
450; CHECK-NEXT:    fcvtzs x11, s1
451; CHECK-NEXT:    frintx v1.4s, v4.4s
452; CHECK-NEXT:    fcvtzs x12, s3
453; CHECK-NEXT:    mov s3, v0.s[3]
454; CHECK-NEXT:    mov s4, v0.s[2]
455; CHECK-NEXT:    stp x9, x13, [sp, #48]
456; CHECK-NEXT:    fcvtzs x13, s16
457; CHECK-NEXT:    fcvtzs x9, s17
458; CHECK-NEXT:    mov s16, v0.s[1]
459; CHECK-NEXT:    stp x11, x10, [sp, #32]
460; CHECK-NEXT:    fcvtzs x10, s2
461; CHECK-NEXT:    frintx v2.4s, v5.4s
462; CHECK-NEXT:    fcvtzs x11, s3
463; CHECK-NEXT:    mov s3, v1.s[3]
464; CHECK-NEXT:    mov s5, v1.s[1]
465; CHECK-NEXT:    stp x13, x12, [sp, #80]
466; CHECK-NEXT:    fcvtzs x12, s4
467; CHECK-NEXT:    mov s4, v1.s[2]
468; CHECK-NEXT:    fcvtzs x13, s16
469; CHECK-NEXT:    stp x10, x9, [sp, #64]
470; CHECK-NEXT:    fcvtzs x9, s0
471; CHECK-NEXT:    mov s0, v2.s[3]
472; CHECK-NEXT:    fcvtzs x10, s3
473; CHECK-NEXT:    frintx v3.4s, v6.4s
474; CHECK-NEXT:    stp x12, x11, [sp, #112]
475; CHECK-NEXT:    fcvtzs x11, s4
476; CHECK-NEXT:    mov s4, v2.s[2]
477; CHECK-NEXT:    fcvtzs x12, s5
478; CHECK-NEXT:    mov s5, v2.s[1]
479; CHECK-NEXT:    stp x9, x13, [sp, #96]
480; CHECK-NEXT:    fcvtzs x9, s1
481; CHECK-NEXT:    fcvtzs x13, s0
482; CHECK-NEXT:    mov s0, v3.s[3]
483; CHECK-NEXT:    frintx v1.4s, v7.4s
484; CHECK-NEXT:    stp x11, x10, [sp, #144]
485; CHECK-NEXT:    fcvtzs x10, s4
486; CHECK-NEXT:    mov s4, v3.s[2]
487; CHECK-NEXT:    fcvtzs x11, s5
488; CHECK-NEXT:    mov s5, v3.s[1]
489; CHECK-NEXT:    stp x9, x12, [sp, #128]
490; CHECK-NEXT:    fcvtzs x9, s2
491; CHECK-NEXT:    fcvtzs x12, s0
492; CHECK-NEXT:    mov s0, v1.s[3]
493; CHECK-NEXT:    mov s2, v1.s[2]
494; CHECK-NEXT:    stp x10, x13, [sp, #176]
495; CHECK-NEXT:    fcvtzs x10, s4
496; CHECK-NEXT:    mov s4, v1.s[1]
497; CHECK-NEXT:    fcvtzs x13, s5
498; CHECK-NEXT:    stp x9, x11, [sp, #160]
499; CHECK-NEXT:    fcvtzs x9, s3
500; CHECK-NEXT:    fcvtzs x11, s0
501; CHECK-NEXT:    stp x10, x12, [sp, #208]
502; CHECK-NEXT:    fcvtzs x10, s2
503; CHECK-NEXT:    fcvtzs x12, s4
504; CHECK-NEXT:    stp x9, x13, [sp, #192]
505; CHECK-NEXT:    fcvtzs x9, s1
506; CHECK-NEXT:    stp x10, x11, [sp, #240]
507; CHECK-NEXT:    add x10, sp, #64
508; CHECK-NEXT:    stp x9, x12, [sp, #224]
509; CHECK-NEXT:    mov x9, sp
510; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x9]
511; CHECK-NEXT:    add x9, sp, #32
512; CHECK-NEXT:    ld1d { z2.d }, p0/z, [x10]
513; CHECK-NEXT:    ld1d { z1.d }, p0/z, [x9]
514; CHECK-NEXT:    add x9, sp, #224
515; CHECK-NEXT:    add x10, sp, #96
516; CHECK-NEXT:    ld1d { z3.d }, p0/z, [x9]
517; CHECK-NEXT:    add x9, sp, #192
518; CHECK-NEXT:    ld1d { z4.d }, p0/z, [x10]
519; CHECK-NEXT:    add x10, sp, #160
520; CHECK-NEXT:    ld1d { z5.d }, p0/z, [x9]
521; CHECK-NEXT:    add x9, sp, #128
522; CHECK-NEXT:    ld1d { z6.d }, p0/z, [x10]
523; CHECK-NEXT:    mov x10, #28 // =0x1c
524; CHECK-NEXT:    ld1d { z7.d }, p0/z, [x9]
525; CHECK-NEXT:    mov x9, #24 // =0x18
526; CHECK-NEXT:    st1d { z3.d }, p0, [x8, x10, lsl #3]
527; CHECK-NEXT:    st1d { z5.d }, p0, [x8, x9, lsl #3]
528; CHECK-NEXT:    mov x9, #20 // =0x14
529; CHECK-NEXT:    st1d { z6.d }, p0, [x8, x9, lsl #3]
530; CHECK-NEXT:    mov x9, #16 // =0x10
531; CHECK-NEXT:    st1d { z7.d }, p0, [x8, x9, lsl #3]
532; CHECK-NEXT:    mov x9, #12 // =0xc
533; CHECK-NEXT:    st1d { z4.d }, p0, [x8, x9, lsl #3]
534; CHECK-NEXT:    mov x9, #8 // =0x8
535; CHECK-NEXT:    st1d { z2.d }, p0, [x8, x9, lsl #3]
536; CHECK-NEXT:    mov x9, #4 // =0x4
537; CHECK-NEXT:    st1d { z1.d }, p0, [x8, x9, lsl #3]
538; CHECK-NEXT:    st1d { z0.d }, p0, [x8]
539; CHECK-NEXT:    mov sp, x29
540; CHECK-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload
541; CHECK-NEXT:    ret
542  %a = call <32 x i64> @llvm.llrint.v32i64.v32f32(<32 x float> %x)
543  ret <32 x i64> %a
544}
545declare <32 x i64> @llvm.llrint.v32i64.v32f32(<32 x float>)
546
547define <1 x i64> @llrint_v1i64_v1f64(<1 x double> %x) {
548; CHECK-LABEL: llrint_v1i64_v1f64:
549; CHECK:       // %bb.0:
550; CHECK-NEXT:    frintx d0, d0
551; CHECK-NEXT:    fcvtzs x8, d0
552; CHECK-NEXT:    fmov d0, x8
553; CHECK-NEXT:    ret
554  %a = call <1 x i64> @llvm.llrint.v1i64.v1f64(<1 x double> %x)
555  ret <1 x i64> %a
556}
557declare <1 x i64> @llvm.llrint.v1i64.v1f64(<1 x double>)
558
559define <2 x i64> @llrint_v2i64_v2f64(<2 x double> %x) {
560; CHECK-LABEL: llrint_v2i64_v2f64:
561; CHECK:       // %bb.0:
562; CHECK-NEXT:    frintx v0.2d, v0.2d
563; CHECK-NEXT:    fcvtzs v0.2d, v0.2d
564; CHECK-NEXT:    ret
565  %a = call <2 x i64> @llvm.llrint.v2i64.v2f64(<2 x double> %x)
566  ret <2 x i64> %a
567}
568declare <2 x i64> @llvm.llrint.v2i64.v2f64(<2 x double>)
569
570define <4 x i64> @llrint_v4i64_v4f64(<4 x double> %x) {
571; CHECK-LABEL: llrint_v4i64_v4f64:
572; CHECK:       // %bb.0:
573; CHECK-NEXT:    ptrue p0.d, vl2
574; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
575; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
576; CHECK-NEXT:    splice z0.d, p0, z0.d, z1.d
577; CHECK-NEXT:    ptrue p0.d, vl4
578; CHECK-NEXT:    frintx z0.d, p0/m, z0.d
579; CHECK-NEXT:    mov z1.d, z0.d[2]
580; CHECK-NEXT:    mov z2.d, z0.d[3]
581; CHECK-NEXT:    mov z3.d, z0.d[1]
582; CHECK-NEXT:    fcvtzs x9, d0
583; CHECK-NEXT:    fcvtzs x8, d1
584; CHECK-NEXT:    fcvtzs x10, d2
585; CHECK-NEXT:    fcvtzs x11, d3
586; CHECK-NEXT:    fmov d0, x9
587; CHECK-NEXT:    fmov d1, x8
588; CHECK-NEXT:    mov v0.d[1], x11
589; CHECK-NEXT:    mov v1.d[1], x10
590; CHECK-NEXT:    ret
591  %a = call <4 x i64> @llvm.llrint.v4i64.v4f64(<4 x double> %x)
592  ret <4 x i64> %a
593}
594declare <4 x i64> @llvm.llrint.v4i64.v4f64(<4 x double>)
595
596define <8 x i64> @llrint_v8i64_v8f64(<8 x double> %x) {
597; CHECK-LABEL: llrint_v8i64_v8f64:
598; CHECK:       // %bb.0:
599; CHECK-NEXT:    ptrue p0.d, vl2
600; CHECK-NEXT:    // kill: def $q2 killed $q2 def $z2
601; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
602; CHECK-NEXT:    // kill: def $q3 killed $q3 def $z3
603; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
604; CHECK-NEXT:    splice z0.d, p0, z0.d, z1.d
605; CHECK-NEXT:    splice z2.d, p0, z2.d, z3.d
606; CHECK-NEXT:    ptrue p0.d, vl4
607; CHECK-NEXT:    frintx z0.d, p0/m, z0.d
608; CHECK-NEXT:    movprfx z1, z2
609; CHECK-NEXT:    frintx z1.d, p0/m, z2.d
610; CHECK-NEXT:    mov z4.d, z1.d[2]
611; CHECK-NEXT:    mov z5.d, z0.d[2]
612; CHECK-NEXT:    mov z2.d, z0.d[1]
613; CHECK-NEXT:    mov z3.d, z1.d[3]
614; CHECK-NEXT:    mov z6.d, z0.d[3]
615; CHECK-NEXT:    fcvtzs x8, d0
616; CHECK-NEXT:    mov z0.d, z1.d[1]
617; CHECK-NEXT:    fcvtzs x10, d1
618; CHECK-NEXT:    fcvtzs x11, d4
619; CHECK-NEXT:    fcvtzs x12, d5
620; CHECK-NEXT:    fcvtzs x9, d2
621; CHECK-NEXT:    fcvtzs x13, d3
622; CHECK-NEXT:    fcvtzs x14, d6
623; CHECK-NEXT:    fcvtzs x15, d0
624; CHECK-NEXT:    fmov d0, x8
625; CHECK-NEXT:    fmov d2, x10
626; CHECK-NEXT:    fmov d1, x12
627; CHECK-NEXT:    fmov d3, x11
628; CHECK-NEXT:    mov v0.d[1], x9
629; CHECK-NEXT:    mov v2.d[1], x15
630; CHECK-NEXT:    mov v1.d[1], x14
631; CHECK-NEXT:    mov v3.d[1], x13
632; CHECK-NEXT:    ret
633  %a = call <8 x i64> @llvm.llrint.v8i64.v8f64(<8 x double> %x)
634  ret <8 x i64> %a
635}
636declare <8 x i64> @llvm.llrint.v8i64.v8f64(<8 x double>)
637
638define <16 x i64> @llrint_v16f64(<16 x double> %x) {
639; CHECK-LABEL: llrint_v16f64:
640; CHECK:       // %bb.0:
641; CHECK-NEXT:    ptrue p1.d, vl2
642; CHECK-NEXT:    // kill: def $q6 killed $q6 def $z6
643; CHECK-NEXT:    // kill: def $q4 killed $q4 def $z4
644; CHECK-NEXT:    // kill: def $q7 killed $q7 def $z7
645; CHECK-NEXT:    // kill: def $q5 killed $q5 def $z5
646; CHECK-NEXT:    // kill: def $q2 killed $q2 def $z2
647; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
648; CHECK-NEXT:    // kill: def $q3 killed $q3 def $z3
649; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
650; CHECK-NEXT:    ptrue p0.d, vl4
651; CHECK-NEXT:    splice z6.d, p1, z6.d, z7.d
652; CHECK-NEXT:    splice z4.d, p1, z4.d, z5.d
653; CHECK-NEXT:    splice z2.d, p1, z2.d, z3.d
654; CHECK-NEXT:    splice z0.d, p1, z0.d, z1.d
655; CHECK-NEXT:    movprfx z3, z6
656; CHECK-NEXT:    frintx z3.d, p0/m, z6.d
657; CHECK-NEXT:    movprfx z1, z4
658; CHECK-NEXT:    frintx z1.d, p0/m, z4.d
659; CHECK-NEXT:    frintx z2.d, p0/m, z2.d
660; CHECK-NEXT:    frintx z0.d, p0/m, z0.d
661; CHECK-NEXT:    mov z4.d, z3.d[2]
662; CHECK-NEXT:    mov z5.d, z1.d[2]
663; CHECK-NEXT:    mov z6.d, z2.d[3]
664; CHECK-NEXT:    fcvtzs x11, d0
665; CHECK-NEXT:    fcvtzs x12, d1
666; CHECK-NEXT:    fcvtzs x13, d2
667; CHECK-NEXT:    fcvtzs x14, d3
668; CHECK-NEXT:    mov z7.d, z3.d[3]
669; CHECK-NEXT:    mov z16.d, z1.d[3]
670; CHECK-NEXT:    fcvtzs x9, d4
671; CHECK-NEXT:    fcvtzs x10, d5
672; CHECK-NEXT:    mov z4.d, z2.d[2]
673; CHECK-NEXT:    mov z5.d, z0.d[2]
674; CHECK-NEXT:    fcvtzs x8, d6
675; CHECK-NEXT:    mov z2.d, z2.d[1]
676; CHECK-NEXT:    mov z6.d, z0.d[3]
677; CHECK-NEXT:    mov z1.d, z1.d[1]
678; CHECK-NEXT:    mov z3.d, z3.d[1]
679; CHECK-NEXT:    fcvtzs x15, d4
680; CHECK-NEXT:    mov z4.d, z0.d[1]
681; CHECK-NEXT:    fmov d0, x11
682; CHECK-NEXT:    fcvtzs x16, d5
683; CHECK-NEXT:    fcvtzs x11, d2
684; CHECK-NEXT:    fmov d2, x13
685; CHECK-NEXT:    fcvtzs x17, d7
686; CHECK-NEXT:    fcvtzs x18, d16
687; CHECK-NEXT:    fcvtzs x0, d3
688; CHECK-NEXT:    fcvtzs x13, d4
689; CHECK-NEXT:    fmov d4, x12
690; CHECK-NEXT:    fcvtzs x12, d6
691; CHECK-NEXT:    fmov d6, x14
692; CHECK-NEXT:    fcvtzs x14, d1
693; CHECK-NEXT:    fmov d3, x15
694; CHECK-NEXT:    fmov d1, x16
695; CHECK-NEXT:    fmov d5, x10
696; CHECK-NEXT:    fmov d7, x9
697; CHECK-NEXT:    mov v2.d[1], x11
698; CHECK-NEXT:    mov v0.d[1], x13
699; CHECK-NEXT:    mov v3.d[1], x8
700; CHECK-NEXT:    mov v6.d[1], x0
701; CHECK-NEXT:    mov v4.d[1], x14
702; CHECK-NEXT:    mov v1.d[1], x12
703; CHECK-NEXT:    mov v5.d[1], x18
704; CHECK-NEXT:    mov v7.d[1], x17
705; CHECK-NEXT:    ret
706  %a = call <16 x i64> @llvm.llrint.v16i64.v16f64(<16 x double> %x)
707  ret <16 x i64> %a
708}
709declare <16 x i64> @llvm.llrint.v16i64.v16f64(<16 x double>)
710
711define <32 x i64> @llrint_v32f64(<32 x double> %x) {
712; CHECK-LABEL: llrint_v32f64:
713; CHECK:       // %bb.0:
714; CHECK-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
715; CHECK-NEXT:    sub x9, sp, #272
716; CHECK-NEXT:    mov x29, sp
717; CHECK-NEXT:    and sp, x9, #0xffffffffffffffe0
718; CHECK-NEXT:    .cfi_def_cfa w29, 16
719; CHECK-NEXT:    .cfi_offset w30, -8
720; CHECK-NEXT:    .cfi_offset w29, -16
721; CHECK-NEXT:    ptrue p1.d, vl2
722; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
723; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
724; CHECK-NEXT:    // kill: def $q3 killed $q3 def $z3
725; CHECK-NEXT:    // kill: def $q2 killed $q2 def $z2
726; CHECK-NEXT:    // kill: def $q7 killed $q7 def $z7
727; CHECK-NEXT:    // kill: def $q6 killed $q6 def $z6
728; CHECK-NEXT:    // kill: def $q4 killed $q4 def $z4
729; CHECK-NEXT:    // kill: def $q5 killed $q5 def $z5
730; CHECK-NEXT:    ptrue p0.d, vl4
731; CHECK-NEXT:    splice z0.d, p1, z0.d, z1.d
732; CHECK-NEXT:    splice z2.d, p1, z2.d, z3.d
733; CHECK-NEXT:    splice z4.d, p1, z4.d, z5.d
734; CHECK-NEXT:    splice z6.d, p1, z6.d, z7.d
735; CHECK-NEXT:    ldp q5, q19, [x29, #16]
736; CHECK-NEXT:    movprfx z3, z0
737; CHECK-NEXT:    frintx z3.d, p0/m, z0.d
738; CHECK-NEXT:    movprfx z16, z2
739; CHECK-NEXT:    frintx z16.d, p0/m, z2.d
740; CHECK-NEXT:    frintx z4.d, p0/m, z4.d
741; CHECK-NEXT:    splice z5.d, p1, z5.d, z19.d
742; CHECK-NEXT:    frintx z6.d, p0/m, z6.d
743; CHECK-NEXT:    ldp q2, q17, [x29, #48]
744; CHECK-NEXT:    ldp q0, q1, [x29, #112]
745; CHECK-NEXT:    mov z18.d, z3.d[3]
746; CHECK-NEXT:    mov z7.d, z3.d[2]
747; CHECK-NEXT:    fcvtzs x9, d3
748; CHECK-NEXT:    mov z3.d, z3.d[1]
749; CHECK-NEXT:    mov z20.d, z16.d[3]
750; CHECK-NEXT:    fcvtzs x12, d16
751; CHECK-NEXT:    splice z2.d, p1, z2.d, z17.d
752; CHECK-NEXT:    frintx z5.d, p0/m, z5.d
753; CHECK-NEXT:    splice z0.d, p1, z0.d, z1.d
754; CHECK-NEXT:    fcvtzs x10, d18
755; CHECK-NEXT:    fcvtzs x11, d7
756; CHECK-NEXT:    mov z18.d, z16.d[2]
757; CHECK-NEXT:    mov z7.d, z16.d[1]
758; CHECK-NEXT:    fcvtzs x13, d3
759; CHECK-NEXT:    fcvtzs x14, d20
760; CHECK-NEXT:    str x9, [sp, #128]
761; CHECK-NEXT:    mov z16.d, z4.d[3]
762; CHECK-NEXT:    fcvtzs x9, d18
763; CHECK-NEXT:    mov z18.d, z4.d[2]
764; CHECK-NEXT:    frintx z2.d, p0/m, z2.d
765; CHECK-NEXT:    stp x11, x10, [sp, #144]
766; CHECK-NEXT:    fcvtzs x10, d7
767; CHECK-NEXT:    mov z7.d, z4.d[1]
768; CHECK-NEXT:    str x13, [sp, #136]
769; CHECK-NEXT:    fcvtzs x11, d16
770; CHECK-NEXT:    mov z16.d, z6.d[3]
771; CHECK-NEXT:    fcvtzs x13, d18
772; CHECK-NEXT:    ldp q3, q19, [x29, #80]
773; CHECK-NEXT:    stp x9, x14, [sp, #176]
774; CHECK-NEXT:    fcvtzs x9, d4
775; CHECK-NEXT:    mov z4.d, z6.d[2]
776; CHECK-NEXT:    stp x12, x10, [sp, #160]
777; CHECK-NEXT:    fcvtzs x10, d7
778; CHECK-NEXT:    mov z7.d, z6.d[1]
779; CHECK-NEXT:    fcvtzs x12, d6
780; CHECK-NEXT:    splice z3.d, p1, z3.d, z19.d
781; CHECK-NEXT:    mov z6.d, z5.d[2]
782; CHECK-NEXT:    stp x13, x11, [sp, #208]
783; CHECK-NEXT:    fcvtzs x11, d16
784; CHECK-NEXT:    fcvtzs x13, d4
785; CHECK-NEXT:    mov z4.d, z5.d[3]
786; CHECK-NEXT:    mov z1.d, z5.d[1]
787; CHECK-NEXT:    frintx z0.d, p0/m, z0.d
788; CHECK-NEXT:    stp x9, x10, [sp, #192]
789; CHECK-NEXT:    fcvtzs x9, d7
790; CHECK-NEXT:    frintx z3.d, p0/m, z3.d
791; CHECK-NEXT:    fcvtzs x10, d4
792; CHECK-NEXT:    stp x13, x11, [sp, #240]
793; CHECK-NEXT:    fcvtzs x11, d6
794; CHECK-NEXT:    mov z4.d, z2.d[3]
795; CHECK-NEXT:    fcvtzs x13, d2
796; CHECK-NEXT:    stp x12, x9, [sp, #224]
797; CHECK-NEXT:    fcvtzs x9, d5
798; CHECK-NEXT:    fcvtzs x12, d1
799; CHECK-NEXT:    mov z5.d, z2.d[2]
800; CHECK-NEXT:    mov z1.d, z2.d[1]
801; CHECK-NEXT:    mov z2.d, z3.d[2]
802; CHECK-NEXT:    stp x11, x10, [sp, #16]
803; CHECK-NEXT:    fcvtzs x10, d4
804; CHECK-NEXT:    mov z4.d, z3.d[3]
805; CHECK-NEXT:    fcvtzs x11, d5
806; CHECK-NEXT:    stp x9, x12, [sp]
807; CHECK-NEXT:    fcvtzs x9, d1
808; CHECK-NEXT:    mov z1.d, z3.d[1]
809; CHECK-NEXT:    fcvtzs x12, d4
810; CHECK-NEXT:    stp x11, x10, [sp, #48]
811; CHECK-NEXT:    fcvtzs x10, d2
812; CHECK-NEXT:    fcvtzs x11, d3
813; CHECK-NEXT:    stp x13, x9, [sp, #32]
814; CHECK-NEXT:    fcvtzs x9, d1
815; CHECK-NEXT:    mov z2.d, z0.d[3]
816; CHECK-NEXT:    mov z3.d, z0.d[2]
817; CHECK-NEXT:    mov z1.d, z0.d[1]
818; CHECK-NEXT:    fcvtzs x13, d2
819; CHECK-NEXT:    stp x10, x12, [sp, #80]
820; CHECK-NEXT:    fcvtzs x12, d0
821; CHECK-NEXT:    fcvtzs x10, d3
822; CHECK-NEXT:    stp x11, x9, [sp, #64]
823; CHECK-NEXT:    fcvtzs x9, d1
824; CHECK-NEXT:    stp x10, x13, [sp, #112]
825; CHECK-NEXT:    add x10, sp, #192
826; CHECK-NEXT:    stp x12, x9, [sp, #96]
827; CHECK-NEXT:    add x9, sp, #128
828; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x9]
829; CHECK-NEXT:    add x9, sp, #160
830; CHECK-NEXT:    ld1d { z2.d }, p0/z, [x10]
831; CHECK-NEXT:    ld1d { z1.d }, p0/z, [x9]
832; CHECK-NEXT:    add x9, sp, #96
833; CHECK-NEXT:    add x10, sp, #224
834; CHECK-NEXT:    ld1d { z3.d }, p0/z, [x9]
835; CHECK-NEXT:    add x9, sp, #64
836; CHECK-NEXT:    ld1d { z4.d }, p0/z, [x10]
837; CHECK-NEXT:    add x10, sp, #32
838; CHECK-NEXT:    ld1d { z5.d }, p0/z, [x9]
839; CHECK-NEXT:    mov x9, sp
840; CHECK-NEXT:    ld1d { z6.d }, p0/z, [x10]
841; CHECK-NEXT:    mov x10, #28 // =0x1c
842; CHECK-NEXT:    ld1d { z7.d }, p0/z, [x9]
843; CHECK-NEXT:    mov x9, #24 // =0x18
844; CHECK-NEXT:    st1d { z3.d }, p0, [x8, x10, lsl #3]
845; CHECK-NEXT:    st1d { z5.d }, p0, [x8, x9, lsl #3]
846; CHECK-NEXT:    mov x9, #20 // =0x14
847; CHECK-NEXT:    st1d { z6.d }, p0, [x8, x9, lsl #3]
848; CHECK-NEXT:    mov x9, #16 // =0x10
849; CHECK-NEXT:    st1d { z7.d }, p0, [x8, x9, lsl #3]
850; CHECK-NEXT:    mov x9, #12 // =0xc
851; CHECK-NEXT:    st1d { z4.d }, p0, [x8, x9, lsl #3]
852; CHECK-NEXT:    mov x9, #8 // =0x8
853; CHECK-NEXT:    st1d { z2.d }, p0, [x8, x9, lsl #3]
854; CHECK-NEXT:    mov x9, #4 // =0x4
855; CHECK-NEXT:    st1d { z1.d }, p0, [x8, x9, lsl #3]
856; CHECK-NEXT:    st1d { z0.d }, p0, [x8]
857; CHECK-NEXT:    mov sp, x29
858; CHECK-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload
859; CHECK-NEXT:    ret
860  %a = call <32 x i64> @llvm.llrint.v32i64.v16f64(<32 x double> %x)
861  ret <32 x i64> %a
862}
863declare <32 x i64> @llvm.llrint.v32i64.v32f64(<32 x double>)
864