1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256 3; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512 4; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512 5 6target triple = "aarch64-unknown-linux-gnu" 7 8; Don't use SVE for 64-bit vectors 9define <8 x i8> @shuffle_ext_byone_v8i8(<8 x i8> %op1, <8 x i8> %op2) vscale_range(2,0) #0 { 10; CHECK-LABEL: shuffle_ext_byone_v8i8: 11; CHECK: // %bb.0: 12; CHECK-NEXT: ext v0.8b, v0.8b, v1.8b, #7 13; CHECK-NEXT: ret 14 %ret = shufflevector <8 x i8> %op1, <8 x i8> %op2, <8 x i32> <i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14> 15 ret <8 x i8> %ret 16} 17 18; Don't use SVE for 128-bit vectors 19define <16 x i8> @shuffle_ext_byone_v16i8(<16 x i8> %op1, <16 x i8> %op2) vscale_range(2,0) #0 { 20; CHECK-LABEL: shuffle_ext_byone_v16i8: 21; CHECK: // %bb.0: 22; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #15 23; CHECK-NEXT: ret 24 %ret = shufflevector <16 x i8> %op1, <16 x i8> %op2, <16 x i32> <i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, 25 i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30> 26 ret <16 x i8> %ret 27} 28 29define void @shuffle_ext_byone_v32i8(ptr %a, ptr %b) vscale_range(2,0) #0 { 30; CHECK-LABEL: shuffle_ext_byone_v32i8: 31; CHECK: // %bb.0: 32; CHECK-NEXT: ptrue p0.b, vl32 33; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0] 34; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1] 35; CHECK-NEXT: mov z0.b, z0.b[31] 36; CHECK-NEXT: fmov w8, s0 37; CHECK-NEXT: insr z1.b, w8 38; CHECK-NEXT: st1b { z1.b }, p0, [x0] 39; CHECK-NEXT: ret 40 %op1 = load <32 x i8>, ptr %a 41 %op2 = load <32 x i8>, ptr %b 42 %ret = shufflevector <32 x i8> %op1, <32 x i8> %op2, <32 x i32> <i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, 43 i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, 44 i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, 45 i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62> 46 store <32 x i8> %ret, ptr %a 47 ret void 48} 49 50define void @shuffle_ext_byone_v64i8(ptr %a, ptr %b) #0 { 51; VBITS_GE_256-LABEL: shuffle_ext_byone_v64i8: 52; VBITS_GE_256: // %bb.0: 53; VBITS_GE_256-NEXT: ptrue p0.b, vl32 54; VBITS_GE_256-NEXT: mov w8, #32 // =0x20 55; VBITS_GE_256-NEXT: ld1b { z0.b }, p0/z, [x1] 56; VBITS_GE_256-NEXT: ld1b { z1.b }, p0/z, [x0, x8] 57; VBITS_GE_256-NEXT: ld1b { z3.b }, p0/z, [x1, x8] 58; VBITS_GE_256-NEXT: mov z2.b, z0.b[31] 59; VBITS_GE_256-NEXT: mov z1.b, z1.b[31] 60; VBITS_GE_256-NEXT: fmov w9, s2 61; VBITS_GE_256-NEXT: insr z3.b, w9 62; VBITS_GE_256-NEXT: fmov w9, s1 63; VBITS_GE_256-NEXT: insr z0.b, w9 64; VBITS_GE_256-NEXT: st1b { z3.b }, p0, [x0, x8] 65; VBITS_GE_256-NEXT: st1b { z0.b }, p0, [x0] 66; VBITS_GE_256-NEXT: ret 67; 68; VBITS_GE_512-LABEL: shuffle_ext_byone_v64i8: 69; VBITS_GE_512: // %bb.0: 70; VBITS_GE_512-NEXT: ptrue p0.b, vl64 71; VBITS_GE_512-NEXT: ld1b { z0.b }, p0/z, [x0] 72; VBITS_GE_512-NEXT: ld1b { z1.b }, p0/z, [x1] 73; VBITS_GE_512-NEXT: mov z0.b, z0.b[63] 74; VBITS_GE_512-NEXT: fmov w8, s0 75; VBITS_GE_512-NEXT: insr z1.b, w8 76; VBITS_GE_512-NEXT: st1b { z1.b }, p0, [x0] 77; VBITS_GE_512-NEXT: ret 78 %op1 = load <64 x i8>, ptr %a 79 %op2 = load <64 x i8>, ptr %b 80 %ret = shufflevector <64 x i8> %op1, <64 x i8> %op2, <64 x i32> <i32 63, i32 64, i32 65, i32 66, i32 67, i32 68, i32 69, i32 70, 81 i32 71, i32 72, i32 73, i32 74, i32 75, i32 76, i32 77, i32 78, 82 i32 79, i32 80, i32 81, i32 82, i32 83, i32 84, i32 85, i32 86, 83 i32 87, i32 88, i32 89, i32 90, i32 91, i32 92, i32 93, i32 94, 84 i32 95, i32 96, i32 97, i32 98, i32 99, i32 100, i32 101, i32 102, 85 i32 103, i32 104, i32 105, i32 106, i32 107, i32 108, i32 109, i32 110, 86 i32 111, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, 87 i32 119, i32 120, i32 121, i32 122, i32 123, i32 124, i32 125, i32 126> 88 store <64 x i8> %ret, ptr %a 89 ret void 90} 91 92define void @shuffle_ext_byone_v128i8(ptr %a, ptr %b) vscale_range(8,0) #0 { 93; CHECK-LABEL: shuffle_ext_byone_v128i8: 94; CHECK: // %bb.0: 95; CHECK-NEXT: ptrue p0.b, vl128 96; CHECK-NEXT: mov w8, #127 // =0x7f 97; CHECK-NEXT: whilels p1.b, xzr, x8 98; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0] 99; CHECK-NEXT: lastb w8, p1, z0.b 100; CHECK-NEXT: ld1b { z0.b }, p0/z, [x1] 101; CHECK-NEXT: insr z0.b, w8 102; CHECK-NEXT: st1b { z0.b }, p0, [x0] 103; CHECK-NEXT: ret 104 %op1 = load <128 x i8>, ptr %a 105 %op2 = load <128 x i8>, ptr %b 106 %ret = shufflevector <128 x i8> %op1, <128 x i8> %op2, <128 x i32> <i32 127, i32 128, i32 129, i32 130, i32 131, i32 132, i32 133, i32 134, 107 i32 135, i32 136, i32 137, i32 138, i32 139, i32 140, i32 141, i32 142, 108 i32 143, i32 144, i32 145, i32 146, i32 147, i32 148, i32 149, i32 150, 109 i32 151, i32 152, i32 153, i32 154, i32 155, i32 156, i32 157, i32 158, 110 i32 159, i32 160, i32 161, i32 162, i32 163, i32 164, i32 165, i32 166, 111 i32 167, i32 168, i32 169, i32 170, i32 171, i32 172, i32 173, i32 174, 112 i32 175, i32 176, i32 177, i32 178, i32 179, i32 180, i32 181, i32 182, 113 i32 183, i32 184, i32 185, i32 186, i32 187, i32 188, i32 189, i32 190, 114 i32 191, i32 192, i32 193, i32 194, i32 195, i32 196, i32 197, i32 198, 115 i32 199, i32 200, i32 201, i32 202, i32 203, i32 204, i32 205, i32 206, 116 i32 207, i32 208, i32 209, i32 210, i32 211, i32 212, i32 213, i32 214, 117 i32 215, i32 216, i32 217, i32 218, i32 219, i32 220, i32 221, i32 222, 118 i32 223, i32 224, i32 225, i32 226, i32 227, i32 228, i32 229, i32 230, 119 i32 231, i32 232, i32 233, i32 234, i32 235, i32 236, i32 237, i32 238, 120 i32 239, i32 240, i32 241, i32 242, i32 243, i32 244, i32 245, i32 246, 121 i32 247, i32 248, i32 249, i32 250, i32 251, i32 252, i32 253, i32 254> 122 store <128 x i8> %ret, ptr %a 123 ret void 124} 125 126define void @shuffle_ext_byone_v256i8(ptr %a, ptr %b) vscale_range(16,0) #0 { 127; CHECK-LABEL: shuffle_ext_byone_v256i8: 128; CHECK: // %bb.0: 129; CHECK-NEXT: ptrue p0.b, vl256 130; CHECK-NEXT: mov w8, #255 // =0xff 131; CHECK-NEXT: whilels p1.b, xzr, x8 132; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0] 133; CHECK-NEXT: lastb w8, p1, z0.b 134; CHECK-NEXT: ld1b { z0.b }, p0/z, [x1] 135; CHECK-NEXT: insr z0.b, w8 136; CHECK-NEXT: st1b { z0.b }, p0, [x0] 137; CHECK-NEXT: ret 138 %op1 = load <256 x i8>, ptr %a 139 %op2 = load <256 x i8>, ptr %b 140 %ret = shufflevector <256 x i8> %op1, <256 x i8> %op2, <256 x i32> <i32 255, i32 256, i32 257, i32 258, i32 259, i32 260, i32 261, i32 262, 141 i32 263, i32 264, i32 265, i32 266, i32 267, i32 268, i32 269, i32 270, 142 i32 271, i32 272, i32 273, i32 274, i32 275, i32 276, i32 277, i32 278, 143 i32 279, i32 280, i32 281, i32 282, i32 283, i32 284, i32 285, i32 286, 144 i32 287, i32 288, i32 289, i32 290, i32 291, i32 292, i32 293, i32 294, 145 i32 295, i32 296, i32 297, i32 298, i32 299, i32 300, i32 301, i32 302, 146 i32 303, i32 304, i32 305, i32 306, i32 307, i32 308, i32 309, i32 310, 147 i32 311, i32 312, i32 313, i32 314, i32 315, i32 316, i32 317, i32 318, 148 i32 319, i32 320, i32 321, i32 322, i32 323, i32 324, i32 325, i32 326, 149 i32 327, i32 328, i32 329, i32 330, i32 331, i32 332, i32 333, i32 334, 150 i32 335, i32 336, i32 337, i32 338, i32 339, i32 340, i32 341, i32 342, 151 i32 343, i32 344, i32 345, i32 346, i32 347, i32 348, i32 349, i32 350, 152 i32 351, i32 352, i32 353, i32 354, i32 355, i32 356, i32 357, i32 358, 153 i32 359, i32 360, i32 361, i32 362, i32 363, i32 364, i32 365, i32 366, 154 i32 367, i32 368, i32 369, i32 370, i32 371, i32 372, i32 373, i32 374, 155 i32 375, i32 376, i32 377, i32 378, i32 379, i32 380, i32 381, i32 382, 156 i32 383, i32 384, i32 385, i32 386, i32 387, i32 388, i32 389, i32 390, 157 i32 391, i32 392, i32 393, i32 394, i32 395, i32 396, i32 397, i32 398, 158 i32 399, i32 400, i32 401, i32 402, i32 403, i32 404, i32 405, i32 406, 159 i32 407, i32 408, i32 409, i32 410, i32 411, i32 412, i32 413, i32 414, 160 i32 415, i32 416, i32 417, i32 418, i32 419, i32 420, i32 421, i32 422, 161 i32 423, i32 424, i32 425, i32 426, i32 427, i32 428, i32 429, i32 430, 162 i32 431, i32 432, i32 433, i32 434, i32 435, i32 436, i32 437, i32 438, 163 i32 439, i32 440, i32 441, i32 442, i32 443, i32 444, i32 445, i32 446, 164 i32 447, i32 448, i32 449, i32 450, i32 451, i32 452, i32 453, i32 454, 165 i32 455, i32 456, i32 457, i32 458, i32 459, i32 460, i32 461, i32 462, 166 i32 463, i32 464, i32 465, i32 466, i32 467, i32 468, i32 469, i32 470, 167 i32 471, i32 472, i32 473, i32 474, i32 475, i32 476, i32 477, i32 478, 168 i32 479, i32 480, i32 481, i32 482, i32 483, i32 484, i32 485, i32 486, 169 i32 487, i32 488, i32 489, i32 490, i32 491, i32 492, i32 493, i32 494, 170 i32 495, i32 496, i32 497, i32 498, i32 499, i32 500, i32 501, i32 502, 171 i32 503, i32 504, i32 505, i32 506, i32 507, i32 508, i32 509, i32 510> 172 store <256 x i8> %ret, ptr %a 173 ret void 174} 175 176; Don't use SVE for 64-bit vectors 177define <4 x i16> @shuffle_ext_byone_v4i16(<4 x i16> %op1, <4 x i16> %op2) vscale_range(2,0) #0 { 178; CHECK-LABEL: shuffle_ext_byone_v4i16: 179; CHECK: // %bb.0: 180; CHECK-NEXT: ext v0.8b, v0.8b, v1.8b, #6 181; CHECK-NEXT: ret 182 %ret = shufflevector <4 x i16> %op1, <4 x i16> %op2, <4 x i32> <i32 3, i32 4, i32 5, i32 6> 183 ret <4 x i16> %ret 184} 185 186; Don't use SVE for 128-bit vectors 187define <8 x i16> @shuffle_ext_byone_v8i16(<8 x i16> %op1, <8 x i16> %op2) vscale_range(2,0) #0 { 188; CHECK-LABEL: shuffle_ext_byone_v8i16: 189; CHECK: // %bb.0: 190; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #14 191; CHECK-NEXT: ret 192 %ret = shufflevector <8 x i16> %op1, <8 x i16> %op2, <8 x i32> <i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14> 193 ret <8 x i16> %ret 194} 195 196define void @shuffle_ext_byone_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 { 197; CHECK-LABEL: shuffle_ext_byone_v16i16: 198; CHECK: // %bb.0: 199; CHECK-NEXT: ptrue p0.h, vl16 200; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0] 201; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1] 202; CHECK-NEXT: mov z0.h, z0.h[15] 203; CHECK-NEXT: fmov w8, s0 204; CHECK-NEXT: insr z1.h, w8 205; CHECK-NEXT: st1h { z1.h }, p0, [x0] 206; CHECK-NEXT: ret 207 %op1 = load <16 x i16>, ptr %a 208 %op2 = load <16 x i16>, ptr %b 209 %ret = shufflevector <16 x i16> %op1, <16 x i16> %op2, <16 x i32> <i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, 210 i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30> 211 store <16 x i16> %ret, ptr %a 212 ret void 213} 214 215define void @shuffle_ext_byone_v32i16(ptr %a, ptr %b) #0 { 216; VBITS_GE_256-LABEL: shuffle_ext_byone_v32i16: 217; VBITS_GE_256: // %bb.0: 218; VBITS_GE_256-NEXT: ptrue p0.h, vl16 219; VBITS_GE_256-NEXT: mov x8, #16 // =0x10 220; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x1] 221; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x0, x8, lsl #1] 222; VBITS_GE_256-NEXT: ld1h { z3.h }, p0/z, [x1, x8, lsl #1] 223; VBITS_GE_256-NEXT: mov z2.h, z0.h[15] 224; VBITS_GE_256-NEXT: mov z1.h, z1.h[15] 225; VBITS_GE_256-NEXT: fmov w9, s2 226; VBITS_GE_256-NEXT: insr z3.h, w9 227; VBITS_GE_256-NEXT: fmov w9, s1 228; VBITS_GE_256-NEXT: insr z0.h, w9 229; VBITS_GE_256-NEXT: st1h { z3.h }, p0, [x0, x8, lsl #1] 230; VBITS_GE_256-NEXT: st1h { z0.h }, p0, [x0] 231; VBITS_GE_256-NEXT: ret 232; 233; VBITS_GE_512-LABEL: shuffle_ext_byone_v32i16: 234; VBITS_GE_512: // %bb.0: 235; VBITS_GE_512-NEXT: ptrue p0.h, vl32 236; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0] 237; VBITS_GE_512-NEXT: ld1h { z1.h }, p0/z, [x1] 238; VBITS_GE_512-NEXT: mov z0.h, z0.h[31] 239; VBITS_GE_512-NEXT: fmov w8, s0 240; VBITS_GE_512-NEXT: insr z1.h, w8 241; VBITS_GE_512-NEXT: st1h { z1.h }, p0, [x0] 242; VBITS_GE_512-NEXT: ret 243 %op1 = load <32 x i16>, ptr %a 244 %op2 = load <32 x i16>, ptr %b 245 %ret = shufflevector <32 x i16> %op1, <32 x i16> %op2, <32 x i32> <i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, 246 i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, 247 i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, 248 i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62> 249 store <32 x i16> %ret, ptr %a 250 ret void 251} 252 253define void @shuffle_ext_byone_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 { 254; CHECK-LABEL: shuffle_ext_byone_v64i16: 255; CHECK: // %bb.0: 256; CHECK-NEXT: ptrue p0.h, vl64 257; CHECK-NEXT: mov w8, #63 // =0x3f 258; CHECK-NEXT: whilels p1.h, xzr, x8 259; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0] 260; CHECK-NEXT: lastb w8, p1, z0.h 261; CHECK-NEXT: ld1h { z0.h }, p0/z, [x1] 262; CHECK-NEXT: insr z0.h, w8 263; CHECK-NEXT: st1h { z0.h }, p0, [x0] 264; CHECK-NEXT: ret 265 %op1 = load <64 x i16>, ptr %a 266 %op2 = load <64 x i16>, ptr %b 267 %ret = shufflevector <64 x i16> %op1, <64 x i16> %op2, <64 x i32> <i32 63, i32 64, i32 65, i32 66, i32 67, i32 68, i32 69, i32 70, 268 i32 71, i32 72, i32 73, i32 74, i32 75, i32 76, i32 77, i32 78, 269 i32 79, i32 80, i32 81, i32 82, i32 83, i32 84, i32 85, i32 86, 270 i32 87, i32 88, i32 89, i32 90, i32 91, i32 92, i32 93, i32 94, 271 i32 95, i32 96, i32 97, i32 98, i32 99, i32 100, i32 101, i32 102, 272 i32 103, i32 104, i32 105, i32 106, i32 107, i32 108, i32 109, i32 110, 273 i32 111, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, 274 i32 119, i32 120, i32 121, i32 122, i32 123, i32 124, i32 125, i32 126> 275 store <64 x i16> %ret, ptr %a 276 ret void 277} 278 279define void @shuffle_ext_byone_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 { 280; CHECK-LABEL: shuffle_ext_byone_v128i16: 281; CHECK: // %bb.0: 282; CHECK-NEXT: ptrue p0.h, vl128 283; CHECK-NEXT: mov w8, #127 // =0x7f 284; CHECK-NEXT: whilels p1.h, xzr, x8 285; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0] 286; CHECK-NEXT: lastb w8, p1, z0.h 287; CHECK-NEXT: ld1h { z0.h }, p0/z, [x1] 288; CHECK-NEXT: insr z0.h, w8 289; CHECK-NEXT: st1h { z0.h }, p0, [x0] 290; CHECK-NEXT: ret 291 %op1 = load <128 x i16>, ptr %a 292 %op2 = load <128 x i16>, ptr %b 293 %ret = shufflevector <128 x i16> %op1, <128 x i16> %op2, <128 x i32> <i32 127, i32 128, i32 129, i32 130, i32 131, i32 132, i32 133, i32 134, 294 i32 135, i32 136, i32 137, i32 138, i32 139, i32 140, i32 141, i32 142, 295 i32 143, i32 144, i32 145, i32 146, i32 147, i32 148, i32 149, i32 150, 296 i32 151, i32 152, i32 153, i32 154, i32 155, i32 156, i32 157, i32 158, 297 i32 159, i32 160, i32 161, i32 162, i32 163, i32 164, i32 165, i32 166, 298 i32 167, i32 168, i32 169, i32 170, i32 171, i32 172, i32 173, i32 174, 299 i32 175, i32 176, i32 177, i32 178, i32 179, i32 180, i32 181, i32 182, 300 i32 183, i32 184, i32 185, i32 186, i32 187, i32 188, i32 189, i32 190, 301 i32 191, i32 192, i32 193, i32 194, i32 195, i32 196, i32 197, i32 198, 302 i32 199, i32 200, i32 201, i32 202, i32 203, i32 204, i32 205, i32 206, 303 i32 207, i32 208, i32 209, i32 210, i32 211, i32 212, i32 213, i32 214, 304 i32 215, i32 216, i32 217, i32 218, i32 219, i32 220, i32 221, i32 222, 305 i32 223, i32 224, i32 225, i32 226, i32 227, i32 228, i32 229, i32 230, 306 i32 231, i32 232, i32 233, i32 234, i32 235, i32 236, i32 237, i32 238, 307 i32 239, i32 240, i32 241, i32 242, i32 243, i32 244, i32 245, i32 246, 308 i32 247, i32 248, i32 249, i32 250, i32 251, i32 252, i32 253, i32 254> 309 store <128 x i16> %ret, ptr %a 310 ret void 311} 312 313; Don't use SVE for 64-bit vectors 314define <2 x i32> @shuffle_ext_byone_v2i32(<2 x i32> %op1, <2 x i32> %op2) vscale_range(2,0) #0 { 315; CHECK-LABEL: shuffle_ext_byone_v2i32: 316; CHECK: // %bb.0: 317; CHECK-NEXT: ext v0.8b, v0.8b, v1.8b, #4 318; CHECK-NEXT: ret 319 %ret = shufflevector <2 x i32> %op1, <2 x i32> %op2, <2 x i32> <i32 1, i32 2> 320 ret <2 x i32> %ret 321} 322 323; Don't use SVE for 128-bit vectors 324define <4 x i32> @shuffle_ext_byone_v4i32(<4 x i32> %op1, <4 x i32> %op2) vscale_range(2,0) #0 { 325; CHECK-LABEL: shuffle_ext_byone_v4i32: 326; CHECK: // %bb.0: 327; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #12 328; CHECK-NEXT: ret 329 %ret = shufflevector <4 x i32> %op1, <4 x i32> %op2, <4 x i32> <i32 3, i32 4, i32 5, i32 6> 330 ret <4 x i32> %ret 331} 332 333define void @shuffle_ext_byone_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 { 334; CHECK-LABEL: shuffle_ext_byone_v8i32: 335; CHECK: // %bb.0: 336; CHECK-NEXT: ptrue p0.s, vl8 337; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] 338; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1] 339; CHECK-NEXT: mov z0.s, z0.s[7] 340; CHECK-NEXT: fmov w8, s0 341; CHECK-NEXT: insr z1.s, w8 342; CHECK-NEXT: st1w { z1.s }, p0, [x0] 343; CHECK-NEXT: ret 344 %op1 = load <8 x i32>, ptr %a 345 %op2 = load <8 x i32>, ptr %b 346 %ret = shufflevector <8 x i32> %op1, <8 x i32> %op2, <8 x i32> <i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14> 347 store <8 x i32> %ret, ptr %a 348 ret void 349} 350 351define void @shuffle_ext_byone_v16i32(ptr %a, ptr %b) #0 { 352; VBITS_GE_256-LABEL: shuffle_ext_byone_v16i32: 353; VBITS_GE_256: // %bb.0: 354; VBITS_GE_256-NEXT: ptrue p0.s, vl8 355; VBITS_GE_256-NEXT: mov x8, #8 // =0x8 356; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x1] 357; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x0, x8, lsl #2] 358; VBITS_GE_256-NEXT: ld1w { z3.s }, p0/z, [x1, x8, lsl #2] 359; VBITS_GE_256-NEXT: mov z2.s, z0.s[7] 360; VBITS_GE_256-NEXT: mov z1.s, z1.s[7] 361; VBITS_GE_256-NEXT: fmov w9, s2 362; VBITS_GE_256-NEXT: insr z3.s, w9 363; VBITS_GE_256-NEXT: fmov w9, s1 364; VBITS_GE_256-NEXT: insr z0.s, w9 365; VBITS_GE_256-NEXT: st1w { z3.s }, p0, [x0, x8, lsl #2] 366; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x0] 367; VBITS_GE_256-NEXT: ret 368; 369; VBITS_GE_512-LABEL: shuffle_ext_byone_v16i32: 370; VBITS_GE_512: // %bb.0: 371; VBITS_GE_512-NEXT: ptrue p0.s, vl16 372; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0] 373; VBITS_GE_512-NEXT: ld1w { z1.s }, p0/z, [x1] 374; VBITS_GE_512-NEXT: mov z0.s, z0.s[15] 375; VBITS_GE_512-NEXT: fmov w8, s0 376; VBITS_GE_512-NEXT: insr z1.s, w8 377; VBITS_GE_512-NEXT: st1w { z1.s }, p0, [x0] 378; VBITS_GE_512-NEXT: ret 379 %op1 = load <16 x i32>, ptr %a 380 %op2 = load <16 x i32>, ptr %b 381 %ret = shufflevector <16 x i32> %op1, <16 x i32> %op2, <16 x i32> <i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, 382 i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30> 383 store <16 x i32> %ret, ptr %a 384 ret void 385} 386 387define void @shuffle_ext_byone_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 { 388; CHECK-LABEL: shuffle_ext_byone_v32i32: 389; CHECK: // %bb.0: 390; CHECK-NEXT: ptrue p0.s, vl32 391; CHECK-NEXT: mov w8, #31 // =0x1f 392; CHECK-NEXT: whilels p1.s, xzr, x8 393; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] 394; CHECK-NEXT: lastb w8, p1, z0.s 395; CHECK-NEXT: ld1w { z0.s }, p0/z, [x1] 396; CHECK-NEXT: insr z0.s, w8 397; CHECK-NEXT: st1w { z0.s }, p0, [x0] 398; CHECK-NEXT: ret 399 %op1 = load <32 x i32>, ptr %a 400 %op2 = load <32 x i32>, ptr %b 401 %ret = shufflevector <32 x i32> %op1, <32 x i32> %op2, <32 x i32> <i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, 402 i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, 403 i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, 404 i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62> 405 store <32 x i32> %ret, ptr %a 406 ret void 407} 408 409define void @shuffle_ext_byone_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 { 410; CHECK-LABEL: shuffle_ext_byone_v64i32: 411; CHECK: // %bb.0: 412; CHECK-NEXT: ptrue p0.s, vl64 413; CHECK-NEXT: mov w8, #63 // =0x3f 414; CHECK-NEXT: whilels p1.s, xzr, x8 415; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] 416; CHECK-NEXT: lastb w8, p1, z0.s 417; CHECK-NEXT: ld1w { z0.s }, p0/z, [x1] 418; CHECK-NEXT: insr z0.s, w8 419; CHECK-NEXT: st1w { z0.s }, p0, [x0] 420; CHECK-NEXT: ret 421 %op1 = load <64 x i32>, ptr %a 422 %op2 = load <64 x i32>, ptr %b 423 %ret = shufflevector <64 x i32> %op1, <64 x i32> %op2, <64 x i32> <i32 63, i32 64, i32 65, i32 66, i32 67, i32 68, i32 69, i32 70, 424 i32 71, i32 72, i32 73, i32 74, i32 75, i32 76, i32 77, i32 78, 425 i32 79, i32 80, i32 81, i32 82, i32 83, i32 84, i32 85, i32 86, 426 i32 87, i32 88, i32 89, i32 90, i32 91, i32 92, i32 93, i32 94, 427 i32 95, i32 96, i32 97, i32 98, i32 99, i32 100, i32 101, i32 102, 428 i32 103, i32 104, i32 105, i32 106, i32 107, i32 108, i32 109, i32 110, 429 i32 111, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, 430 i32 119, i32 120, i32 121, i32 122, i32 123, i32 124, i32 125, i32 126> 431 store <64 x i32> %ret, ptr %a 432 ret void 433} 434 435; Don't use SVE for 128-bit vectors 436define <2 x i64> @shuffle_ext_byone_v2i64(<2 x i64> %op1, <2 x i64> %op2) vscale_range(2,0) #0 { 437; CHECK-LABEL: shuffle_ext_byone_v2i64: 438; CHECK: // %bb.0: 439; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #8 440; CHECK-NEXT: ret 441 %ret = shufflevector <2 x i64> %op1, <2 x i64> %op2, <2 x i32> <i32 1, i32 2> 442 ret <2 x i64> %ret 443} 444 445define void @shuffle_ext_byone_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 { 446; CHECK-LABEL: shuffle_ext_byone_v4i64: 447; CHECK: // %bb.0: 448; CHECK-NEXT: ptrue p0.d, vl4 449; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0] 450; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1] 451; CHECK-NEXT: mov z0.d, z0.d[3] 452; CHECK-NEXT: fmov x8, d0 453; CHECK-NEXT: insr z1.d, x8 454; CHECK-NEXT: st1d { z1.d }, p0, [x0] 455; CHECK-NEXT: ret 456 %op1 = load <4 x i64>, ptr %a 457 %op2 = load <4 x i64>, ptr %b 458 %ret = shufflevector <4 x i64> %op1, <4 x i64> %op2, <4 x i32> <i32 3, i32 4, i32 5, i32 6> 459 store <4 x i64> %ret, ptr %a 460 ret void 461} 462 463define void @shuffle_ext_byone_v8i64(ptr %a, ptr %b) #0 { 464; VBITS_GE_256-LABEL: shuffle_ext_byone_v8i64: 465; VBITS_GE_256: // %bb.0: 466; VBITS_GE_256-NEXT: ptrue p0.d, vl4 467; VBITS_GE_256-NEXT: mov x8, #4 // =0x4 468; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x1] 469; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x0, x8, lsl #3] 470; VBITS_GE_256-NEXT: ld1d { z3.d }, p0/z, [x1, x8, lsl #3] 471; VBITS_GE_256-NEXT: mov z2.d, z0.d[3] 472; VBITS_GE_256-NEXT: mov z1.d, z1.d[3] 473; VBITS_GE_256-NEXT: fmov x9, d2 474; VBITS_GE_256-NEXT: insr z3.d, x9 475; VBITS_GE_256-NEXT: fmov x9, d1 476; VBITS_GE_256-NEXT: insr z0.d, x9 477; VBITS_GE_256-NEXT: st1d { z3.d }, p0, [x0, x8, lsl #3] 478; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x0] 479; VBITS_GE_256-NEXT: ret 480; 481; VBITS_GE_512-LABEL: shuffle_ext_byone_v8i64: 482; VBITS_GE_512: // %bb.0: 483; VBITS_GE_512-NEXT: ptrue p0.d, vl8 484; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0] 485; VBITS_GE_512-NEXT: ld1d { z1.d }, p0/z, [x1] 486; VBITS_GE_512-NEXT: mov z0.d, z0.d[7] 487; VBITS_GE_512-NEXT: fmov x8, d0 488; VBITS_GE_512-NEXT: insr z1.d, x8 489; VBITS_GE_512-NEXT: st1d { z1.d }, p0, [x0] 490; VBITS_GE_512-NEXT: ret 491 %op1 = load <8 x i64>, ptr %a 492 %op2 = load <8 x i64>, ptr %b 493 %ret = shufflevector <8 x i64> %op1, <8 x i64> %op2, <8 x i32> <i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14> 494 store <8 x i64> %ret, ptr %a 495 ret void 496} 497 498define void @shuffle_ext_byone_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 { 499; CHECK-LABEL: shuffle_ext_byone_v16i64: 500; CHECK: // %bb.0: 501; CHECK-NEXT: ptrue p0.d, vl16 502; CHECK-NEXT: mov w8, #15 // =0xf 503; CHECK-NEXT: whilels p1.d, xzr, x8 504; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0] 505; CHECK-NEXT: lastb x8, p1, z0.d 506; CHECK-NEXT: ld1d { z0.d }, p0/z, [x1] 507; CHECK-NEXT: insr z0.d, x8 508; CHECK-NEXT: st1d { z0.d }, p0, [x0] 509; CHECK-NEXT: ret 510 %op1 = load <16 x i64>, ptr %a 511 %op2 = load <16 x i64>, ptr %b 512 %ret = shufflevector <16 x i64> %op1, <16 x i64> %op2, <16 x i32> <i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, 513 i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30> 514 store <16 x i64> %ret, ptr %a 515 ret void 516} 517 518define void @shuffle_ext_byone_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 { 519; CHECK-LABEL: shuffle_ext_byone_v32i64: 520; CHECK: // %bb.0: 521; CHECK-NEXT: ptrue p0.d, vl32 522; CHECK-NEXT: mov w8, #31 // =0x1f 523; CHECK-NEXT: whilels p1.d, xzr, x8 524; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0] 525; CHECK-NEXT: lastb x8, p1, z0.d 526; CHECK-NEXT: ld1d { z0.d }, p0/z, [x1] 527; CHECK-NEXT: insr z0.d, x8 528; CHECK-NEXT: st1d { z0.d }, p0, [x0] 529; CHECK-NEXT: ret 530 %op1 = load <32 x i64>, ptr %a 531 %op2 = load <32 x i64>, ptr %b 532 %ret = shufflevector <32 x i64> %op1, <32 x i64> %op2, <32 x i32> <i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, 533 i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, 534 i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, 535 i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62> 536 store <32 x i64> %ret, ptr %a 537 ret void 538} 539 540; Don't use SVE for 64-bit vectors 541define <4 x half> @shuffle_ext_byone_v4f16(<4 x half> %op1, <4 x half> %op2) vscale_range(2,0) #0 { 542; CHECK-LABEL: shuffle_ext_byone_v4f16: 543; CHECK: // %bb.0: 544; CHECK-NEXT: ext v0.8b, v0.8b, v1.8b, #6 545; CHECK-NEXT: ret 546 %ret = shufflevector <4 x half> %op1, <4 x half> %op2, <4 x i32> <i32 3, i32 4, i32 5, i32 6> 547 ret <4 x half> %ret 548} 549 550; Don't use SVE for 128-bit vectors 551define <8 x half> @shuffle_ext_byone_v8f16(<8 x half> %op1, <8 x half> %op2) vscale_range(2,0) #0 { 552; CHECK-LABEL: shuffle_ext_byone_v8f16: 553; CHECK: // %bb.0: 554; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #14 555; CHECK-NEXT: ret 556 %ret = shufflevector <8 x half> %op1, <8 x half> %op2, <8 x i32> <i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14> 557 ret <8 x half> %ret 558} 559 560define void @shuffle_ext_byone_v16f16(ptr %a, ptr %b) vscale_range(2,0) #0 { 561; CHECK-LABEL: shuffle_ext_byone_v16f16: 562; CHECK: // %bb.0: 563; CHECK-NEXT: ptrue p0.h, vl16 564; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0] 565; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1] 566; CHECK-NEXT: mov z0.h, z0.h[15] 567; CHECK-NEXT: insr z1.h, h0 568; CHECK-NEXT: st1h { z1.h }, p0, [x0] 569; CHECK-NEXT: ret 570 %op1 = load <16 x half>, ptr %a 571 %op2 = load <16 x half>, ptr %b 572 %ret = shufflevector <16 x half> %op1, <16 x half> %op2, <16 x i32> <i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, 573 i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30> 574 store <16 x half> %ret, ptr %a 575 ret void 576} 577 578define void @shuffle_ext_byone_v32f16(ptr %a, ptr %b) #0 { 579; VBITS_GE_256-LABEL: shuffle_ext_byone_v32f16: 580; VBITS_GE_256: // %bb.0: 581; VBITS_GE_256-NEXT: ptrue p0.h, vl16 582; VBITS_GE_256-NEXT: mov x8, #16 // =0x10 583; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x1] 584; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x0, x8, lsl #1] 585; VBITS_GE_256-NEXT: ld1h { z2.h }, p0/z, [x1, x8, lsl #1] 586; VBITS_GE_256-NEXT: mov z3.h, z0.h[15] 587; VBITS_GE_256-NEXT: mov z1.h, z1.h[15] 588; VBITS_GE_256-NEXT: insr z2.h, h3 589; VBITS_GE_256-NEXT: insr z0.h, h1 590; VBITS_GE_256-NEXT: st1h { z2.h }, p0, [x0, x8, lsl #1] 591; VBITS_GE_256-NEXT: st1h { z0.h }, p0, [x0] 592; VBITS_GE_256-NEXT: ret 593; 594; VBITS_GE_512-LABEL: shuffle_ext_byone_v32f16: 595; VBITS_GE_512: // %bb.0: 596; VBITS_GE_512-NEXT: ptrue p0.h, vl32 597; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0] 598; VBITS_GE_512-NEXT: ld1h { z1.h }, p0/z, [x1] 599; VBITS_GE_512-NEXT: mov z0.h, z0.h[31] 600; VBITS_GE_512-NEXT: insr z1.h, h0 601; VBITS_GE_512-NEXT: st1h { z1.h }, p0, [x0] 602; VBITS_GE_512-NEXT: ret 603 %op1 = load <32 x half>, ptr %a 604 %op2 = load <32 x half>, ptr %b 605 %ret = shufflevector <32 x half> %op1, <32 x half> %op2, <32 x i32> <i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, 606 i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, 607 i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, 608 i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62> 609 store <32 x half> %ret, ptr %a 610 ret void 611} 612 613define void @shuffle_ext_byone_v64f16(ptr %a, ptr %b) vscale_range(8,0) #0 { 614; CHECK-LABEL: shuffle_ext_byone_v64f16: 615; CHECK: // %bb.0: 616; CHECK-NEXT: ptrue p0.h, vl64 617; CHECK-NEXT: mov w8, #63 // =0x3f 618; CHECK-NEXT: whilels p1.h, xzr, x8 619; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0] 620; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1] 621; CHECK-NEXT: lastb h0, p1, z0.h 622; CHECK-NEXT: insr z1.h, h0 623; CHECK-NEXT: st1h { z1.h }, p0, [x0] 624; CHECK-NEXT: ret 625 %op1 = load <64 x half>, ptr %a 626 %op2 = load <64 x half>, ptr %b 627 %ret = shufflevector <64 x half> %op1, <64 x half> %op2, <64 x i32> <i32 63, i32 64, i32 65, i32 66, i32 67, i32 68, i32 69, i32 70, 628 i32 71, i32 72, i32 73, i32 74, i32 75, i32 76, i32 77, i32 78, 629 i32 79, i32 80, i32 81, i32 82, i32 83, i32 84, i32 85, i32 86, 630 i32 87, i32 88, i32 89, i32 90, i32 91, i32 92, i32 93, i32 94, 631 i32 95, i32 96, i32 97, i32 98, i32 99, i32 100, i32 101, i32 102, 632 i32 103, i32 104, i32 105, i32 106, i32 107, i32 108, i32 109, i32 110, 633 i32 111, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, 634 i32 119, i32 120, i32 121, i32 122, i32 123, i32 124, i32 125, i32 126> 635 store <64 x half> %ret, ptr %a 636 ret void 637} 638 639define void @shuffle_ext_byone_v128f16(ptr %a, ptr %b) vscale_range(16,0) #0 { 640; CHECK-LABEL: shuffle_ext_byone_v128f16: 641; CHECK: // %bb.0: 642; CHECK-NEXT: ptrue p0.h, vl128 643; CHECK-NEXT: mov w8, #127 // =0x7f 644; CHECK-NEXT: whilels p1.h, xzr, x8 645; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0] 646; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1] 647; CHECK-NEXT: lastb h0, p1, z0.h 648; CHECK-NEXT: insr z1.h, h0 649; CHECK-NEXT: st1h { z1.h }, p0, [x0] 650; CHECK-NEXT: ret 651 %op1 = load <128 x half>, ptr %a 652 %op2 = load <128 x half>, ptr %b 653 %ret = shufflevector <128 x half> %op1, <128 x half> %op2, <128 x i32> <i32 127, i32 128, i32 129, i32 130, i32 131, i32 132, i32 133, i32 134, 654 i32 135, i32 136, i32 137, i32 138, i32 139, i32 140, i32 141, i32 142, 655 i32 143, i32 144, i32 145, i32 146, i32 147, i32 148, i32 149, i32 150, 656 i32 151, i32 152, i32 153, i32 154, i32 155, i32 156, i32 157, i32 158, 657 i32 159, i32 160, i32 161, i32 162, i32 163, i32 164, i32 165, i32 166, 658 i32 167, i32 168, i32 169, i32 170, i32 171, i32 172, i32 173, i32 174, 659 i32 175, i32 176, i32 177, i32 178, i32 179, i32 180, i32 181, i32 182, 660 i32 183, i32 184, i32 185, i32 186, i32 187, i32 188, i32 189, i32 190, 661 i32 191, i32 192, i32 193, i32 194, i32 195, i32 196, i32 197, i32 198, 662 i32 199, i32 200, i32 201, i32 202, i32 203, i32 204, i32 205, i32 206, 663 i32 207, i32 208, i32 209, i32 210, i32 211, i32 212, i32 213, i32 214, 664 i32 215, i32 216, i32 217, i32 218, i32 219, i32 220, i32 221, i32 222, 665 i32 223, i32 224, i32 225, i32 226, i32 227, i32 228, i32 229, i32 230, 666 i32 231, i32 232, i32 233, i32 234, i32 235, i32 236, i32 237, i32 238, 667 i32 239, i32 240, i32 241, i32 242, i32 243, i32 244, i32 245, i32 246, 668 i32 247, i32 248, i32 249, i32 250, i32 251, i32 252, i32 253, i32 254> 669 store <128 x half> %ret, ptr %a 670 ret void 671} 672 673; Don't use SVE for 64-bit vectors 674define <2 x float> @shuffle_ext_byone_v2f32(<2 x float> %op1, <2 x float> %op2) vscale_range(2,0) #0 { 675; CHECK-LABEL: shuffle_ext_byone_v2f32: 676; CHECK: // %bb.0: 677; CHECK-NEXT: ext v0.8b, v0.8b, v1.8b, #4 678; CHECK-NEXT: ret 679 %ret = shufflevector <2 x float> %op1, <2 x float> %op2, <2 x i32> <i32 1, i32 2> 680 ret <2 x float> %ret 681} 682 683; Don't use SVE for 128-bit vectors 684define <4 x float> @shuffle_ext_byone_v4f32(<4 x float> %op1, <4 x float> %op2) vscale_range(2,0) #0 { 685; CHECK-LABEL: shuffle_ext_byone_v4f32: 686; CHECK: // %bb.0: 687; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #12 688; CHECK-NEXT: ret 689 %ret = shufflevector <4 x float> %op1, <4 x float> %op2, <4 x i32> <i32 3, i32 4, i32 5, i32 6> 690 ret <4 x float> %ret 691} 692 693define void @shuffle_ext_byone_v8f32(ptr %a, ptr %b) vscale_range(2,0) #0 { 694; CHECK-LABEL: shuffle_ext_byone_v8f32: 695; CHECK: // %bb.0: 696; CHECK-NEXT: ptrue p0.s, vl8 697; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] 698; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1] 699; CHECK-NEXT: mov z0.s, z0.s[7] 700; CHECK-NEXT: insr z1.s, s0 701; CHECK-NEXT: st1w { z1.s }, p0, [x0] 702; CHECK-NEXT: ret 703 %op1 = load <8 x float>, ptr %a 704 %op2 = load <8 x float>, ptr %b 705 %ret = shufflevector <8 x float> %op1, <8 x float> %op2, <8 x i32> <i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14> 706 store <8 x float> %ret, ptr %a 707 ret void 708} 709 710define void @shuffle_ext_byone_v16f32(ptr %a, ptr %b) #0 { 711; VBITS_GE_256-LABEL: shuffle_ext_byone_v16f32: 712; VBITS_GE_256: // %bb.0: 713; VBITS_GE_256-NEXT: ptrue p0.s, vl8 714; VBITS_GE_256-NEXT: mov x8, #8 // =0x8 715; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x1] 716; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x0, x8, lsl #2] 717; VBITS_GE_256-NEXT: ld1w { z2.s }, p0/z, [x1, x8, lsl #2] 718; VBITS_GE_256-NEXT: mov z3.s, z0.s[7] 719; VBITS_GE_256-NEXT: mov z1.s, z1.s[7] 720; VBITS_GE_256-NEXT: insr z2.s, s3 721; VBITS_GE_256-NEXT: insr z0.s, s1 722; VBITS_GE_256-NEXT: st1w { z2.s }, p0, [x0, x8, lsl #2] 723; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x0] 724; VBITS_GE_256-NEXT: ret 725; 726; VBITS_GE_512-LABEL: shuffle_ext_byone_v16f32: 727; VBITS_GE_512: // %bb.0: 728; VBITS_GE_512-NEXT: ptrue p0.s, vl16 729; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0] 730; VBITS_GE_512-NEXT: ld1w { z1.s }, p0/z, [x1] 731; VBITS_GE_512-NEXT: mov z0.s, z0.s[15] 732; VBITS_GE_512-NEXT: insr z1.s, s0 733; VBITS_GE_512-NEXT: st1w { z1.s }, p0, [x0] 734; VBITS_GE_512-NEXT: ret 735 %op1 = load <16 x float>, ptr %a 736 %op2 = load <16 x float>, ptr %b 737 %ret = shufflevector <16 x float> %op1, <16 x float> %op2, <16 x i32> <i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, 738 i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30> 739 store <16 x float> %ret, ptr %a 740 ret void 741} 742 743define void @shuffle_ext_byone_v32f32(ptr %a, ptr %b) vscale_range(8,0) #0 { 744; CHECK-LABEL: shuffle_ext_byone_v32f32: 745; CHECK: // %bb.0: 746; CHECK-NEXT: ptrue p0.s, vl32 747; CHECK-NEXT: mov w8, #31 // =0x1f 748; CHECK-NEXT: whilels p1.s, xzr, x8 749; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] 750; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1] 751; CHECK-NEXT: lastb s0, p1, z0.s 752; CHECK-NEXT: insr z1.s, s0 753; CHECK-NEXT: st1w { z1.s }, p0, [x0] 754; CHECK-NEXT: ret 755 %op1 = load <32 x float>, ptr %a 756 %op2 = load <32 x float>, ptr %b 757 %ret = shufflevector <32 x float> %op1, <32 x float> %op2, <32 x i32> <i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, 758 i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, 759 i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, 760 i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62> 761 store <32 x float> %ret, ptr %a 762 ret void 763} 764 765define void @shuffle_ext_byone_v64f32(ptr %a, ptr %b) vscale_range(16,0) #0 { 766; CHECK-LABEL: shuffle_ext_byone_v64f32: 767; CHECK: // %bb.0: 768; CHECK-NEXT: ptrue p0.s, vl64 769; CHECK-NEXT: mov w8, #63 // =0x3f 770; CHECK-NEXT: whilels p1.s, xzr, x8 771; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] 772; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1] 773; CHECK-NEXT: lastb s0, p1, z0.s 774; CHECK-NEXT: insr z1.s, s0 775; CHECK-NEXT: st1w { z1.s }, p0, [x0] 776; CHECK-NEXT: ret 777 %op1 = load <64 x float>, ptr %a 778 %op2 = load <64 x float>, ptr %b 779 %ret = shufflevector <64 x float> %op1, <64 x float> %op2, <64 x i32> <i32 63, i32 64, i32 65, i32 66, i32 67, i32 68, i32 69, i32 70, 780 i32 71, i32 72, i32 73, i32 74, i32 75, i32 76, i32 77, i32 78, 781 i32 79, i32 80, i32 81, i32 82, i32 83, i32 84, i32 85, i32 86, 782 i32 87, i32 88, i32 89, i32 90, i32 91, i32 92, i32 93, i32 94, 783 i32 95, i32 96, i32 97, i32 98, i32 99, i32 100, i32 101, i32 102, 784 i32 103, i32 104, i32 105, i32 106, i32 107, i32 108, i32 109, i32 110, 785 i32 111, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, 786 i32 119, i32 120, i32 121, i32 122, i32 123, i32 124, i32 125, i32 126> 787 store <64 x float> %ret, ptr %a 788 ret void 789} 790 791; Don't use SVE for 128-bit vectors 792define <2 x double> @shuffle_ext_byone_v2f64(<2 x double> %op1, <2 x double> %op2) vscale_range(2,0) #0 { 793; CHECK-LABEL: shuffle_ext_byone_v2f64: 794; CHECK: // %bb.0: 795; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #8 796; CHECK-NEXT: ret 797 %ret = shufflevector <2 x double> %op1, <2 x double> %op2, <2 x i32> <i32 1, i32 2> 798 ret <2 x double> %ret 799} 800 801define void @shuffle_ext_byone_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 { 802; CHECK-LABEL: shuffle_ext_byone_v4f64: 803; CHECK: // %bb.0: 804; CHECK-NEXT: ptrue p0.d, vl4 805; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0] 806; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1] 807; CHECK-NEXT: mov z0.d, z0.d[3] 808; CHECK-NEXT: insr z1.d, d0 809; CHECK-NEXT: st1d { z1.d }, p0, [x0] 810; CHECK-NEXT: ret 811 %op1 = load <4 x double>, ptr %a 812 %op2 = load <4 x double>, ptr %b 813 %ret = shufflevector <4 x double> %op1, <4 x double> %op2, <4 x i32> <i32 3, i32 4, i32 5, i32 6> 814 store <4 x double> %ret, ptr %a 815 ret void 816} 817 818define void @shuffle_ext_byone_v8f64(ptr %a, ptr %b) #0 { 819; VBITS_GE_256-LABEL: shuffle_ext_byone_v8f64: 820; VBITS_GE_256: // %bb.0: 821; VBITS_GE_256-NEXT: ptrue p0.d, vl4 822; VBITS_GE_256-NEXT: mov x8, #4 // =0x4 823; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x1] 824; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x0, x8, lsl #3] 825; VBITS_GE_256-NEXT: ld1d { z2.d }, p0/z, [x1, x8, lsl #3] 826; VBITS_GE_256-NEXT: mov z3.d, z0.d[3] 827; VBITS_GE_256-NEXT: mov z1.d, z1.d[3] 828; VBITS_GE_256-NEXT: insr z2.d, d3 829; VBITS_GE_256-NEXT: insr z0.d, d1 830; VBITS_GE_256-NEXT: st1d { z2.d }, p0, [x0, x8, lsl #3] 831; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x0] 832; VBITS_GE_256-NEXT: ret 833; 834; VBITS_GE_512-LABEL: shuffle_ext_byone_v8f64: 835; VBITS_GE_512: // %bb.0: 836; VBITS_GE_512-NEXT: ptrue p0.d, vl8 837; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0] 838; VBITS_GE_512-NEXT: ld1d { z1.d }, p0/z, [x1] 839; VBITS_GE_512-NEXT: mov z0.d, z0.d[7] 840; VBITS_GE_512-NEXT: insr z1.d, d0 841; VBITS_GE_512-NEXT: st1d { z1.d }, p0, [x0] 842; VBITS_GE_512-NEXT: ret 843 %op1 = load <8 x double>, ptr %a 844 %op2 = load <8 x double>, ptr %b 845 %ret = shufflevector <8 x double> %op1, <8 x double> %op2, <8 x i32> <i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14> 846 store <8 x double> %ret, ptr %a 847 ret void 848} 849 850define void @shuffle_ext_byone_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 { 851; CHECK-LABEL: shuffle_ext_byone_v16f64: 852; CHECK: // %bb.0: 853; CHECK-NEXT: ptrue p0.d, vl16 854; CHECK-NEXT: mov w8, #15 // =0xf 855; CHECK-NEXT: whilels p1.d, xzr, x8 856; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0] 857; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1] 858; CHECK-NEXT: lastb d0, p1, z0.d 859; CHECK-NEXT: insr z1.d, d0 860; CHECK-NEXT: st1d { z1.d }, p0, [x0] 861; CHECK-NEXT: ret 862 %op1 = load <16 x double>, ptr %a 863 %op2 = load <16 x double>, ptr %b 864 %ret = shufflevector <16 x double> %op1, <16 x double> %op2, <16 x i32> <i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, 865 i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30> 866 store <16 x double> %ret, ptr %a 867 ret void 868} 869 870define void @shuffle_ext_byone_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 { 871; CHECK-LABEL: shuffle_ext_byone_v32f64: 872; CHECK: // %bb.0: 873; CHECK-NEXT: ptrue p0.d, vl32 874; CHECK-NEXT: mov w8, #31 // =0x1f 875; CHECK-NEXT: whilels p1.d, xzr, x8 876; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0] 877; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1] 878; CHECK-NEXT: lastb d0, p1, z0.d 879; CHECK-NEXT: insr z1.d, d0 880; CHECK-NEXT: st1d { z1.d }, p0, [x0] 881; CHECK-NEXT: ret 882 %op1 = load <32 x double>, ptr %a 883 %op2 = load <32 x double>, ptr %b 884 %ret = shufflevector <32 x double> %op1, <32 x double> %op2, <32 x i32> <i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, 885 i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, 886 i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, 887 i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62> 888 store <32 x double> %ret, ptr %a 889 ret void 890} 891 892define void @shuffle_ext_byone_reverse(ptr %a, ptr %b) vscale_range(2,0) #0 { 893; CHECK-LABEL: shuffle_ext_byone_reverse: 894; CHECK: // %bb.0: 895; CHECK-NEXT: ptrue p0.d, vl4 896; CHECK-NEXT: ld1d { z0.d }, p0/z, [x1] 897; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0] 898; CHECK-NEXT: mov z0.d, z0.d[3] 899; CHECK-NEXT: insr z1.d, d0 900; CHECK-NEXT: st1d { z1.d }, p0, [x0] 901; CHECK-NEXT: ret 902 %op1 = load <4 x double>, ptr %a 903 %op2 = load <4 x double>, ptr %b 904 %ret = shufflevector <4 x double> %op1, <4 x double> %op2, <4 x i32> <i32 7, i32 0, i32 1, i32 2> 905 store <4 x double> %ret, ptr %a 906 ret void 907} 908 909define void @shuffle_ext_invalid(ptr %a, ptr %b) vscale_range(2,0) #0 { 910; CHECK-LABEL: shuffle_ext_invalid: 911; CHECK: // %bb.0: 912; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill 913; CHECK-NEXT: sub x9, sp, #48 914; CHECK-NEXT: mov x29, sp 915; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0 916; CHECK-NEXT: .cfi_def_cfa w29, 16 917; CHECK-NEXT: .cfi_offset w30, -8 918; CHECK-NEXT: .cfi_offset w29, -16 919; CHECK-NEXT: ptrue p0.d, vl4 920; CHECK-NEXT: mov x8, sp 921; CHECK-NEXT: ld1d { z0.d }, p0/z, [x1] 922; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0] 923; CHECK-NEXT: mov z2.d, z0.d[1] 924; CHECK-NEXT: mov z3.d, z1.d[3] 925; CHECK-NEXT: mov z1.d, z1.d[2] 926; CHECK-NEXT: stp d0, d2, [sp, #16] 927; CHECK-NEXT: stp d1, d3, [sp] 928; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8] 929; CHECK-NEXT: st1d { z0.d }, p0, [x0] 930; CHECK-NEXT: mov sp, x29 931; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload 932; CHECK-NEXT: ret 933 %op1 = load <4 x double>, ptr %a 934 %op2 = load <4 x double>, ptr %b 935 %ret = shufflevector <4 x double> %op1, <4 x double> %op2, <4 x i32> <i32 2, i32 3, i32 4, i32 5> 936 store <4 x double> %ret, ptr %a 937 ret void 938} 939 940attributes #0 = { "target-features"="+sve" } 941