1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s | FileCheck %s 3 4target triple = "aarch64-unknown-linux-gnu" 5 6; Currently there is no custom lowering for vector shuffles operating on types 7; bigger than NEON. However, having no support opens us up to a code generator 8; hang when expanding BUILD_VECTOR. Here we just validate the promblematic case 9; successfully exits code generation. 10define void @hang_when_merging_stores_after_legalisation(ptr %a, <2 x i32> %b) vscale_range(2,2) #0 { 11; CHECK-LABEL: hang_when_merging_stores_after_legalisation: 12; CHECK: // %bb.0: 13; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 14; CHECK-NEXT: mov z0.s, s0 15; CHECK-NEXT: mov z1.d, z0.d 16; CHECK-NEXT: ext z1.b, z1.b, z1.b, #16 17; CHECK-NEXT: st2 { v0.4s, v1.4s }, [x0] 18; CHECK-NEXT: ret 19 %splat = shufflevector <2 x i32> %b, <2 x i32> undef, <8 x i32> zeroinitializer 20 %interleaved.vec = shufflevector <8 x i32> %splat, <8 x i32> undef, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7> 21 store <8 x i32> %interleaved.vec, ptr %a, align 4 22 ret void 23} 24 25; Ensure we don't crash when trying to lower a shuffle via an extract 26define void @crash_when_lowering_extract_shuffle(ptr %dst, i1 %cond) vscale_range(2,2) #0 { 27; CHECK-LABEL: crash_when_lowering_extract_shuffle: 28; CHECK: // %bb.0: 29; CHECK-NEXT: tbnz w1, #0, .LBB1_2 30; CHECK-NEXT: // %bb.1: // %vector.body 31; CHECK-NEXT: mov z0.b, #0 // =0x0 32; CHECK-NEXT: ptrue p0.s 33; CHECK-NEXT: mov x9, #8 // =0x8 34; CHECK-NEXT: mov x10, #24 // =0x18 35; CHECK-NEXT: umov w8, v0.b[8] 36; CHECK-NEXT: mov v1.16b, v0.16b 37; CHECK-NEXT: mov v1.b[1], v0.b[1] 38; CHECK-NEXT: fmov s2, w8 39; CHECK-NEXT: mov x8, #16 // =0x10 40; CHECK-NEXT: mov v2.b[1], v0.b[9] 41; CHECK-NEXT: mov v1.b[2], v0.b[2] 42; CHECK-NEXT: mov v2.b[2], v0.b[10] 43; CHECK-NEXT: mov v1.b[3], v0.b[3] 44; CHECK-NEXT: mov v2.b[3], v0.b[11] 45; CHECK-NEXT: mov v1.b[4], v0.b[4] 46; CHECK-NEXT: mov v2.b[4], v0.b[12] 47; CHECK-NEXT: mov v1.b[5], v0.b[5] 48; CHECK-NEXT: mov v2.b[5], v0.b[13] 49; CHECK-NEXT: mov v1.b[6], v0.b[6] 50; CHECK-NEXT: mov v2.b[6], v0.b[14] 51; CHECK-NEXT: mov v1.b[7], v0.b[7] 52; CHECK-NEXT: mov v2.b[7], v0.b[15] 53; CHECK-NEXT: ext z0.b, z0.b, z0.b, #16 54; CHECK-NEXT: uunpklo z1.h, z1.b 55; CHECK-NEXT: ext v3.16b, v0.16b, v0.16b, #8 56; CHECK-NEXT: uunpklo z0.h, z0.b 57; CHECK-NEXT: uunpklo z2.h, z2.b 58; CHECK-NEXT: uunpklo z1.s, z1.h 59; CHECK-NEXT: uunpklo z3.h, z3.b 60; CHECK-NEXT: uunpklo z0.s, z0.h 61; CHECK-NEXT: uunpklo z2.s, z2.h 62; CHECK-NEXT: lsl z1.s, z1.s, #31 63; CHECK-NEXT: uunpklo z3.s, z3.h 64; CHECK-NEXT: lsl z0.s, z0.s, #31 65; CHECK-NEXT: asr z1.s, z1.s, #31 66; CHECK-NEXT: lsl z2.s, z2.s, #31 67; CHECK-NEXT: asr z0.s, z0.s, #31 68; CHECK-NEXT: and z1.s, z1.s, #0x1 69; CHECK-NEXT: lsl z3.s, z3.s, #31 70; CHECK-NEXT: asr z2.s, z2.s, #31 71; CHECK-NEXT: and z0.s, z0.s, #0x1 72; CHECK-NEXT: cmpne p4.s, p0/z, z1.s, #0 73; CHECK-NEXT: ld1w { z1.s }, p0/z, [x0] 74; CHECK-NEXT: asr z3.s, z3.s, #31 75; CHECK-NEXT: and z2.s, z2.s, #0x1 76; CHECK-NEXT: cmpne p1.s, p0/z, z0.s, #0 77; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2] 78; CHECK-NEXT: and z3.s, z3.s, #0x1 79; CHECK-NEXT: cmpne p2.s, p0/z, z2.s, #0 80; CHECK-NEXT: ld1w { z2.s }, p0/z, [x0, x9, lsl #2] 81; CHECK-NEXT: mov z1.s, p4/m, #0 // =0x0 82; CHECK-NEXT: cmpne p3.s, p0/z, z3.s, #0 83; CHECK-NEXT: ld1w { z3.s }, p0/z, [x0, x10, lsl #2] 84; CHECK-NEXT: mov z0.s, p1/m, #0 // =0x0 85; CHECK-NEXT: mov z2.s, p2/m, #0 // =0x0 86; CHECK-NEXT: st1w { z1.s }, p0, [x0] 87; CHECK-NEXT: st1w { z0.s }, p0, [x0, x8, lsl #2] 88; CHECK-NEXT: mov z3.s, p3/m, #0 // =0x0 89; CHECK-NEXT: st1w { z2.s }, p0, [x0, x9, lsl #2] 90; CHECK-NEXT: st1w { z3.s }, p0, [x0, x10, lsl #2] 91; CHECK-NEXT: .LBB1_2: // %exit 92; CHECK-NEXT: ret 93 %broadcast.splat = shufflevector <32 x i1> zeroinitializer, <32 x i1> zeroinitializer, <32 x i32> zeroinitializer 94 br i1 %cond, label %exit, label %vector.body 95 96vector.body: 97 %1 = load <32 x i32>, ptr %dst, align 16 98 %predphi = select <32 x i1> %broadcast.splat, <32 x i32> zeroinitializer, <32 x i32> %1 99 store <32 x i32> %predphi, ptr %dst, align 16 100 br label %exit 101 102exit: 103 ret void 104} 105 106attributes #0 = { "target-features"="+sve" } 107