xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-fixed-length-no-vscale-range.ll (revision db158c7c830807caeeb0691739c41f1d522029e9)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s | FileCheck %s
3
4target triple = "aarch64-unknown-linux-gnu"
5
6define <2 x i64> @mul_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
7; CHECK-LABEL: mul_v2i64:
8; CHECK:       // %bb.0:
9; CHECK-NEXT:    ptrue p0.d, vl2
10; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
11; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
12; CHECK-NEXT:    mul z0.d, p0/m, z0.d, z1.d
13; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
14; CHECK-NEXT:    ret
15  %res = mul <2 x i64> %op1, %op2
16  ret <2 x i64> %res
17}
18
19define <4 x i32> @sdiv_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
20; CHECK-LABEL: sdiv_v4i32:
21; CHECK:       // %bb.0:
22; CHECK-NEXT:    ptrue p0.s, vl4
23; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
24; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
25; CHECK-NEXT:    sdiv z0.s, p0/m, z0.s, z1.s
26; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
27; CHECK-NEXT:    ret
28  %res = sdiv <4 x i32> %op1, %op2
29  ret <4 x i32> %res
30}
31
32attributes #0 = { "target-features"="+sve" }
33