1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mattr=+sve -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s 3target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" 4target triple = "aarch64-unknown-linux-gnu" 5 6define <4 x i32> @test(ptr %arg1, ptr %arg2) { 7; CHECK-LABEL: test: 8; CHECK: // %bb.0: // %entry 9; CHECK-NEXT: ptrue p0.s, vl8 10; CHECK-NEXT: mov x8, #8 // =0x8 11; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2] 12; CHECK-NEXT: ld1w { z2.s }, p0/z, [x0] 13; CHECK-NEXT: add z1.s, z0.s, z0.s 14; CHECK-NEXT: ext z0.b, z0.b, z0.b, #16 15; CHECK-NEXT: add z2.s, z2.s, z2.s 16; CHECK-NEXT: dup v0.4s, v0.s[2] 17; CHECK-NEXT: st1w { z1.s }, p0, [x0, x8, lsl #2] 18; CHECK-NEXT: st1w { z2.s }, p0, [x0] 19; CHECK-NEXT: ret 20entry: 21 %0 = load <16 x i32>, ptr %arg1, align 256 22 %1 = load <16 x i32>, ptr %arg2, align 256 23 %shvec = shufflevector <16 x i32> %0, <16 x i32> %1, <4 x i32> <i32 14, i32 14, i32 14, i32 14> 24 %2 = add <16 x i32> %0, %0 25 store <16 x i32> %2, ptr %arg1, align 256 26 ret <4 x i32> %shvec 27} 28 29define <2 x i32> @test2(ptr %arg1, ptr %arg2) { 30; CHECK-LABEL: test2: 31; CHECK: // %bb.0: // %entry 32; CHECK-NEXT: ptrue p0.s, vl8 33; CHECK-NEXT: mov x8, #8 // =0x8 34; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2] 35; CHECK-NEXT: ld1w { z2.s }, p0/z, [x0] 36; CHECK-NEXT: add z1.s, z0.s, z0.s 37; CHECK-NEXT: ext z0.b, z0.b, z0.b, #24 38; CHECK-NEXT: add z2.s, z2.s, z2.s 39; CHECK-NEXT: dup v0.2s, v0.s[0] 40; CHECK-NEXT: st1w { z1.s }, p0, [x0, x8, lsl #2] 41; CHECK-NEXT: st1w { z2.s }, p0, [x0] 42; CHECK-NEXT: ret 43entry: 44 %0 = load <16 x i32>, ptr %arg1, align 256 45 %1 = load <16 x i32>, ptr %arg2, align 256 46 %shvec = shufflevector <16 x i32> %0, <16 x i32> %1, <2 x i32> <i32 14, i32 14> 47 %2 = add <16 x i32> %0, %0 48 store <16 x i32> %2, ptr %arg1, align 256 49 ret <2 x i32> %shvec 50} 51