1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256 3; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512 4; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512 5 6target triple = "aarch64-unknown-linux-gnu" 7 8; 9; insertelement 10; 11 12; Don't use SVE for 64-bit vectors. 13define <4 x half> @insertelement_v4f16(<4 x half> %op1) vscale_range(2,0) #0 { 14; CHECK-LABEL: insertelement_v4f16: 15; CHECK: // %bb.0: 16; CHECK-NEXT: fmov h1, #5.00000000 17; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 18; CHECK-NEXT: mov v0.h[3], v1.h[0] 19; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 20; CHECK-NEXT: ret 21 %r = insertelement <4 x half> %op1, half 5.0, i64 3 22 ret <4 x half> %r 23} 24 25; Don't use SVE for 128-bit vectors. 26define <8 x half> @insertelement_v8f16(<8 x half> %op1) vscale_range(2,0) #0 { 27; CHECK-LABEL: insertelement_v8f16: 28; CHECK: // %bb.0: 29; CHECK-NEXT: fmov h1, #5.00000000 30; CHECK-NEXT: mov v0.h[7], v1.h[0] 31; CHECK-NEXT: ret 32 %r = insertelement <8 x half> %op1, half 5.0, i64 7 33 ret <8 x half> %r 34} 35 36define void @insertelement_v16f16(ptr %a, ptr %b) vscale_range(2,0) #0 { 37; CHECK-LABEL: insertelement_v16f16: 38; CHECK: // %bb.0: 39; CHECK-NEXT: mov w8, #15 // =0xf 40; CHECK-NEXT: index z0.h, #0, #1 41; CHECK-NEXT: ptrue p0.h 42; CHECK-NEXT: mov z1.h, w8 43; CHECK-NEXT: ptrue p1.h, vl16 44; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, z1.h 45; CHECK-NEXT: ld1h { z0.h }, p1/z, [x0] 46; CHECK-NEXT: fmov h1, #5.00000000 47; CHECK-NEXT: mov z0.h, p0/m, h1 48; CHECK-NEXT: st1h { z0.h }, p1, [x1] 49; CHECK-NEXT: ret 50 %op1 = load <16 x half>, ptr %a 51 %r = insertelement <16 x half> %op1, half 5.0, i64 15 52 store <16 x half> %r, ptr %b 53 ret void 54} 55 56define void @insertelement_v32f16(ptr %a, ptr %b) #0 { 57; VBITS_GE_256-LABEL: insertelement_v32f16: 58; VBITS_GE_256: // %bb.0: 59; VBITS_GE_256-NEXT: mov w8, #15 // =0xf 60; VBITS_GE_256-NEXT: index z0.h, #0, #1 61; VBITS_GE_256-NEXT: ptrue p0.h 62; VBITS_GE_256-NEXT: mov z1.h, w8 63; VBITS_GE_256-NEXT: ptrue p1.h, vl16 64; VBITS_GE_256-NEXT: mov x8, #16 // =0x10 65; VBITS_GE_256-NEXT: cmpeq p0.h, p0/z, z0.h, z1.h 66; VBITS_GE_256-NEXT: fmov h0, #5.00000000 67; VBITS_GE_256-NEXT: ld1h { z1.h }, p1/z, [x0, x8, lsl #1] 68; VBITS_GE_256-NEXT: mov z1.h, p0/m, h0 69; VBITS_GE_256-NEXT: ld1h { z0.h }, p1/z, [x0] 70; VBITS_GE_256-NEXT: st1h { z1.h }, p1, [x1, x8, lsl #1] 71; VBITS_GE_256-NEXT: st1h { z0.h }, p1, [x1] 72; VBITS_GE_256-NEXT: ret 73; 74; VBITS_GE_512-LABEL: insertelement_v32f16: 75; VBITS_GE_512: // %bb.0: 76; VBITS_GE_512-NEXT: mov w8, #31 // =0x1f 77; VBITS_GE_512-NEXT: index z0.h, #0, #1 78; VBITS_GE_512-NEXT: ptrue p0.h 79; VBITS_GE_512-NEXT: mov z1.h, w8 80; VBITS_GE_512-NEXT: ptrue p1.h, vl32 81; VBITS_GE_512-NEXT: cmpeq p0.h, p0/z, z0.h, z1.h 82; VBITS_GE_512-NEXT: ld1h { z0.h }, p1/z, [x0] 83; VBITS_GE_512-NEXT: fmov h1, #5.00000000 84; VBITS_GE_512-NEXT: mov z0.h, p0/m, h1 85; VBITS_GE_512-NEXT: st1h { z0.h }, p1, [x1] 86; VBITS_GE_512-NEXT: ret 87 %op1 = load <32 x half>, ptr %a 88 %r = insertelement <32 x half> %op1, half 5.0, i64 31 89 store <32 x half> %r, ptr %b 90 ret void 91} 92 93define void @insertelement_v64f16(ptr %a, ptr %b) vscale_range(8,0) #0 { 94; CHECK-LABEL: insertelement_v64f16: 95; CHECK: // %bb.0: 96; CHECK-NEXT: mov w8, #63 // =0x3f 97; CHECK-NEXT: index z0.h, #0, #1 98; CHECK-NEXT: ptrue p0.h 99; CHECK-NEXT: mov z1.h, w8 100; CHECK-NEXT: ptrue p1.h, vl64 101; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, z1.h 102; CHECK-NEXT: ld1h { z0.h }, p1/z, [x0] 103; CHECK-NEXT: fmov h1, #5.00000000 104; CHECK-NEXT: mov z0.h, p0/m, h1 105; CHECK-NEXT: st1h { z0.h }, p1, [x1] 106; CHECK-NEXT: ret 107 %op1 = load <64 x half>, ptr %a 108 %r = insertelement <64 x half> %op1, half 5.0, i64 63 109 store <64 x half> %r, ptr %b 110 ret void 111} 112 113define void @insertelement_v128f16(ptr %a, ptr %b) vscale_range(16,0) #0 { 114; CHECK-LABEL: insertelement_v128f16: 115; CHECK: // %bb.0: 116; CHECK-NEXT: mov w8, #127 // =0x7f 117; CHECK-NEXT: index z0.h, #0, #1 118; CHECK-NEXT: ptrue p0.h 119; CHECK-NEXT: mov z1.h, w8 120; CHECK-NEXT: ptrue p1.h, vl128 121; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, z1.h 122; CHECK-NEXT: ld1h { z0.h }, p1/z, [x0] 123; CHECK-NEXT: fmov h1, #5.00000000 124; CHECK-NEXT: mov z0.h, p0/m, h1 125; CHECK-NEXT: st1h { z0.h }, p1, [x1] 126; CHECK-NEXT: ret 127 %op1 = load <128 x half>, ptr %a 128 %r = insertelement <128 x half> %op1, half 5.0, i64 127 129 store <128 x half> %r, ptr %b 130 ret void 131} 132 133; Don't use SVE for 64-bit vectors. 134define <2 x float> @insertelement_v2f32(<2 x float> %op1) vscale_range(2,0) #0 { 135; CHECK-LABEL: insertelement_v2f32: 136; CHECK: // %bb.0: 137; CHECK-NEXT: fmov s1, #5.00000000 138; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 139; CHECK-NEXT: mov v0.s[1], v1.s[0] 140; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 141; CHECK-NEXT: ret 142 %r = insertelement <2 x float> %op1, float 5.0, i64 1 143 ret <2 x float> %r 144} 145 146; Don't use SVE for 128-bit vectors. 147define <4 x float> @insertelement_v4f32(<4 x float> %op1) vscale_range(2,0) #0 { 148; CHECK-LABEL: insertelement_v4f32: 149; CHECK: // %bb.0: 150; CHECK-NEXT: fmov s1, #5.00000000 151; CHECK-NEXT: mov v0.s[3], v1.s[0] 152; CHECK-NEXT: ret 153 %r = insertelement <4 x float> %op1, float 5.0, i64 3 154 ret <4 x float> %r 155} 156 157define void @insertelement_v8f32(ptr %a, ptr %b) vscale_range(2,0) #0 { 158; CHECK-LABEL: insertelement_v8f32: 159; CHECK: // %bb.0: 160; CHECK-NEXT: mov w8, #7 // =0x7 161; CHECK-NEXT: index z0.s, #0, #1 162; CHECK-NEXT: ptrue p0.s 163; CHECK-NEXT: mov z1.s, w8 164; CHECK-NEXT: ptrue p1.s, vl8 165; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, z1.s 166; CHECK-NEXT: ld1w { z0.s }, p1/z, [x0] 167; CHECK-NEXT: fmov s1, #5.00000000 168; CHECK-NEXT: mov z0.s, p0/m, s1 169; CHECK-NEXT: st1w { z0.s }, p1, [x1] 170; CHECK-NEXT: ret 171 %op1 = load <8 x float>, ptr %a 172 %r = insertelement <8 x float> %op1, float 5.0, i64 7 173 store <8 x float> %r, ptr %b 174 ret void 175} 176 177define void @insertelement_v16f32(ptr %a, ptr %b) #0 { 178; VBITS_GE_256-LABEL: insertelement_v16f32: 179; VBITS_GE_256: // %bb.0: 180; VBITS_GE_256-NEXT: mov w8, #7 // =0x7 181; VBITS_GE_256-NEXT: index z0.s, #0, #1 182; VBITS_GE_256-NEXT: ptrue p0.s 183; VBITS_GE_256-NEXT: mov z1.s, w8 184; VBITS_GE_256-NEXT: ptrue p1.s, vl8 185; VBITS_GE_256-NEXT: mov x8, #8 // =0x8 186; VBITS_GE_256-NEXT: cmpeq p0.s, p0/z, z0.s, z1.s 187; VBITS_GE_256-NEXT: fmov s0, #5.00000000 188; VBITS_GE_256-NEXT: ld1w { z1.s }, p1/z, [x0, x8, lsl #2] 189; VBITS_GE_256-NEXT: mov z1.s, p0/m, s0 190; VBITS_GE_256-NEXT: ld1w { z0.s }, p1/z, [x0] 191; VBITS_GE_256-NEXT: st1w { z1.s }, p1, [x1, x8, lsl #2] 192; VBITS_GE_256-NEXT: st1w { z0.s }, p1, [x1] 193; VBITS_GE_256-NEXT: ret 194; 195; VBITS_GE_512-LABEL: insertelement_v16f32: 196; VBITS_GE_512: // %bb.0: 197; VBITS_GE_512-NEXT: mov w8, #15 // =0xf 198; VBITS_GE_512-NEXT: index z0.s, #0, #1 199; VBITS_GE_512-NEXT: ptrue p0.s 200; VBITS_GE_512-NEXT: mov z1.s, w8 201; VBITS_GE_512-NEXT: ptrue p1.s, vl16 202; VBITS_GE_512-NEXT: cmpeq p0.s, p0/z, z0.s, z1.s 203; VBITS_GE_512-NEXT: ld1w { z0.s }, p1/z, [x0] 204; VBITS_GE_512-NEXT: fmov s1, #5.00000000 205; VBITS_GE_512-NEXT: mov z0.s, p0/m, s1 206; VBITS_GE_512-NEXT: st1w { z0.s }, p1, [x1] 207; VBITS_GE_512-NEXT: ret 208 %op1 = load <16 x float>, ptr %a 209 %r = insertelement <16 x float> %op1, float 5.0, i64 15 210 store <16 x float> %r, ptr %b 211 ret void 212} 213 214define void @insertelement_v32f32(ptr %a, ptr %b) vscale_range(8,0) #0 { 215; CHECK-LABEL: insertelement_v32f32: 216; CHECK: // %bb.0: 217; CHECK-NEXT: mov w8, #31 // =0x1f 218; CHECK-NEXT: index z0.s, #0, #1 219; CHECK-NEXT: ptrue p0.s 220; CHECK-NEXT: mov z1.s, w8 221; CHECK-NEXT: ptrue p1.s, vl32 222; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, z1.s 223; CHECK-NEXT: ld1w { z0.s }, p1/z, [x0] 224; CHECK-NEXT: fmov s1, #5.00000000 225; CHECK-NEXT: mov z0.s, p0/m, s1 226; CHECK-NEXT: st1w { z0.s }, p1, [x1] 227; CHECK-NEXT: ret 228 %op1 = load <32 x float>, ptr %a 229 %r = insertelement <32 x float> %op1, float 5.0, i64 31 230 store <32 x float> %r, ptr %b 231 ret void 232} 233 234define void @insertelement_v64f32(ptr %a, ptr %b) vscale_range(16,0) #0 { 235; CHECK-LABEL: insertelement_v64f32: 236; CHECK: // %bb.0: 237; CHECK-NEXT: mov w8, #63 // =0x3f 238; CHECK-NEXT: index z0.s, #0, #1 239; CHECK-NEXT: ptrue p0.s 240; CHECK-NEXT: mov z1.s, w8 241; CHECK-NEXT: ptrue p1.s, vl64 242; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, z1.s 243; CHECK-NEXT: ld1w { z0.s }, p1/z, [x0] 244; CHECK-NEXT: fmov s1, #5.00000000 245; CHECK-NEXT: mov z0.s, p0/m, s1 246; CHECK-NEXT: st1w { z0.s }, p1, [x1] 247; CHECK-NEXT: ret 248 %op1 = load <64 x float>, ptr %a 249 %r = insertelement <64 x float> %op1, float 5.0, i64 63 250 store <64 x float> %r, ptr %b 251 ret void 252} 253 254; Don't use SVE for 64-bit vectors. 255define <1 x double> @insertelement_v1f64(<1 x double> %op1) vscale_range(2,0) #0 { 256; CHECK-LABEL: insertelement_v1f64: 257; CHECK: // %bb.0: 258; CHECK-NEXT: mov x8, #4617315517961601024 // =0x4014000000000000 259; CHECK-NEXT: fmov d0, x8 260; CHECK-NEXT: ret 261 %r = insertelement <1 x double> %op1, double 5.0, i64 0 262 ret <1 x double> %r 263} 264 265; Don't use SVE for 128-bit vectors. 266define <2 x double> @insertelement_v2f64(<2 x double> %op1) vscale_range(2,0) #0 { 267; CHECK-LABEL: insertelement_v2f64: 268; CHECK: // %bb.0: 269; CHECK-NEXT: fmov d1, #5.00000000 270; CHECK-NEXT: mov v0.d[1], v1.d[0] 271; CHECK-NEXT: ret 272 %r = insertelement <2 x double> %op1, double 5.0, i64 1 273 ret <2 x double> %r 274} 275 276define void @insertelement_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 { 277; CHECK-LABEL: insertelement_v4f64: 278; CHECK: // %bb.0: 279; CHECK-NEXT: mov w8, #3 // =0x3 280; CHECK-NEXT: index z0.d, #0, #1 281; CHECK-NEXT: ptrue p0.d 282; CHECK-NEXT: mov z1.d, x8 283; CHECK-NEXT: ptrue p1.d, vl4 284; CHECK-NEXT: cmpeq p0.d, p0/z, z0.d, z1.d 285; CHECK-NEXT: ld1d { z0.d }, p1/z, [x0] 286; CHECK-NEXT: fmov d1, #5.00000000 287; CHECK-NEXT: mov z0.d, p0/m, d1 288; CHECK-NEXT: st1d { z0.d }, p1, [x1] 289; CHECK-NEXT: ret 290 %op1 = load <4 x double>, ptr %a 291 %r = insertelement <4 x double> %op1, double 5.0, i64 3 292 store <4 x double> %r, ptr %b 293 ret void 294} 295 296define void @insertelement_v8f64(ptr %a, ptr %b) #0 { 297; VBITS_GE_256-LABEL: insertelement_v8f64: 298; VBITS_GE_256: // %bb.0: 299; VBITS_GE_256-NEXT: mov w8, #3 // =0x3 300; VBITS_GE_256-NEXT: index z0.d, #0, #1 301; VBITS_GE_256-NEXT: ptrue p0.d 302; VBITS_GE_256-NEXT: mov z1.d, x8 303; VBITS_GE_256-NEXT: ptrue p1.d, vl4 304; VBITS_GE_256-NEXT: mov x8, #4 // =0x4 305; VBITS_GE_256-NEXT: cmpeq p0.d, p0/z, z0.d, z1.d 306; VBITS_GE_256-NEXT: fmov d0, #5.00000000 307; VBITS_GE_256-NEXT: ld1d { z1.d }, p1/z, [x0, x8, lsl #3] 308; VBITS_GE_256-NEXT: mov z1.d, p0/m, d0 309; VBITS_GE_256-NEXT: ld1d { z0.d }, p1/z, [x0] 310; VBITS_GE_256-NEXT: st1d { z1.d }, p1, [x1, x8, lsl #3] 311; VBITS_GE_256-NEXT: st1d { z0.d }, p1, [x1] 312; VBITS_GE_256-NEXT: ret 313; 314; VBITS_GE_512-LABEL: insertelement_v8f64: 315; VBITS_GE_512: // %bb.0: 316; VBITS_GE_512-NEXT: mov w8, #7 // =0x7 317; VBITS_GE_512-NEXT: index z0.d, #0, #1 318; VBITS_GE_512-NEXT: ptrue p0.d 319; VBITS_GE_512-NEXT: mov z1.d, x8 320; VBITS_GE_512-NEXT: ptrue p1.d, vl8 321; VBITS_GE_512-NEXT: cmpeq p0.d, p0/z, z0.d, z1.d 322; VBITS_GE_512-NEXT: ld1d { z0.d }, p1/z, [x0] 323; VBITS_GE_512-NEXT: fmov d1, #5.00000000 324; VBITS_GE_512-NEXT: mov z0.d, p0/m, d1 325; VBITS_GE_512-NEXT: st1d { z0.d }, p1, [x1] 326; VBITS_GE_512-NEXT: ret 327 %op1 = load <8 x double>, ptr %a 328 %r = insertelement <8 x double> %op1, double 5.0, i64 7 329 store <8 x double> %r, ptr %b 330 ret void 331} 332 333define void @insertelement_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 { 334; CHECK-LABEL: insertelement_v16f64: 335; CHECK: // %bb.0: 336; CHECK-NEXT: mov w8, #15 // =0xf 337; CHECK-NEXT: index z0.d, #0, #1 338; CHECK-NEXT: ptrue p0.d 339; CHECK-NEXT: mov z1.d, x8 340; CHECK-NEXT: ptrue p1.d, vl16 341; CHECK-NEXT: cmpeq p0.d, p0/z, z0.d, z1.d 342; CHECK-NEXT: ld1d { z0.d }, p1/z, [x0] 343; CHECK-NEXT: fmov d1, #5.00000000 344; CHECK-NEXT: mov z0.d, p0/m, d1 345; CHECK-NEXT: st1d { z0.d }, p1, [x1] 346; CHECK-NEXT: ret 347 %op1 = load <16 x double>, ptr %a 348 %r = insertelement <16 x double> %op1, double 5.0, i64 15 349 store <16 x double> %r, ptr %b 350 ret void 351} 352 353define void @insertelement_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 { 354; CHECK-LABEL: insertelement_v32f64: 355; CHECK: // %bb.0: 356; CHECK-NEXT: mov w8, #31 // =0x1f 357; CHECK-NEXT: index z0.d, #0, #1 358; CHECK-NEXT: ptrue p0.d 359; CHECK-NEXT: mov z1.d, x8 360; CHECK-NEXT: ptrue p1.d, vl32 361; CHECK-NEXT: cmpeq p0.d, p0/z, z0.d, z1.d 362; CHECK-NEXT: ld1d { z0.d }, p1/z, [x0] 363; CHECK-NEXT: fmov d1, #5.00000000 364; CHECK-NEXT: mov z0.d, p0/m, d1 365; CHECK-NEXT: st1d { z0.d }, p1, [x1] 366; CHECK-NEXT: ret 367 %op1 = load <32 x double>, ptr %a 368 %r = insertelement <32 x double> %op1, double 5.0, i64 31 369 store <32 x double> %r, ptr %b 370 ret void 371} 372 373attributes #0 = { "target-features"="+sve" } 374