1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 2; RUN: llc < %s | FileCheck %s 3; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s 4; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s 5 6target triple = "aarch64-unknown-linux-gnu" 7 8define <32 x i8> @test_v32i8(<32 x i8> %unused, <32 x i8> %a) #0 { 9; CHECK-LABEL: test_v32i8: 10; CHECK: // %bb.0: 11; CHECK-NEXT: mov v1.16b, v3.16b 12; CHECK-NEXT: mov v0.16b, v2.16b 13; CHECK-NEXT: ret 14 ret <32 x i8> %a 15} 16 17define <16 x i16> @test_v16i16(<16 x i16> %unused, <16 x i16> %a) #0 { 18; CHECK-LABEL: test_v16i16: 19; CHECK: // %bb.0: 20; CHECK-NEXT: mov v1.16b, v3.16b 21; CHECK-NEXT: mov v0.16b, v2.16b 22; CHECK-NEXT: ret 23 ret <16 x i16> %a 24} 25 26define <8 x i32> @test_v8i32(<8 x i32> %unused, <8 x i32> %a) #0 { 27; CHECK-LABEL: test_v8i32: 28; CHECK: // %bb.0: 29; CHECK-NEXT: mov v1.16b, v3.16b 30; CHECK-NEXT: mov v0.16b, v2.16b 31; CHECK-NEXT: ret 32 ret <8 x i32> %a 33} 34 35define <4 x i64> @test_v4i64(<4 x i64> %unused, <4 x i64> %a) #0 { 36; CHECK-LABEL: test_v4i64: 37; CHECK: // %bb.0: 38; CHECK-NEXT: mov v1.16b, v3.16b 39; CHECK-NEXT: mov v0.16b, v2.16b 40; CHECK-NEXT: ret 41 ret <4 x i64> %a 42} 43 44define <16 x half> @test_v16f16(<16 x half> %unused, <16 x half> %a) #0 { 45; CHECK-LABEL: test_v16f16: 46; CHECK: // %bb.0: 47; CHECK-NEXT: mov v1.16b, v3.16b 48; CHECK-NEXT: mov v0.16b, v2.16b 49; CHECK-NEXT: ret 50 ret <16 x half> %a 51} 52 53define <8 x float> @test_v8f32(<8 x float> %unused, <8 x float> %a) #0 { 54; CHECK-LABEL: test_v8f32: 55; CHECK: // %bb.0: 56; CHECK-NEXT: mov v1.16b, v3.16b 57; CHECK-NEXT: mov v0.16b, v2.16b 58; CHECK-NEXT: ret 59 ret <8 x float> %a 60} 61 62define <4 x double> @test_v4f64(<4 x double> %unused, <4 x double> %a) #0 { 63; CHECK-LABEL: test_v4f64: 64; CHECK: // %bb.0: 65; CHECK-NEXT: mov v1.16b, v3.16b 66; CHECK-NEXT: mov v0.16b, v2.16b 67; CHECK-NEXT: ret 68 ret <4 x double> %a 69} 70 71define <16 x bfloat> @test_v16bf16(<16 x bfloat> %unused, <16 x bfloat> %a) #0 { 72; CHECK-LABEL: test_v16bf16: 73; CHECK: // %bb.0: 74; CHECK-NEXT: mov v1.16b, v3.16b 75; CHECK-NEXT: mov v0.16b, v2.16b 76; CHECK-NEXT: ret 77 ret <16 x bfloat> %a 78} 79 80define <3 x i64> @test_v3i64(<3 x i64> %unused, <3 x i64> %a) #0 { 81; CHECK-LABEL: test_v3i64: 82; CHECK: // %bb.0: 83; CHECK-NEXT: fmov d2, d5 84; CHECK-NEXT: fmov d1, d4 85; CHECK-NEXT: fmov d0, d3 86; CHECK-NEXT: ret 87 ret <3 x i64> %a 88} 89 90define <5 x i64> @test_v5i64(<5 x i64> %unused, <5 x i64> %a) #0 { 91; CHECK-LABEL: test_v5i64: 92; CHECK: // %bb.0: 93; CHECK-NEXT: fmov d1, d6 94; CHECK-NEXT: fmov d0, d5 95; CHECK-NEXT: fmov d2, d7 96; CHECK-NEXT: ldp d3, d4, [sp] 97; CHECK-NEXT: ret 98 ret <5 x i64> %a 99} 100 101define <1 x i16> @test_v1i16(<1 x i16> %unused, <1 x i16> %a) #0 { 102; CHECK-LABEL: test_v1i16: 103; CHECK: // %bb.0: 104; CHECK-NEXT: fmov d0, d1 105; CHECK-NEXT: ret 106 ret <1 x i16> %a 107} 108 109define <9 x i16> @test_v9i16(<9 x i16> %unused, <9 x i16> %a) #0 { 110; CHECK-LABEL: test_v9i16: 111; CHECK: // %bb.0: 112; CHECK-NEXT: ldr h0, [sp, #8] 113; CHECK-NEXT: add x9, sp, #16 114; CHECK-NEXT: ld1 { v0.h }[1], [x9] 115; CHECK-NEXT: add x9, sp, #24 116; CHECK-NEXT: ld1 { v0.h }[2], [x9] 117; CHECK-NEXT: add x9, sp, #32 118; CHECK-NEXT: ld1 { v0.h }[3], [x9] 119; CHECK-NEXT: add x9, sp, #40 120; CHECK-NEXT: ld1 { v0.h }[4], [x9] 121; CHECK-NEXT: add x9, sp, #48 122; CHECK-NEXT: ld1 { v0.h }[5], [x9] 123; CHECK-NEXT: add x9, sp, #56 124; CHECK-NEXT: ld1 { v0.h }[6], [x9] 125; CHECK-NEXT: add x9, sp, #64 126; CHECK-NEXT: ld1 { v0.h }[7], [x9] 127; CHECK-NEXT: ldrh w9, [sp, #72] 128; CHECK-NEXT: strh w9, [x8, #16] 129; CHECK-NEXT: str q0, [x8] 130; CHECK-NEXT: ret 131 ret <9 x i16> %a 132} 133 134define <16 x i1> @test_v16i1(<16 x i1> %unused, <16 x i1> %a) #0 { 135; CHECK-LABEL: test_v16i1: 136; CHECK: // %bb.0: 137; CHECK-NEXT: mov v0.16b, v1.16b 138; CHECK-NEXT: ret 139 ret <16 x i1> %a 140} 141 142; UTC_ARGS: --disable 143; The output from this test is large and generally not useful, what matters is 144; no vector registers are used. 145define <32 x i1> @test_v32i1(<32 x i1> %unused, <32 x i1> %a) #0 { 146; CHECK-LABEL: test_v32i1: 147; CHECK: // %bb.0: 148; CHECK-NOT: [q,v,z][0-9]+ 149; CHECK: ret 150 ret <32 x i1> %a 151} 152; UTC_ARGS: --enable 153 154define <1 x i128> @test_v1i128(<1 x i128> %unused, <1 x i128> %a) #0 { 155; CHECK-LABEL: test_v1i128: 156; CHECK: // %bb.0: 157; CHECK-NEXT: mov x1, x3 158; CHECK-NEXT: mov x0, x2 159; CHECK-NEXT: ret 160 ret <1 x i128> %a 161} 162 163define <2 x i128> @test_v2i128(<2 x i128> %unused, <2 x i128> %a) #0 { 164; CHECK-LABEL: test_v2i128: 165; CHECK: // %bb.0: 166; CHECK-NEXT: mov x3, x7 167; CHECK-NEXT: mov x2, x6 168; CHECK-NEXT: mov x0, x4 169; CHECK-NEXT: mov x1, x5 170; CHECK-NEXT: ret 171 ret <2 x i128> %a 172} 173 174define <1 x i256> @test_v1i256(<1 x i256> %unused, <1 x i256> %a) #0 { 175; CHECK-LABEL: test_v1i256: 176; CHECK: // %bb.0: 177; CHECK-NEXT: mov x3, x7 178; CHECK-NEXT: mov x2, x6 179; CHECK-NEXT: mov x0, x4 180; CHECK-NEXT: mov x1, x5 181; CHECK-NEXT: ret 182 ret <1 x i256> %a 183} 184 185define <2 x i256> @test_v2i256(<2 x i256> %unused, <2 x i256> %a) #0 { 186; CHECK-LABEL: test_v2i256: 187; CHECK: // %bb.0: 188; CHECK-NEXT: ldp x0, x1, [sp] 189; CHECK-NEXT: ldp x2, x3, [sp, #16] 190; CHECK-NEXT: ldp x4, x5, [sp, #32] 191; CHECK-NEXT: ldp x6, x7, [sp, #48] 192; CHECK-NEXT: ret 193 ret <2 x i256> %a 194} 195 196define <1 x fp128> @test_v1f128(<1 x fp128> %unused, <1 x fp128> %a) #0 { 197; CHECK-LABEL: test_v1f128: 198; CHECK: // %bb.0: 199; CHECK-NEXT: mov v0.16b, v1.16b 200; CHECK-NEXT: ret 201 ret <1 x fp128> %a 202} 203 204define <2 x fp128> @test_v2f128(<2 x fp128> %unused, <2 x fp128> %a) #0 { 205; CHECK-LABEL: test_v2f128: 206; CHECK: // %bb.0: 207; CHECK-NEXT: mov v1.16b, v3.16b 208; CHECK-NEXT: mov v0.16b, v2.16b 209; CHECK-NEXT: ret 210 ret <2 x fp128> %a 211} 212 213attributes #0 = { "target-features"="+sve,+bf16" } 214