1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -debug-only=isel < %s 2>&1 | FileCheck %s 3 4; REQUIRES: asserts 5 6target triple = "aarch64-unknown-linux-gnu" 7 8; Ensure that only no offset frame indexes are folded into SVE load/stores when 9; accessing fixed width objects. 10define void @foo(ptr %a) #0 { 11; CHECK-LABEL: foo: 12; CHECK: SelectionDAG has 15 nodes: 13; CHECK-NEXT: t0: ch,glue = EntryToken 14; CHECK-NEXT: t12: nxv2i1 = PTRUE_D TargetConstant:i32<31> 15; CHECK-NEXT: t2: i64,ch = CopyFromReg t0, Register:i64 %0 16; CHECK-NEXT: t18: nxv2i64,ch = LD1D_IMM<Mem:(volatile load (s512) from %ir.a)> t12, t2, TargetConstant:i64<0>, t0 17; CHECK-NEXT: t8: i64 = ADDXri TargetFrameIndex:i64<1>, TargetConstant:i32<0>, TargetConstant:i32<0> 18; CHECK-NEXT: t6: i64 = ADDXri TargetFrameIndex:i64<0>, TargetConstant:i32<0>, TargetConstant:i32<0> 19; CHECK-NEXT: t17: ch = ST1D_IMM<Mem:(volatile store (s512) into %ir.r0)> t18, t12, t6, TargetConstant:i64<0>, t18:1 20; CHECK-NEXT: t16: ch = ST1D_IMM<Mem:(volatile store (s512) into %ir.r1)> t18, t12, t8, TargetConstant:i64<0>, t17 21; CHECK-NEXT: t10: ch = RET_ReallyLR t16 22; CHECK-EMPTY: 23entry: 24 %r0 = alloca <8 x i64> 25 %r1 = alloca <8 x i64> 26 %r = load volatile <8 x i64>, ptr %a 27 store volatile <8 x i64> %r, ptr %r0 28 store volatile <8 x i64> %r, ptr %r1 29 ret void 30} 31 32attributes #0 = { nounwind "target-features"="+sve" vscale_range(4,4) } 33