xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-fixed-length-addressing-modes.ll (revision cc82f1290a1e2157a6c0530d78d8cc84d2b8553d) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s
3; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s
4
5target triple = "aarch64-unknown-linux-gnu"
6
7define void @masked_gather_base_plus_stride_v8f32(ptr %dst, ptr %src) #0 {
8; CHECK-LABEL: masked_gather_base_plus_stride_v8f32:
9; CHECK:       // %bb.0:
10; CHECK-NEXT:    index z0.s, #0, #7
11; CHECK-NEXT:    ptrue p0.s, vl8
12; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x1, z0.s, sxtw #2]
13; CHECK-NEXT:    st1w { z0.s }, p0, [x0]
14; CHECK-NEXT:    ret
15  %ptrs = getelementptr float, ptr %src, <8 x i64> <i64 0, i64 7, i64 14, i64 21, i64 28, i64 35, i64 42, i64 49>
16  %data = tail call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x float> undef)
17  store <8 x float> %data, ptr %dst, align 4
18  ret void
19}
20
21define void @masked_gather_base_plus_stride_v4f64(ptr %dst, ptr %src) #0 {
22; CHECK-LABEL: masked_gather_base_plus_stride_v4f64:
23; CHECK:       // %bb.0:
24; CHECK-NEXT:    mov x8, #-32 // =0xffffffffffffffe0
25; CHECK-NEXT:    ptrue p0.d, vl4
26; CHECK-NEXT:    index z0.d, #-2, x8
27; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x1, z0.d, lsl #3]
28; CHECK-NEXT:    st1d { z0.d }, p0, [x0]
29; CHECK-NEXT:    ret
30  %ptrs = getelementptr double, ptr %src, <4 x i64> <i64 -2, i64 -34, i64 -66, i64 -98>
31  %data = tail call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> %ptrs, i32 8, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x double> undef)
32  store <4 x double> %data, ptr %dst, align 8
33  ret void
34}
35
36define void @masked_scatter_base_plus_stride_v8f32(ptr %dst, ptr %src) #0 {
37; CHECK-LABEL: masked_scatter_base_plus_stride_v8f32:
38; CHECK:       // %bb.0:
39; CHECK-NEXT:    ptrue p0.s, vl8
40; CHECK-NEXT:    index z0.s, #0, #-7
41; CHECK-NEXT:    ld1w { z1.s }, p0/z, [x1]
42; CHECK-NEXT:    st1w { z1.s }, p0, [x0, z0.s, sxtw #2]
43; CHECK-NEXT:    ret
44  %data = load <8 x float>, ptr %src, align 4
45  %ptrs = getelementptr float, ptr %dst, <8 x i64> <i64 0, i64 -7, i64 -14, i64 -21, i64 -28, i64 -35, i64 -42, i64 -49>
46  tail call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> %data, <8 x ptr> %ptrs, i32 4, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)
47  ret void
48}
49
50define void @masked_scatter_base_plus_stride_v4f64(ptr %dst, ptr %src) #0 {
51; CHECK-LABEL: masked_scatter_base_plus_stride_v4f64:
52; CHECK:       // %bb.0:
53; CHECK-NEXT:    ptrue p0.d, vl4
54; CHECK-NEXT:    index z0.d, #-2, #3
55; CHECK-NEXT:    ld1d { z1.d }, p0/z, [x1]
56; CHECK-NEXT:    st1d { z1.d }, p0, [x0, z0.d, lsl #3]
57; CHECK-NEXT:    ret
58  %data = load <4 x double>, ptr %src, align 8
59  %ptrs = getelementptr double, ptr %dst, <4 x i64> <i64 -2, i64 1, i64 4, i64 7>
60  tail call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> %data, <4 x ptr> %ptrs, i32 8, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)
61  ret void
62}
63
64declare <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr>, i32 immarg, <8 x i1>, <8 x float>)
65declare <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr>, i32 immarg, <4 x i1>, <4 x double>)
66
67declare void @llvm.masked.scatter.v8f32.v8p0(<8 x float>, <8 x ptr>, i32 immarg, <8 x i1>)
68declare void @llvm.masked.scatter.v4f64.v4p0(<4 x double>, <4 x ptr>, i32 immarg, <4 x i1>)
69
70attributes #0 = { "target-features"="+sve" }
71