xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-fixed-ld2-alloca.ll (revision 93b89bee471f58d798cba42d21201e154778846a)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s | FileCheck %s
3
4target triple = "aarch64-unknown-linux-gnu"
5
6declare void @def(ptr)
7
8define void @st1d_fixed(ptr %ptr) #0 {
9; CHECK-LABEL: st1d_fixed:
10; CHECK:       // %bb.0:
11; CHECK-NEXT:    sub sp, sp, #160
12; CHECK-NEXT:    stp x20, x19, [sp, #144] // 16-byte Folded Spill
13; CHECK-NEXT:    mov x19, x0
14; CHECK-NEXT:    mov x0, sp
15; CHECK-NEXT:    str x30, [sp, #128] // 8-byte Folded Spill
16; CHECK-NEXT:    mov x20, sp
17; CHECK-NEXT:    bl def
18; CHECK-NEXT:    ptrue p0.d
19; CHECK-NEXT:    ld2d { z0.d, z1.d }, p0/z, [x20]
20; CHECK-NEXT:    ldr x30, [sp, #128] // 8-byte Folded Reload
21; CHECK-NEXT:    st1d { z0.d }, p0, [x19]
22; CHECK-NEXT:    ldp x20, x19, [sp, #144] // 16-byte Folded Reload
23; CHECK-NEXT:    add sp, sp, #160
24; CHECK-NEXT:    ret
25  %alloc = alloca [16 x double]
26  call void @def(ptr %alloc)
27  %load = load <8 x double>, ptr %alloc
28  %strided.vec = shufflevector <8 x double> %load, <8 x double> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
29  store <4 x double> %strided.vec, ptr %ptr
30  ret void
31}
32
33attributes #0 = { "target-features"="+sve" vscale_range(2,2) nounwind }
34