1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -aarch64-sve-vector-bits-min=512 -o - < %s | FileCheck %s 3 4define void @vls_sve_and_64xi8(ptr %ap, ptr %out) nounwind { 5; CHECK-LABEL: vls_sve_and_64xi8: 6; CHECK: // %bb.0: 7; CHECK-NEXT: ptrue p0.b, vl64 8; CHECK-NEXT: adrp x8, .LCPI0_0 9; CHECK-NEXT: add x8, x8, :lo12:.LCPI0_0 10; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0] 11; CHECK-NEXT: ld1b { z1.b }, p0/z, [x8] 12; CHECK-NEXT: and z0.d, z0.d, z1.d 13; CHECK-NEXT: st1b { z0.b }, p0, [x1] 14; CHECK-NEXT: ret 15 %a = load <64 x i8>, ptr %ap 16 %b = and <64 x i8> %a, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, 17 i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, 18 i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, 19 i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255> 20 store <64 x i8> %b, ptr %out 21 ret void 22} 23 24define <16 x i8> @vls_sve_and_16xi8(<16 x i8> %b, ptr %out) nounwind { 25; CHECK-LABEL: vls_sve_and_16xi8: 26; CHECK: // %bb.0: 27; CHECK-NEXT: bic v0.8h, #255 28; CHECK-NEXT: ret 29 %c = and <16 x i8> %b, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255> 30 ret <16 x i8> %c 31} 32 33define <8 x i8> @vls_sve_and_8xi8(<8 x i8> %b, ptr %out) nounwind { 34; CHECK-LABEL: vls_sve_and_8xi8: 35; CHECK: // %bb.0: 36; CHECK-NEXT: bic v0.4h, #255 37; CHECK-NEXT: ret 38 %c = and <8 x i8> %b, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255> 39 ret <8 x i8> %c 40} 41 42