xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-fcvt.ll (revision cc82f1290a1e2157a6c0530d78d8cc84d2b8553d) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
3
4;
5; FP_EXTEND
6;
7
8define <vscale x 2 x float> @fcvts_nxv2f16(<vscale x 2 x half> %a) {
9; CHECK-LABEL: fcvts_nxv2f16:
10; CHECK:       // %bb.0:
11; CHECK-NEXT:    ptrue p0.d
12; CHECK-NEXT:    fcvt z0.s, p0/m, z0.h
13; CHECK-NEXT:    ret
14  %res = fpext <vscale x 2 x half> %a to <vscale x 2 x float>
15  ret <vscale x 2 x float> %res
16}
17
18define <vscale x 3 x float> @fcvts_nxv3f16(<vscale x 3 x half> %a) {
19; CHECK-LABEL: fcvts_nxv3f16:
20; CHECK:       // %bb.0:
21; CHECK-NEXT:    ptrue p0.s
22; CHECK-NEXT:    fcvt z0.s, p0/m, z0.h
23; CHECK-NEXT:    ret
24  %res = fpext <vscale x 3 x half> %a to <vscale x 3 x float>
25  ret <vscale x 3 x float> %res
26}
27
28define <vscale x 4 x float> @fcvts_nxv4f16(<vscale x 4 x half> %a) {
29; CHECK-LABEL: fcvts_nxv4f16:
30; CHECK:       // %bb.0:
31; CHECK-NEXT:    ptrue p0.s
32; CHECK-NEXT:    fcvt z0.s, p0/m, z0.h
33; CHECK-NEXT:    ret
34  %res = fpext <vscale x 4 x half> %a to <vscale x 4 x float>
35  ret <vscale x 4 x float> %res
36}
37
38define <vscale x 2 x double> @fcvtd_nxv2f16(<vscale x 2 x half> %a) {
39; CHECK-LABEL: fcvtd_nxv2f16:
40; CHECK:       // %bb.0:
41; CHECK-NEXT:    ptrue p0.d
42; CHECK-NEXT:    fcvt z0.d, p0/m, z0.h
43; CHECK-NEXT:    ret
44  %res = fpext <vscale x 2 x half> %a to <vscale x 2 x double>
45  ret <vscale x 2 x double> %res
46}
47
48define <vscale x 2 x double> @fcvtd_nxv2f32(<vscale x 2 x float> %a) {
49; CHECK-LABEL: fcvtd_nxv2f32:
50; CHECK:       // %bb.0:
51; CHECK-NEXT:    ptrue p0.d
52; CHECK-NEXT:    fcvt z0.d, p0/m, z0.s
53; CHECK-NEXT:    ret
54  %res = fpext <vscale x 2 x float> %a to <vscale x 2 x double>
55  ret <vscale x 2 x double> %res
56}
57
58;
59; FP_ROUND
60;
61
62define <vscale x 2 x half> @fcvth_nxv2f32(<vscale x 2 x float> %a) {
63; CHECK-LABEL: fcvth_nxv2f32:
64; CHECK:       // %bb.0:
65; CHECK-NEXT:    ptrue p0.d
66; CHECK-NEXT:    fcvt z0.h, p0/m, z0.s
67; CHECK-NEXT:    ret
68  %res = fptrunc <vscale x 2 x float> %a to <vscale x 2 x half>
69  ret <vscale x 2 x half> %res
70}
71
72define <vscale x 3 x half> @fcvth_nxv3f32(<vscale x 3 x float> %a) {
73; CHECK-LABEL: fcvth_nxv3f32:
74; CHECK:       // %bb.0:
75; CHECK-NEXT:    ptrue p0.s
76; CHECK-NEXT:    fcvt z0.h, p0/m, z0.s
77; CHECK-NEXT:    ret
78  %res = fptrunc <vscale x 3 x float> %a to <vscale x 3 x half>
79  ret <vscale x 3 x half> %res
80}
81
82define <vscale x 4 x half> @fcvth_nxv4f32(<vscale x 4 x float> %a) {
83; CHECK-LABEL: fcvth_nxv4f32:
84; CHECK:       // %bb.0:
85; CHECK-NEXT:    ptrue p0.s
86; CHECK-NEXT:    fcvt z0.h, p0/m, z0.s
87; CHECK-NEXT:    ret
88  %res = fptrunc <vscale x 4 x float> %a to <vscale x 4 x half>
89  ret <vscale x 4 x half> %res
90}
91
92define <vscale x 2 x half> @fcvth_nxv2f64(<vscale x 2 x double> %a) {
93; CHECK-LABEL: fcvth_nxv2f64:
94; CHECK:       // %bb.0:
95; CHECK-NEXT:    ptrue p0.d
96; CHECK-NEXT:    fcvt z0.h, p0/m, z0.d
97; CHECK-NEXT:    ret
98  %res = fptrunc <vscale x 2 x double> %a to <vscale x 2 x half>
99  ret <vscale x 2 x half> %res
100}
101
102define <vscale x 2 x float> @fcvts_nxv2f64(<vscale x 2 x double> %a) {
103; CHECK-LABEL: fcvts_nxv2f64:
104; CHECK:       // %bb.0:
105; CHECK-NEXT:    ptrue p0.d
106; CHECK-NEXT:    fcvt z0.s, p0/m, z0.d
107; CHECK-NEXT:    ret
108  %res = fptrunc <vscale x 2 x double> %a to <vscale x 2 x float>
109  ret <vscale x 2 x float> %res
110}
111
112;
113; FP_TO_SINT
114;
115
116define <vscale x 2 x i16> @fcvtzs_h_nxv2f16(<vscale x 2 x half> %a) {
117; CHECK-LABEL: fcvtzs_h_nxv2f16:
118; CHECK:       // %bb.0:
119; CHECK-NEXT:    ptrue p0.d
120; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.h
121; CHECK-NEXT:    ret
122  %res = fptosi <vscale x 2 x half> %a to <vscale x 2 x i16>
123  ret <vscale x 2 x i16> %res
124}
125
126define <vscale x 2 x i16> @fcvtzs_h_nxv2f32(<vscale x 2 x float> %a) {
127; CHECK-LABEL: fcvtzs_h_nxv2f32:
128; CHECK:       // %bb.0:
129; CHECK-NEXT:    ptrue p0.d
130; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.s
131; CHECK-NEXT:    ret
132  %res = fptosi <vscale x 2 x float> %a to <vscale x 2 x i16>
133  ret <vscale x 2 x i16> %res
134}
135
136define <vscale x 2 x i16> @fcvtzs_h_nxv2f64(<vscale x 2 x double> %a) {
137; CHECK-LABEL: fcvtzs_h_nxv2f64:
138; CHECK:       // %bb.0:
139; CHECK-NEXT:    ptrue p0.d
140; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.d
141; CHECK-NEXT:    ret
142  %res = fptosi <vscale x 2 x double> %a to <vscale x 2 x i16>
143  ret <vscale x 2 x i16> %res
144}
145
146define <vscale x 4 x i16> @fcvtzs_h_nxv4f16(<vscale x 4 x half> %a) {
147; CHECK-LABEL: fcvtzs_h_nxv4f16:
148; CHECK:       // %bb.0:
149; CHECK-NEXT:    ptrue p0.s
150; CHECK-NEXT:    fcvtzs z0.s, p0/m, z0.h
151; CHECK-NEXT:    ret
152  %res = fptosi <vscale x 4 x half> %a to <vscale x 4 x i16>
153  ret <vscale x 4 x i16> %res
154}
155
156define <vscale x 4 x i16> @fcvtzs_h_nxv4f32(<vscale x 4 x float> %a) {
157; CHECK-LABEL: fcvtzs_h_nxv4f32:
158; CHECK:       // %bb.0:
159; CHECK-NEXT:    ptrue p0.s
160; CHECK-NEXT:    fcvtzs z0.s, p0/m, z0.s
161; CHECK-NEXT:    ret
162  %res = fptosi <vscale x 4 x float> %a to <vscale x 4 x i16>
163  ret <vscale x 4 x i16> %res
164}
165
166define <vscale x 7 x i16> @fcvtzs_h_nxv7f16(<vscale x 7 x half> %a) {
167; CHECK-LABEL: fcvtzs_h_nxv7f16:
168; CHECK:       // %bb.0:
169; CHECK-NEXT:    ptrue p0.h
170; CHECK-NEXT:    fcvtzs z0.h, p0/m, z0.h
171; CHECK-NEXT:    ret
172  %res = fptosi <vscale x 7 x half> %a to <vscale x 7 x i16>
173  ret <vscale x 7 x i16> %res
174}
175
176define <vscale x 8 x i16> @fcvtzs_h_nxv8f16(<vscale x 8 x half> %a) {
177; CHECK-LABEL: fcvtzs_h_nxv8f16:
178; CHECK:       // %bb.0:
179; CHECK-NEXT:    ptrue p0.h
180; CHECK-NEXT:    fcvtzs z0.h, p0/m, z0.h
181; CHECK-NEXT:    ret
182  %res = fptosi <vscale x 8 x half> %a to <vscale x 8 x i16>
183  ret <vscale x 8 x i16> %res
184}
185
186define <vscale x 2 x i32> @fcvtzs_s_nxv2f16(<vscale x 2 x half> %a) {
187; CHECK-LABEL: fcvtzs_s_nxv2f16:
188; CHECK:       // %bb.0:
189; CHECK-NEXT:    ptrue p0.d
190; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.h
191; CHECK-NEXT:    ret
192  %res = fptosi <vscale x 2 x half> %a to <vscale x 2 x i32>
193  ret <vscale x 2 x i32> %res
194}
195
196define <vscale x 2 x i32> @fcvtzs_s_nxv2f32(<vscale x 2 x float> %a) {
197; CHECK-LABEL: fcvtzs_s_nxv2f32:
198; CHECK:       // %bb.0:
199; CHECK-NEXT:    ptrue p0.d
200; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.s
201; CHECK-NEXT:    ret
202  %res = fptosi <vscale x 2 x float> %a to <vscale x 2 x i32>
203  ret <vscale x 2 x i32> %res
204}
205
206define <vscale x 2 x i32> @fcvtzs_s_nxv2f64(<vscale x 2 x double> %a) {
207; CHECK-LABEL: fcvtzs_s_nxv2f64:
208; CHECK:       // %bb.0:
209; CHECK-NEXT:    ptrue p0.d
210; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.d
211; CHECK-NEXT:    ret
212  %res = fptosi <vscale x 2 x double> %a to <vscale x 2 x i32>
213  ret <vscale x 2 x i32> %res
214}
215
216define <vscale x 4 x i32> @fcvtzs_s_nxv4f16(<vscale x 4 x half> %a) {
217; CHECK-LABEL: fcvtzs_s_nxv4f16:
218; CHECK:       // %bb.0:
219; CHECK-NEXT:    ptrue p0.s
220; CHECK-NEXT:    fcvtzs z0.s, p0/m, z0.h
221; CHECK-NEXT:    ret
222  %res = fptosi <vscale x 4 x half> %a to <vscale x 4 x i32>
223  ret <vscale x 4 x i32> %res
224}
225
226define <vscale x 3 x i32> @fcvtzs_s_nxv3f16(<vscale x 3 x half> %a) {
227; CHECK-LABEL: fcvtzs_s_nxv3f16:
228; CHECK:       // %bb.0:
229; CHECK-NEXT:    ptrue p0.s
230; CHECK-NEXT:    fcvtzs z0.s, p0/m, z0.h
231; CHECK-NEXT:    ret
232  %res = fptosi <vscale x 3 x half> %a to <vscale x 3 x i32>
233  ret <vscale x 3 x i32> %res
234}
235
236define <vscale x 4 x i32> @fcvtzs_s_nxv4f32(<vscale x 4 x float> %a) {
237; CHECK-LABEL: fcvtzs_s_nxv4f32:
238; CHECK:       // %bb.0:
239; CHECK-NEXT:    ptrue p0.s
240; CHECK-NEXT:    fcvtzs z0.s, p0/m, z0.s
241; CHECK-NEXT:    ret
242  %res = fptosi <vscale x 4 x float> %a to <vscale x 4 x i32>
243  ret <vscale x 4 x i32> %res
244}
245
246define <vscale x 2 x i64> @fcvtzs_d_nxv2f16(<vscale x 2 x half> %a) {
247; CHECK-LABEL: fcvtzs_d_nxv2f16:
248; CHECK:       // %bb.0:
249; CHECK-NEXT:    ptrue p0.d
250; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.h
251; CHECK-NEXT:    ret
252  %res = fptosi <vscale x 2 x half> %a to <vscale x 2 x i64>
253  ret <vscale x 2 x i64> %res
254}
255
256define <vscale x 2 x i64> @fcvtzs_d_nxv2f32(<vscale x 2 x float> %a) {
257; CHECK-LABEL: fcvtzs_d_nxv2f32:
258; CHECK:       // %bb.0:
259; CHECK-NEXT:    ptrue p0.d
260; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.s
261; CHECK-NEXT:    ret
262  %res = fptosi <vscale x 2 x float> %a to <vscale x 2 x i64>
263  ret <vscale x 2 x i64> %res
264}
265
266define <vscale x 2 x i64> @fcvtzs_d_nxv2f64(<vscale x 2 x double> %a) {
267; CHECK-LABEL: fcvtzs_d_nxv2f64:
268; CHECK:       // %bb.0:
269; CHECK-NEXT:    ptrue p0.d
270; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.d
271; CHECK-NEXT:    ret
272  %res = fptosi <vscale x 2 x double> %a to <vscale x 2 x i64>
273  ret <vscale x 2 x i64> %res
274}
275
276;
277; FP_TO_UINT
278;
279
280; NOTE: Using fcvtzs is safe as fptoui overflow is considered poison and a
281; 64bit signed value encompasses the entire range of a 16bit unsigned value
282define <vscale x 2 x i16> @fcvtzu_h_nxv2f16(<vscale x 2 x half> %a) {
283; CHECK-LABEL: fcvtzu_h_nxv2f16:
284; CHECK:       // %bb.0:
285; CHECK-NEXT:    ptrue p0.d
286; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.h
287; CHECK-NEXT:    ret
288  %res = fptoui <vscale x 2 x half> %a to <vscale x 2 x i16>
289  ret <vscale x 2 x i16> %res
290}
291
292define <vscale x 2 x i16> @fcvtzu_h_nxv2f32(<vscale x 2 x float> %a) {
293; CHECK-LABEL: fcvtzu_h_nxv2f32:
294; CHECK:       // %bb.0:
295; CHECK-NEXT:    ptrue p0.d
296; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.s
297; CHECK-NEXT:    ret
298  %res = fptoui <vscale x 2 x float> %a to <vscale x 2 x i16>
299  ret <vscale x 2 x i16> %res
300}
301
302define <vscale x 2 x i16> @fcvtzu_h_nxv2f64(<vscale x 2 x double> %a) {
303; CHECK-LABEL: fcvtzu_h_nxv2f64:
304; CHECK:       // %bb.0:
305; CHECK-NEXT:    ptrue p0.d
306; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.d
307; CHECK-NEXT:    ret
308  %res = fptoui <vscale x 2 x double> %a to <vscale x 2 x i16>
309  ret <vscale x 2 x i16> %res
310}
311
312define <vscale x 4 x i16> @fcvtzu_h_nxv4f16(<vscale x 4 x half> %a) {
313; CHECK-LABEL: fcvtzu_h_nxv4f16:
314; CHECK:       // %bb.0:
315; CHECK-NEXT:    ptrue p0.s
316; CHECK-NEXT:    fcvtzs z0.s, p0/m, z0.h
317; CHECK-NEXT:    ret
318  %res = fptoui <vscale x 4 x half> %a to <vscale x 4 x i16>
319  ret <vscale x 4 x i16> %res
320}
321
322define <vscale x 4 x i16> @fcvtzu_h_nxv4f32(<vscale x 4 x float> %a) {
323; CHECK-LABEL: fcvtzu_h_nxv4f32:
324; CHECK:       // %bb.0:
325; CHECK-NEXT:    ptrue p0.s
326; CHECK-NEXT:    fcvtzs z0.s, p0/m, z0.s
327; CHECK-NEXT:    ret
328  %res = fptosi <vscale x 4 x float> %a to <vscale x 4 x i16>
329  ret <vscale x 4 x i16> %res
330}
331
332define <vscale x 7 x i16> @fcvtzu_h_nxv7f16(<vscale x 7 x half> %a) {
333; CHECK-LABEL: fcvtzu_h_nxv7f16:
334; CHECK:       // %bb.0:
335; CHECK-NEXT:    ptrue p0.h
336; CHECK-NEXT:    fcvtzu z0.h, p0/m, z0.h
337; CHECK-NEXT:    ret
338  %res = fptoui <vscale x 7 x half> %a to <vscale x 7 x i16>
339  ret <vscale x 7 x i16> %res
340}
341
342define <vscale x 8 x i16> @fcvtzu_h_nxv8f16(<vscale x 8 x half> %a) {
343; CHECK-LABEL: fcvtzu_h_nxv8f16:
344; CHECK:       // %bb.0:
345; CHECK-NEXT:    ptrue p0.h
346; CHECK-NEXT:    fcvtzu z0.h, p0/m, z0.h
347; CHECK-NEXT:    ret
348  %res = fptoui <vscale x 8 x half> %a to <vscale x 8 x i16>
349  ret <vscale x 8 x i16> %res
350}
351
352define <vscale x 2 x i32> @fcvtzu_s_nxv2f16(<vscale x 2 x half> %a) {
353; CHECK-LABEL: fcvtzu_s_nxv2f16:
354; CHECK:       // %bb.0:
355; CHECK-NEXT:    ptrue p0.d
356; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.h
357; CHECK-NEXT:    ret
358  %res = fptoui <vscale x 2 x half> %a to <vscale x 2 x i32>
359  ret <vscale x 2 x i32> %res
360}
361
362define <vscale x 2 x i32> @fcvtzu_s_nxv2f32(<vscale x 2 x float> %a) {
363; CHECK-LABEL: fcvtzu_s_nxv2f32:
364; CHECK:       // %bb.0:
365; CHECK-NEXT:    ptrue p0.d
366; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.s
367; CHECK-NEXT:    ret
368  %res = fptoui <vscale x 2 x float> %a to <vscale x 2 x i32>
369  ret <vscale x 2 x i32> %res
370}
371
372define <vscale x 2 x i32> @fcvtzu_s_nxv2f64(<vscale x 2 x double> %a) {
373; CHECK-LABEL: fcvtzu_s_nxv2f64:
374; CHECK:       // %bb.0:
375; CHECK-NEXT:    ptrue p0.d
376; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.d
377; CHECK-NEXT:    ret
378  %res = fptoui <vscale x 2 x double> %a to <vscale x 2 x i32>
379  ret <vscale x 2 x i32> %res
380}
381
382define <vscale x 3 x i32> @fcvtzu_s_nxv3f16(<vscale x 3 x half> %a) {
383; CHECK-LABEL: fcvtzu_s_nxv3f16:
384; CHECK:       // %bb.0:
385; CHECK-NEXT:    ptrue p0.s
386; CHECK-NEXT:    fcvtzu z0.s, p0/m, z0.h
387; CHECK-NEXT:    ret
388  %res = fptoui <vscale x 3 x half> %a to <vscale x 3 x i32>
389  ret <vscale x 3 x i32> %res
390}
391
392define <vscale x 3 x i32> @fcvtzu_s_nxv3f32(<vscale x 3 x float> %a) {
393; CHECK-LABEL: fcvtzu_s_nxv3f32:
394; CHECK:       // %bb.0:
395; CHECK-NEXT:    ptrue p0.s
396; CHECK-NEXT:    fcvtzu z0.s, p0/m, z0.s
397; CHECK-NEXT:    ret
398  %res = fptoui <vscale x 3 x float> %a to <vscale x 3 x i32>
399  ret <vscale x 3 x i32> %res
400}
401
402define <vscale x 4 x i32> @fcvtzu_s_nxv4f16(<vscale x 4 x half> %a) {
403; CHECK-LABEL: fcvtzu_s_nxv4f16:
404; CHECK:       // %bb.0:
405; CHECK-NEXT:    ptrue p0.s
406; CHECK-NEXT:    fcvtzu z0.s, p0/m, z0.h
407; CHECK-NEXT:    ret
408  %res = fptoui <vscale x 4 x half> %a to <vscale x 4 x i32>
409  ret <vscale x 4 x i32> %res
410}
411
412define <vscale x 4 x i32> @fcvtzu_s_nxv4f32(<vscale x 4 x float> %a) {
413; CHECK-LABEL: fcvtzu_s_nxv4f32:
414; CHECK:       // %bb.0:
415; CHECK-NEXT:    ptrue p0.s
416; CHECK-NEXT:    fcvtzu z0.s, p0/m, z0.s
417; CHECK-NEXT:    ret
418  %res = fptoui <vscale x 4 x float> %a to <vscale x 4 x i32>
419  ret <vscale x 4 x i32> %res
420}
421
422define <vscale x 2 x i64> @fcvtzu_d_nxv2f16(<vscale x 2 x half> %a) {
423; CHECK-LABEL: fcvtzu_d_nxv2f16:
424; CHECK:       // %bb.0:
425; CHECK-NEXT:    ptrue p0.d
426; CHECK-NEXT:    fcvtzu z0.d, p0/m, z0.h
427; CHECK-NEXT:    ret
428  %res = fptoui <vscale x 2 x half> %a to <vscale x 2 x i64>
429  ret <vscale x 2 x i64> %res
430}
431
432define <vscale x 2 x i64> @fcvtzu_d_nxv2f32(<vscale x 2 x float> %a) {
433; CHECK-LABEL: fcvtzu_d_nxv2f32:
434; CHECK:       // %bb.0:
435; CHECK-NEXT:    ptrue p0.d
436; CHECK-NEXT:    fcvtzu z0.d, p0/m, z0.s
437; CHECK-NEXT:    ret
438  %res = fptoui <vscale x 2 x float> %a to <vscale x 2 x i64>
439  ret <vscale x 2 x i64> %res
440}
441
442define <vscale x 2 x i64> @fcvtzu_d_nxv2f64(<vscale x 2 x double> %a) {
443; CHECK-LABEL: fcvtzu_d_nxv2f64:
444; CHECK:       // %bb.0:
445; CHECK-NEXT:    ptrue p0.d
446; CHECK-NEXT:    fcvtzu z0.d, p0/m, z0.d
447; CHECK-NEXT:    ret
448  %res = fptoui <vscale x 2 x double> %a to <vscale x 2 x i64>
449  ret <vscale x 2 x i64> %res
450}
451
452; SINT_TO_FP
453
454define <vscale x 2 x half> @scvtf_h_nxv2i1(<vscale x 2 x i1> %a) {
455; CHECK-LABEL: scvtf_h_nxv2i1:
456; CHECK:       // %bb.0:
457; CHECK-NEXT:    mov z0.d, p0/z, #-1 // =0xffffffffffffffff
458; CHECK-NEXT:    ptrue p0.d
459; CHECK-NEXT:    scvtf z0.h, p0/m, z0.d
460; CHECK-NEXT:    ret
461  %res = sitofp <vscale x 2 x i1> %a to <vscale x 2 x half>
462  ret <vscale x 2 x half> %res
463}
464
465define <vscale x 2 x half> @scvtf_h_nxv2i16(<vscale x 2 x i16> %a) {
466; CHECK-LABEL: scvtf_h_nxv2i16:
467; CHECK:       // %bb.0:
468; CHECK-NEXT:    ptrue p0.d
469; CHECK-NEXT:    scvtf z0.h, p0/m, z0.h
470; CHECK-NEXT:    ret
471  %res = sitofp <vscale x 2 x i16> %a to <vscale x 2 x half>
472  ret <vscale x 2 x half> %res
473}
474
475define <vscale x 2 x half> @scvtf_h_nxv2i32(<vscale x 2 x i32> %a) {
476; CHECK-LABEL: scvtf_h_nxv2i32:
477; CHECK:       // %bb.0:
478; CHECK-NEXT:    ptrue p0.d
479; CHECK-NEXT:    scvtf z0.h, p0/m, z0.s
480; CHECK-NEXT:    ret
481  %res = sitofp <vscale x 2 x i32> %a to <vscale x 2 x half>
482  ret <vscale x 2 x half> %res
483}
484
485define <vscale x 2 x half> @scvtf_h_nxv2i64(<vscale x 2 x i64> %a) {
486; CHECK-LABEL: scvtf_h_nxv2i64:
487; CHECK:       // %bb.0:
488; CHECK-NEXT:    ptrue p0.d
489; CHECK-NEXT:    scvtf z0.h, p0/m, z0.d
490; CHECK-NEXT:    ret
491  %res = sitofp <vscale x 2 x i64> %a to <vscale x 2 x half>
492  ret <vscale x 2 x half> %res
493}
494
495define <vscale x 3 x half> @scvtf_h_nxv3i1(<vscale x 3 x i1> %a) {
496; CHECK-LABEL: scvtf_h_nxv3i1:
497; CHECK:       // %bb.0:
498; CHECK-NEXT:    mov z0.s, p0/z, #-1 // =0xffffffffffffffff
499; CHECK-NEXT:    ptrue p0.s
500; CHECK-NEXT:    scvtf z0.h, p0/m, z0.s
501; CHECK-NEXT:    ret
502  %res = sitofp <vscale x 3 x i1> %a to <vscale x 3 x half>
503  ret <vscale x 3 x half> %res
504}
505
506define <vscale x 3 x half> @scvtf_h_nxv3i16(<vscale x 3 x i16> %a) {
507; CHECK-LABEL: scvtf_h_nxv3i16:
508; CHECK:       // %bb.0:
509; CHECK-NEXT:    ptrue p0.s
510; CHECK-NEXT:    scvtf z0.h, p0/m, z0.h
511; CHECK-NEXT:    ret
512  %res = sitofp <vscale x 3 x i16> %a to <vscale x 3 x half>
513  ret <vscale x 3 x half> %res
514}
515
516define <vscale x 4 x half> @scvtf_h_nxv4i1(<vscale x 4 x i1> %a) {
517; CHECK-LABEL: scvtf_h_nxv4i1:
518; CHECK:       // %bb.0:
519; CHECK-NEXT:    mov z0.s, p0/z, #-1 // =0xffffffffffffffff
520; CHECK-NEXT:    ptrue p0.s
521; CHECK-NEXT:    scvtf z0.h, p0/m, z0.s
522; CHECK-NEXT:    ret
523  %res = sitofp <vscale x 4 x i1> %a to <vscale x 4 x half>
524  ret <vscale x 4 x half> %res
525}
526
527define <vscale x 4 x half> @scvtf_h_nxv4i16(<vscale x 4 x i16> %a) {
528; CHECK-LABEL: scvtf_h_nxv4i16:
529; CHECK:       // %bb.0:
530; CHECK-NEXT:    ptrue p0.s
531; CHECK-NEXT:    scvtf z0.h, p0/m, z0.h
532; CHECK-NEXT:    ret
533  %res = sitofp <vscale x 4 x i16> %a to <vscale x 4 x half>
534  ret <vscale x 4 x half> %res
535}
536
537define <vscale x 4 x half> @scvtf_h_nxv4i32(<vscale x 4 x i32> %a) {
538; CHECK-LABEL: scvtf_h_nxv4i32:
539; CHECK:       // %bb.0:
540; CHECK-NEXT:    ptrue p0.s
541; CHECK-NEXT:    scvtf z0.h, p0/m, z0.s
542; CHECK-NEXT:    ret
543  %res = sitofp <vscale x 4 x i32> %a to <vscale x 4 x half>
544  ret <vscale x 4 x half> %res
545}
546
547define <vscale x 7 x half> @scvtf_h_nxv7i1(<vscale x 7 x i1> %a) {
548; CHECK-LABEL: scvtf_h_nxv7i1:
549; CHECK:       // %bb.0:
550; CHECK-NEXT:    mov z0.h, p0/z, #-1 // =0xffffffffffffffff
551; CHECK-NEXT:    ptrue p0.h
552; CHECK-NEXT:    scvtf z0.h, p0/m, z0.h
553; CHECK-NEXT:    ret
554  %res = sitofp <vscale x 7 x i1> %a to <vscale x 7 x half>
555  ret <vscale x 7 x half> %res
556}
557
558define <vscale x 7 x half> @scvtf_h_nxv7i16(<vscale x 7 x i16> %a) {
559; CHECK-LABEL: scvtf_h_nxv7i16:
560; CHECK:       // %bb.0:
561; CHECK-NEXT:    ptrue p0.h
562; CHECK-NEXT:    scvtf z0.h, p0/m, z0.h
563; CHECK-NEXT:    ret
564  %res = sitofp <vscale x 7 x i16> %a to <vscale x 7 x half>
565  ret <vscale x 7 x half> %res
566}
567
568define <vscale x 8 x half> @scvtf_h_nxv8i1(<vscale x 8 x i1> %a) {
569; CHECK-LABEL: scvtf_h_nxv8i1:
570; CHECK:       // %bb.0:
571; CHECK-NEXT:    mov z0.h, p0/z, #-1 // =0xffffffffffffffff
572; CHECK-NEXT:    ptrue p0.h
573; CHECK-NEXT:    scvtf z0.h, p0/m, z0.h
574; CHECK-NEXT:    ret
575  %res = sitofp <vscale x 8 x i1> %a to <vscale x 8 x half>
576  ret <vscale x 8 x half> %res
577}
578
579define <vscale x 8 x half> @scvtf_h_nxv8i16(<vscale x 8 x i16> %a) {
580; CHECK-LABEL: scvtf_h_nxv8i16:
581; CHECK:       // %bb.0:
582; CHECK-NEXT:    ptrue p0.h
583; CHECK-NEXT:    scvtf z0.h, p0/m, z0.h
584; CHECK-NEXT:    ret
585  %res = sitofp <vscale x 8 x i16> %a to <vscale x 8 x half>
586  ret <vscale x 8 x half> %res
587}
588
589define <vscale x 2 x float> @scvtf_s_nxv2i1(<vscale x 2 x i1> %a) {
590; CHECK-LABEL: scvtf_s_nxv2i1:
591; CHECK:       // %bb.0:
592; CHECK-NEXT:    mov z0.d, p0/z, #-1 // =0xffffffffffffffff
593; CHECK-NEXT:    ptrue p0.d
594; CHECK-NEXT:    scvtf z0.s, p0/m, z0.d
595; CHECK-NEXT:    ret
596  %res = sitofp <vscale x 2 x i1> %a to <vscale x 2 x float>
597  ret <vscale x 2 x float> %res
598}
599
600define <vscale x 2 x float> @scvtf_s_nxv2i32(<vscale x 2 x i32> %a) {
601; CHECK-LABEL: scvtf_s_nxv2i32:
602; CHECK:       // %bb.0:
603; CHECK-NEXT:    ptrue p0.d
604; CHECK-NEXT:    scvtf z0.s, p0/m, z0.s
605; CHECK-NEXT:    ret
606  %res = sitofp <vscale x 2 x i32> %a to <vscale x 2 x float>
607  ret <vscale x 2 x float> %res
608}
609
610define <vscale x 2 x float> @scvtf_s_nxv2i64(<vscale x 2 x i64> %a) {
611; CHECK-LABEL: scvtf_s_nxv2i64:
612; CHECK:       // %bb.0:
613; CHECK-NEXT:    ptrue p0.d
614; CHECK-NEXT:    scvtf z0.s, p0/m, z0.d
615; CHECK-NEXT:    ret
616  %res = sitofp <vscale x 2 x i64> %a to <vscale x 2 x float>
617  ret <vscale x 2 x float> %res
618}
619
620define <vscale x 3 x float> @scvtf_s_nxv3i1(<vscale x 3 x i1> %a) {
621; CHECK-LABEL: scvtf_s_nxv3i1:
622; CHECK:       // %bb.0:
623; CHECK-NEXT:    mov z0.s, p0/z, #-1 // =0xffffffffffffffff
624; CHECK-NEXT:    ptrue p0.s
625; CHECK-NEXT:    scvtf z0.s, p0/m, z0.s
626; CHECK-NEXT:    ret
627  %res = sitofp <vscale x 3 x i1> %a to <vscale x 3 x float>
628  ret <vscale x 3 x float> %res
629}
630
631define <vscale x 3 x float> @scvtf_s_nxv3i32(<vscale x 3 x i32> %a) {
632; CHECK-LABEL: scvtf_s_nxv3i32:
633; CHECK:       // %bb.0:
634; CHECK-NEXT:    ptrue p0.s
635; CHECK-NEXT:    scvtf z0.s, p0/m, z0.s
636; CHECK-NEXT:    ret
637  %res = sitofp <vscale x 3 x i32> %a to <vscale x 3 x float>
638  ret <vscale x 3 x float> %res
639}
640
641define <vscale x 4 x float> @scvtf_s_nxv4i1(<vscale x 4 x i1> %a) {
642; CHECK-LABEL: scvtf_s_nxv4i1:
643; CHECK:       // %bb.0:
644; CHECK-NEXT:    mov z0.s, p0/z, #-1 // =0xffffffffffffffff
645; CHECK-NEXT:    ptrue p0.s
646; CHECK-NEXT:    scvtf z0.s, p0/m, z0.s
647; CHECK-NEXT:    ret
648  %res = sitofp <vscale x 4 x i1> %a to <vscale x 4 x float>
649  ret <vscale x 4 x float> %res
650}
651
652define <vscale x 4 x float> @scvtf_s_nxv4i32(<vscale x 4 x i32> %a) {
653; CHECK-LABEL: scvtf_s_nxv4i32:
654; CHECK:       // %bb.0:
655; CHECK-NEXT:    ptrue p0.s
656; CHECK-NEXT:    scvtf z0.s, p0/m, z0.s
657; CHECK-NEXT:    ret
658  %res = sitofp <vscale x 4 x i32> %a to <vscale x 4 x float>
659  ret <vscale x 4 x float> %res
660}
661
662define <vscale x 2 x double> @scvtf_d_nxv2i1(<vscale x 2 x i1> %a) {
663; CHECK-LABEL: scvtf_d_nxv2i1:
664; CHECK:       // %bb.0:
665; CHECK-NEXT:    mov z0.d, p0/z, #-1 // =0xffffffffffffffff
666; CHECK-NEXT:    ptrue p0.d
667; CHECK-NEXT:    scvtf z0.d, p0/m, z0.d
668; CHECK-NEXT:    ret
669  %res = sitofp <vscale x 2 x i1> %a to <vscale x 2 x double>
670  ret <vscale x 2 x double> %res
671}
672
673define <vscale x 2 x double> @scvtf_d_nxv2i32(<vscale x 2 x i32> %a) {
674; CHECK-LABEL: scvtf_d_nxv2i32:
675; CHECK:       // %bb.0:
676; CHECK-NEXT:    ptrue p0.d
677; CHECK-NEXT:    scvtf z0.d, p0/m, z0.s
678; CHECK-NEXT:    ret
679  %res = sitofp <vscale x 2 x i32> %a to <vscale x 2 x double>
680  ret <vscale x 2 x double> %res
681}
682
683define <vscale x 2 x double> @scvtf_d_nxv2i64(<vscale x 2 x i64> %a) {
684; CHECK-LABEL: scvtf_d_nxv2i64:
685; CHECK:       // %bb.0:
686; CHECK-NEXT:    ptrue p0.d
687; CHECK-NEXT:    scvtf z0.d, p0/m, z0.d
688; CHECK-NEXT:    ret
689  %res = sitofp <vscale x 2 x i64> %a to <vscale x 2 x double>
690  ret <vscale x 2 x double> %res
691}
692
693; UINT_TO_FP
694
695define <vscale x 2 x half> @ucvtf_h_nxv2i1(<vscale x 2 x i1> %a) {
696; CHECK-LABEL: ucvtf_h_nxv2i1:
697; CHECK:       // %bb.0:
698; CHECK-NEXT:    mov z0.d, p0/z, #1 // =0x1
699; CHECK-NEXT:    ptrue p0.d
700; CHECK-NEXT:    ucvtf z0.h, p0/m, z0.d
701; CHECK-NEXT:    ret
702  %res = uitofp <vscale x 2 x i1> %a to <vscale x 2 x half>
703  ret <vscale x 2 x half> %res
704}
705
706define <vscale x 2 x half> @ucvtf_h_nxv2i16(<vscale x 2 x i16> %a) {
707; CHECK-LABEL: ucvtf_h_nxv2i16:
708; CHECK:       // %bb.0:
709; CHECK-NEXT:    ptrue p0.d
710; CHECK-NEXT:    ucvtf z0.h, p0/m, z0.h
711; CHECK-NEXT:    ret
712  %res = uitofp <vscale x 2 x i16> %a to <vscale x 2 x half>
713  ret <vscale x 2 x half> %res
714}
715
716define <vscale x 2 x half> @ucvtf_h_nxv2i32(<vscale x 2 x i32> %a) {
717; CHECK-LABEL: ucvtf_h_nxv2i32:
718; CHECK:       // %bb.0:
719; CHECK-NEXT:    ptrue p0.d
720; CHECK-NEXT:    ucvtf z0.h, p0/m, z0.s
721; CHECK-NEXT:    ret
722  %res = uitofp <vscale x 2 x i32> %a to <vscale x 2 x half>
723  ret <vscale x 2 x half> %res
724}
725
726define <vscale x 2 x half> @ucvtf_h_nxv2i64(<vscale x 2 x i64> %a) {
727; CHECK-LABEL: ucvtf_h_nxv2i64:
728; CHECK:       // %bb.0:
729; CHECK-NEXT:    ptrue p0.d
730; CHECK-NEXT:    ucvtf z0.h, p0/m, z0.d
731; CHECK-NEXT:    ret
732  %res = uitofp <vscale x 2 x i64> %a to <vscale x 2 x half>
733  ret <vscale x 2 x half> %res
734}
735
736define <vscale x 3 x half> @ucvtf_h_nxv3i1(<vscale x 3 x i1> %a) {
737; CHECK-LABEL: ucvtf_h_nxv3i1:
738; CHECK:       // %bb.0:
739; CHECK-NEXT:    mov z0.s, p0/z, #1 // =0x1
740; CHECK-NEXT:    ptrue p0.s
741; CHECK-NEXT:    ucvtf z0.h, p0/m, z0.s
742; CHECK-NEXT:    ret
743  %res = uitofp <vscale x 3 x i1> %a to <vscale x 3 x half>
744  ret <vscale x 3 x half> %res
745}
746
747define <vscale x 3 x half> @ucvtf_h_nxv3i16(<vscale x 3 x i16> %a) {
748; CHECK-LABEL: ucvtf_h_nxv3i16:
749; CHECK:       // %bb.0:
750; CHECK-NEXT:    ptrue p0.s
751; CHECK-NEXT:    ucvtf z0.h, p0/m, z0.h
752; CHECK-NEXT:    ret
753  %res = uitofp <vscale x 3 x i16> %a to <vscale x 3 x half>
754  ret <vscale x 3 x half> %res
755}
756
757define <vscale x 3 x half> @ucvtf_h_nxv3i32(<vscale x 3 x i32> %a) {
758; CHECK-LABEL: ucvtf_h_nxv3i32:
759; CHECK:       // %bb.0:
760; CHECK-NEXT:    ptrue p0.s
761; CHECK-NEXT:    ucvtf z0.h, p0/m, z0.s
762; CHECK-NEXT:    ret
763  %res = uitofp <vscale x 3 x i32> %a to <vscale x 3 x half>
764  ret <vscale x 3 x half> %res
765}
766
767define <vscale x 4 x half> @ucvtf_h_nxv4i1(<vscale x 4 x i1> %a) {
768; CHECK-LABEL: ucvtf_h_nxv4i1:
769; CHECK:       // %bb.0:
770; CHECK-NEXT:    mov z0.s, p0/z, #1 // =0x1
771; CHECK-NEXT:    ptrue p0.s
772; CHECK-NEXT:    ucvtf z0.h, p0/m, z0.s
773; CHECK-NEXT:    ret
774  %res = uitofp <vscale x 4 x i1> %a to <vscale x 4 x half>
775  ret <vscale x 4 x half> %res
776}
777
778define <vscale x 4 x half> @ucvtf_h_nxv4i16(<vscale x 4 x i16> %a) {
779; CHECK-LABEL: ucvtf_h_nxv4i16:
780; CHECK:       // %bb.0:
781; CHECK-NEXT:    ptrue p0.s
782; CHECK-NEXT:    ucvtf z0.h, p0/m, z0.h
783; CHECK-NEXT:    ret
784  %res = uitofp <vscale x 4 x i16> %a to <vscale x 4 x half>
785  ret <vscale x 4 x half> %res
786}
787
788define <vscale x 4 x half> @ucvtf_h_nxv4i32(<vscale x 4 x i32> %a) {
789; CHECK-LABEL: ucvtf_h_nxv4i32:
790; CHECK:       // %bb.0:
791; CHECK-NEXT:    ptrue p0.s
792; CHECK-NEXT:    ucvtf z0.h, p0/m, z0.s
793; CHECK-NEXT:    ret
794  %res = uitofp <vscale x 4 x i32> %a to <vscale x 4 x half>
795  ret <vscale x 4 x half> %res
796}
797
798define <vscale x 8 x half> @ucvtf_h_nxv8i1(<vscale x 8 x i1> %a) {
799; CHECK-LABEL: ucvtf_h_nxv8i1:
800; CHECK:       // %bb.0:
801; CHECK-NEXT:    mov z0.h, p0/z, #1 // =0x1
802; CHECK-NEXT:    ptrue p0.h
803; CHECK-NEXT:    ucvtf z0.h, p0/m, z0.h
804; CHECK-NEXT:    ret
805  %res = uitofp <vscale x 8 x i1> %a to <vscale x 8 x half>
806  ret <vscale x 8 x half> %res
807}
808
809define <vscale x 8 x half> @ucvtf_h_nxv8i16(<vscale x 8 x i16> %a) {
810; CHECK-LABEL: ucvtf_h_nxv8i16:
811; CHECK:       // %bb.0:
812; CHECK-NEXT:    ptrue p0.h
813; CHECK-NEXT:    ucvtf z0.h, p0/m, z0.h
814; CHECK-NEXT:    ret
815  %res = uitofp <vscale x 8 x i16> %a to <vscale x 8 x half>
816  ret <vscale x 8 x half> %res
817}
818
819define <vscale x 2 x float> @ucvtf_s_nxv2i1(<vscale x 2 x i1> %a) {
820; CHECK-LABEL: ucvtf_s_nxv2i1:
821; CHECK:       // %bb.0:
822; CHECK-NEXT:    mov z0.d, p0/z, #1 // =0x1
823; CHECK-NEXT:    ptrue p0.d
824; CHECK-NEXT:    ucvtf z0.s, p0/m, z0.d
825; CHECK-NEXT:    ret
826  %res = uitofp <vscale x 2 x i1> %a to <vscale x 2 x float>
827  ret <vscale x 2 x float> %res
828}
829
830define <vscale x 2 x float> @ucvtf_s_nxv2i32(<vscale x 2 x i32> %a) {
831; CHECK-LABEL: ucvtf_s_nxv2i32:
832; CHECK:       // %bb.0:
833; CHECK-NEXT:    ptrue p0.d
834; CHECK-NEXT:    ucvtf z0.s, p0/m, z0.s
835; CHECK-NEXT:    ret
836  %res = uitofp <vscale x 2 x i32> %a to <vscale x 2 x float>
837  ret <vscale x 2 x float> %res
838}
839
840define <vscale x 2 x float> @ucvtf_s_nxv2i64(<vscale x 2 x i64> %a) {
841; CHECK-LABEL: ucvtf_s_nxv2i64:
842; CHECK:       // %bb.0:
843; CHECK-NEXT:    ptrue p0.d
844; CHECK-NEXT:    ucvtf z0.s, p0/m, z0.d
845; CHECK-NEXT:    ret
846  %res = uitofp <vscale x 2 x i64> %a to <vscale x 2 x float>
847  ret <vscale x 2 x float> %res
848}
849
850define <vscale x 4 x float> @ucvtf_s_nxv4i1(<vscale x 4 x i1> %a) {
851; CHECK-LABEL: ucvtf_s_nxv4i1:
852; CHECK:       // %bb.0:
853; CHECK-NEXT:    mov z0.s, p0/z, #1 // =0x1
854; CHECK-NEXT:    ptrue p0.s
855; CHECK-NEXT:    ucvtf z0.s, p0/m, z0.s
856; CHECK-NEXT:    ret
857  %res = uitofp <vscale x 4 x i1> %a to <vscale x 4 x float>
858  ret <vscale x 4 x float> %res
859}
860
861define <vscale x 4 x float> @ucvtf_s_nxv4i32(<vscale x 4 x i32> %a) {
862; CHECK-LABEL: ucvtf_s_nxv4i32:
863; CHECK:       // %bb.0:
864; CHECK-NEXT:    ptrue p0.s
865; CHECK-NEXT:    ucvtf z0.s, p0/m, z0.s
866; CHECK-NEXT:    ret
867  %res = uitofp <vscale x 4 x i32> %a to <vscale x 4 x float>
868  ret <vscale x 4 x float> %res
869}
870
871define <vscale x 2 x double> @ucvtf_d_nxv2i1(<vscale x 2 x i1> %a) {
872; CHECK-LABEL: ucvtf_d_nxv2i1:
873; CHECK:       // %bb.0:
874; CHECK-NEXT:    mov z0.d, p0/z, #1 // =0x1
875; CHECK-NEXT:    ptrue p0.d
876; CHECK-NEXT:    ucvtf z0.d, p0/m, z0.d
877; CHECK-NEXT:    ret
878  %res = uitofp <vscale x 2 x i1> %a to <vscale x 2 x double>
879  ret <vscale x 2 x double> %res
880}
881
882define <vscale x 2 x double> @ucvtf_d_nxv2i32(<vscale x 2 x i32> %a) {
883; CHECK-LABEL: ucvtf_d_nxv2i32:
884; CHECK:       // %bb.0:
885; CHECK-NEXT:    ptrue p0.d
886; CHECK-NEXT:    ucvtf z0.d, p0/m, z0.s
887; CHECK-NEXT:    ret
888  %res = uitofp <vscale x 2 x i32> %a to <vscale x 2 x double>
889  ret <vscale x 2 x double> %res
890}
891
892define <vscale x 2 x double> @ucvtf_d_nxv2i64(<vscale x 2 x i64> %a) {
893; CHECK-LABEL: ucvtf_d_nxv2i64:
894; CHECK:       // %bb.0:
895; CHECK-NEXT:    ptrue p0.d
896; CHECK-NEXT:    ucvtf z0.d, p0/m, z0.d
897; CHECK-NEXT:    ret
898  %res = uitofp <vscale x 2 x i64> %a to <vscale x 2 x double>
899  ret <vscale x 2 x double> %res
900}
901
902define <vscale x 4 x float> @fcvt_htos_movprfx(<vscale x 4 x half> %a, <vscale x 4 x half> %b) {
903; CHECK-LABEL: fcvt_htos_movprfx:
904; CHECK:       // %bb.0:
905; CHECK-NEXT:    ptrue p0.s
906; CHECK-NEXT:    movprfx z0, z1
907; CHECK-NEXT:    fcvt z0.s, p0/m, z1.h
908; CHECK-NEXT:    ret
909  %res = fpext <vscale x 4 x half> %b to <vscale x 4 x float>
910  ret <vscale x 4 x float> %res
911}
912
913define <vscale x 2 x double> @fcvt_htod_movprfx(<vscale x 2 x half> %a, <vscale x 2 x half> %b) {
914; CHECK-LABEL: fcvt_htod_movprfx:
915; CHECK:       // %bb.0:
916; CHECK-NEXT:    ptrue p0.d
917; CHECK-NEXT:    movprfx z0, z1
918; CHECK-NEXT:    fcvt z0.d, p0/m, z1.h
919; CHECK-NEXT:    ret
920  %res = fpext <vscale x 2 x half> %b to <vscale x 2 x double>
921  ret <vscale x 2 x double> %res
922}
923
924define <vscale x 2 x double> @fcvt_stod_movprfx(<vscale x 2 x float> %a, <vscale x 2 x float> %b) {
925; CHECK-LABEL: fcvt_stod_movprfx:
926; CHECK:       // %bb.0:
927; CHECK-NEXT:    ptrue p0.d
928; CHECK-NEXT:    movprfx z0, z1
929; CHECK-NEXT:    fcvt z0.d, p0/m, z1.s
930; CHECK-NEXT:    ret
931  %res = fpext <vscale x 2 x float> %b to <vscale x 2 x double>
932  ret <vscale x 2 x double> %res
933}
934
935define <vscale x 4 x half> @fcvt_stoh_movprfx(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {
936; CHECK-LABEL: fcvt_stoh_movprfx:
937; CHECK:       // %bb.0:
938; CHECK-NEXT:    ptrue p0.s
939; CHECK-NEXT:    movprfx z0, z1
940; CHECK-NEXT:    fcvt z0.h, p0/m, z1.s
941; CHECK-NEXT:    ret
942  %res = fptrunc <vscale x 4 x float> %b to <vscale x 4 x half>
943  ret <vscale x 4 x half> %res
944}
945
946define <vscale x 2 x half> @fcvt_dtoh_movprfx(<vscale x 2 x double> %a, <vscale x 2 x double> %b) {
947; CHECK-LABEL: fcvt_dtoh_movprfx:
948; CHECK:       // %bb.0:
949; CHECK-NEXT:    ptrue p0.d
950; CHECK-NEXT:    movprfx z0, z1
951; CHECK-NEXT:    fcvt z0.h, p0/m, z1.d
952; CHECK-NEXT:    ret
953  %res = fptrunc <vscale x 2 x double> %b to <vscale x 2 x half>
954  ret <vscale x 2 x half> %res
955}
956
957define <vscale x 2 x float> @fcvt_dtos_movprfx(<vscale x 2 x double> %a, <vscale x 2 x double> %b) {
958; CHECK-LABEL: fcvt_dtos_movprfx:
959; CHECK:       // %bb.0:
960; CHECK-NEXT:    ptrue p0.d
961; CHECK-NEXT:    movprfx z0, z1
962; CHECK-NEXT:    fcvt z0.s, p0/m, z1.d
963; CHECK-NEXT:    ret
964  %res = fptrunc <vscale x 2 x double> %b to <vscale x 2 x float>
965  ret <vscale x 2 x float> %res
966}
967
968define <vscale x 8 x half> @scvtf_htoh_movprfx(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
969; CHECK-LABEL: scvtf_htoh_movprfx:
970; CHECK:       // %bb.0:
971; CHECK-NEXT:    ptrue p0.h
972; CHECK-NEXT:    movprfx z0, z1
973; CHECK-NEXT:    scvtf z0.h, p0/m, z1.h
974; CHECK-NEXT:    ret
975  %res = sitofp <vscale x 8 x i16> %b to <vscale x 8 x half>
976  ret <vscale x 8 x half> %res
977}
978
979define <vscale x 4 x float> @scvtf_stos_movprfx(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
980; CHECK-LABEL: scvtf_stos_movprfx:
981; CHECK:       // %bb.0:
982; CHECK-NEXT:    ptrue p0.s
983; CHECK-NEXT:    movprfx z0, z1
984; CHECK-NEXT:    scvtf z0.s, p0/m, z1.s
985; CHECK-NEXT:    ret
986  %res = sitofp <vscale x 4 x i32> %b to <vscale x 4 x float>
987  ret <vscale x 4 x float> %res
988}
989
990define <vscale x 2 x double> @scvtf_stod_movprfx(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {
991; CHECK-LABEL: scvtf_stod_movprfx:
992; CHECK:       // %bb.0:
993; CHECK-NEXT:    ptrue p0.d
994; CHECK-NEXT:    movprfx z0, z1
995; CHECK-NEXT:    scvtf z0.d, p0/m, z1.s
996; CHECK-NEXT:    ret
997  %res = sitofp <vscale x 2 x i32> %b to <vscale x 2 x double>
998  ret <vscale x 2 x double> %res
999}
1000
1001define <vscale x 2 x float> @scvtf_dtos_movprfx(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
1002; CHECK-LABEL: scvtf_dtos_movprfx:
1003; CHECK:       // %bb.0:
1004; CHECK-NEXT:    ptrue p0.d
1005; CHECK-NEXT:    movprfx z0, z1
1006; CHECK-NEXT:    scvtf z0.s, p0/m, z1.d
1007; CHECK-NEXT:    ret
1008  %res = sitofp <vscale x 2 x i64> %b to <vscale x 2 x float>
1009  ret <vscale x 2 x float> %res
1010}
1011
1012define <vscale x 4 x half> @scvtf_stoh_movprfx(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
1013; CHECK-LABEL: scvtf_stoh_movprfx:
1014; CHECK:       // %bb.0:
1015; CHECK-NEXT:    ptrue p0.s
1016; CHECK-NEXT:    movprfx z0, z1
1017; CHECK-NEXT:    scvtf z0.h, p0/m, z1.s
1018; CHECK-NEXT:    ret
1019  %res = sitofp <vscale x 4 x i32> %b to <vscale x 4 x half>
1020  ret <vscale x 4 x half> %res
1021}
1022
1023define <vscale x 2 x half> @scvtf_dtoh_movprfx(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
1024; CHECK-LABEL: scvtf_dtoh_movprfx:
1025; CHECK:       // %bb.0:
1026; CHECK-NEXT:    ptrue p0.d
1027; CHECK-NEXT:    movprfx z0, z1
1028; CHECK-NEXT:    scvtf z0.h, p0/m, z1.d
1029; CHECK-NEXT:    ret
1030  %res = sitofp <vscale x 2 x i64> %b to <vscale x 2 x half>
1031  ret <vscale x 2 x half> %res
1032}
1033
1034define <vscale x 2 x double> @scvtf_dtod_movprfx(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
1035; CHECK-LABEL: scvtf_dtod_movprfx:
1036; CHECK:       // %bb.0:
1037; CHECK-NEXT:    ptrue p0.d
1038; CHECK-NEXT:    movprfx z0, z1
1039; CHECK-NEXT:    scvtf z0.d, p0/m, z1.d
1040; CHECK-NEXT:    ret
1041  %res = sitofp <vscale x 2 x i64> %b to <vscale x 2 x double>
1042  ret <vscale x 2 x double> %res
1043}
1044
1045define <vscale x 4 x float> @ucvtf_stos_movprfx(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
1046; CHECK-LABEL: ucvtf_stos_movprfx:
1047; CHECK:       // %bb.0:
1048; CHECK-NEXT:    ptrue p0.s
1049; CHECK-NEXT:    movprfx z0, z1
1050; CHECK-NEXT:    ucvtf z0.s, p0/m, z1.s
1051; CHECK-NEXT:    ret
1052  %res = uitofp <vscale x 4 x i32> %b to <vscale x 4 x float>
1053  ret <vscale x 4 x float> %res
1054}
1055
1056define <vscale x 8 x half> @ucvtf_htoh_movprfx(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
1057; CHECK-LABEL: ucvtf_htoh_movprfx:
1058; CHECK:       // %bb.0:
1059; CHECK-NEXT:    ptrue p0.h
1060; CHECK-NEXT:    movprfx z0, z1
1061; CHECK-NEXT:    ucvtf z0.h, p0/m, z1.h
1062; CHECK-NEXT:    ret
1063  %res = uitofp <vscale x 8 x i16> %b to <vscale x 8 x half>
1064  ret <vscale x 8 x half> %res
1065}
1066
1067define <vscale x 2 x double> @ucvtf_stod_movprfx(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {
1068; CHECK-LABEL: ucvtf_stod_movprfx:
1069; CHECK:       // %bb.0:
1070; CHECK-NEXT:    ptrue p0.d
1071; CHECK-NEXT:    movprfx z0, z1
1072; CHECK-NEXT:    ucvtf z0.d, p0/m, z1.s
1073; CHECK-NEXT:    ret
1074  %res = uitofp <vscale x 2 x i32> %b to <vscale x 2 x double>
1075  ret <vscale x 2 x double> %res
1076}
1077
1078define <vscale x 4 x half> @ucvtf_stoh_movprfx(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
1079; CHECK-LABEL: ucvtf_stoh_movprfx:
1080; CHECK:       // %bb.0:
1081; CHECK-NEXT:    ptrue p0.s
1082; CHECK-NEXT:    movprfx z0, z1
1083; CHECK-NEXT:    ucvtf z0.h, p0/m, z1.s
1084; CHECK-NEXT:    ret
1085  %res = uitofp <vscale x 4 x i32> %b to <vscale x 4 x half>
1086  ret <vscale x 4 x half> %res
1087}
1088
1089define <vscale x 2 x float> @ucvtf_dtos_movprfx(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
1090; CHECK-LABEL: ucvtf_dtos_movprfx:
1091; CHECK:       // %bb.0:
1092; CHECK-NEXT:    ptrue p0.d
1093; CHECK-NEXT:    movprfx z0, z1
1094; CHECK-NEXT:    ucvtf z0.s, p0/m, z1.d
1095; CHECK-NEXT:    ret
1096  %res = uitofp <vscale x 2 x i64> %b to <vscale x 2 x float>
1097  ret <vscale x 2 x float> %res
1098}
1099
1100define <vscale x 2 x half> @ucvtf_dtoh_movprfx(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
1101; CHECK-LABEL: ucvtf_dtoh_movprfx:
1102; CHECK:       // %bb.0:
1103; CHECK-NEXT:    ptrue p0.d
1104; CHECK-NEXT:    movprfx z0, z1
1105; CHECK-NEXT:    ucvtf z0.h, p0/m, z1.d
1106; CHECK-NEXT:    ret
1107  %res = uitofp <vscale x 2 x i64> %b to <vscale x 2 x half>
1108  ret <vscale x 2 x half> %res
1109}
1110
1111define <vscale x 2 x double> @ucvtf_dtod_movprfx(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
1112; CHECK-LABEL: ucvtf_dtod_movprfx:
1113; CHECK:       // %bb.0:
1114; CHECK-NEXT:    ptrue p0.d
1115; CHECK-NEXT:    movprfx z0, z1
1116; CHECK-NEXT:    ucvtf z0.d, p0/m, z1.d
1117; CHECK-NEXT:    ret
1118  %res = uitofp <vscale x 2 x i64> %b to <vscale x 2 x double>
1119  ret <vscale x 2 x double> %res
1120}
1121
1122define <vscale x 8 x i16> @fcvtzs_htoh_movprfx(<vscale x 8 x half> %a, <vscale x 8 x half> %b) {
1123; CHECK-LABEL: fcvtzs_htoh_movprfx:
1124; CHECK:       // %bb.0:
1125; CHECK-NEXT:    ptrue p0.h
1126; CHECK-NEXT:    movprfx z0, z1
1127; CHECK-NEXT:    fcvtzs z0.h, p0/m, z1.h
1128; CHECK-NEXT:    ret
1129  %res = fptosi <vscale x 8 x half> %b to <vscale x 8 x i16>
1130  ret <vscale x 8 x i16> %res
1131}
1132
1133define <vscale x 4 x i32> @fcvtzs_stos_movprfx(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {
1134; CHECK-LABEL: fcvtzs_stos_movprfx:
1135; CHECK:       // %bb.0:
1136; CHECK-NEXT:    ptrue p0.s
1137; CHECK-NEXT:    movprfx z0, z1
1138; CHECK-NEXT:    fcvtzs z0.s, p0/m, z1.s
1139; CHECK-NEXT:    ret
1140  %res = fptosi <vscale x 4 x float> %b to <vscale x 4 x i32>
1141  ret <vscale x 4 x i32> %res
1142}
1143
1144define <vscale x 2 x i32> @fcvtzs_dtos_movprfx(<vscale x 2 x double> %a, <vscale x 2 x double> %b) {
1145; CHECK-LABEL: fcvtzs_dtos_movprfx:
1146; CHECK:       // %bb.0:
1147; CHECK-NEXT:    ptrue p0.d
1148; CHECK-NEXT:    movprfx z0, z1
1149; CHECK-NEXT:    fcvtzs z0.d, p0/m, z1.d
1150; CHECK-NEXT:    ret
1151  %res = fptosi <vscale x 2 x double> %b to <vscale x 2 x i32>
1152  ret <vscale x 2 x i32> %res
1153}
1154
1155define <vscale x 2 x i64> @fcvtzs_stod_movprfx(<vscale x 2 x float> %a, <vscale x 2 x float> %b) {
1156; CHECK-LABEL: fcvtzs_stod_movprfx:
1157; CHECK:       // %bb.0:
1158; CHECK-NEXT:    ptrue p0.d
1159; CHECK-NEXT:    movprfx z0, z1
1160; CHECK-NEXT:    fcvtzs z0.d, p0/m, z1.s
1161; CHECK-NEXT:    ret
1162  %res = fptosi <vscale x 2 x float> %b to <vscale x 2 x i64>
1163  ret <vscale x 2 x i64> %res
1164}
1165
1166define <vscale x 4 x i32> @fcvtzs_htos_movprfx(<vscale x 4 x half> %a, <vscale x 4 x half> %b) {
1167; CHECK-LABEL: fcvtzs_htos_movprfx:
1168; CHECK:       // %bb.0:
1169; CHECK-NEXT:    ptrue p0.s
1170; CHECK-NEXT:    movprfx z0, z1
1171; CHECK-NEXT:    fcvtzs z0.s, p0/m, z1.h
1172; CHECK-NEXT:    ret
1173  %res = fptosi <vscale x 4 x half> %b to <vscale x 4 x i32>
1174  ret <vscale x 4 x i32> %res
1175}
1176
1177define <vscale x 2 x i64> @fcvtzs_htod_movprfx(<vscale x 2 x half> %a, <vscale x 2 x half> %b) {
1178; CHECK-LABEL: fcvtzs_htod_movprfx:
1179; CHECK:       // %bb.0:
1180; CHECK-NEXT:    ptrue p0.d
1181; CHECK-NEXT:    movprfx z0, z1
1182; CHECK-NEXT:    fcvtzs z0.d, p0/m, z1.h
1183; CHECK-NEXT:    ret
1184  %res = fptosi <vscale x 2 x half> %b to <vscale x 2 x i64>
1185  ret <vscale x 2 x i64> %res
1186}
1187
1188define <vscale x 2 x i64> @fcvtzs_dtod_movprfx(<vscale x 2 x double> %a, <vscale x 2 x double> %b) {
1189; CHECK-LABEL: fcvtzs_dtod_movprfx:
1190; CHECK:       // %bb.0:
1191; CHECK-NEXT:    ptrue p0.d
1192; CHECK-NEXT:    movprfx z0, z1
1193; CHECK-NEXT:    fcvtzs z0.d, p0/m, z1.d
1194; CHECK-NEXT:    ret
1195  %res = fptosi <vscale x 2 x double> %b to <vscale x 2 x i64>
1196  ret <vscale x 2 x i64> %res
1197}
1198
1199define <vscale x 8 x i16> @fcvtzu_htoh_movprfx(<vscale x 8 x half> %a, <vscale x 8 x half> %b) {
1200; CHECK-LABEL: fcvtzu_htoh_movprfx:
1201; CHECK:       // %bb.0:
1202; CHECK-NEXT:    ptrue p0.h
1203; CHECK-NEXT:    movprfx z0, z1
1204; CHECK-NEXT:    fcvtzu z0.h, p0/m, z1.h
1205; CHECK-NEXT:    ret
1206  %res = fptoui <vscale x 8 x half> %b to <vscale x 8 x i16>
1207  ret <vscale x 8 x i16> %res
1208}
1209
1210define <vscale x 4 x i32> @fcvtzu_stos_movprfx(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {
1211; CHECK-LABEL: fcvtzu_stos_movprfx:
1212; CHECK:       // %bb.0:
1213; CHECK-NEXT:    ptrue p0.s
1214; CHECK-NEXT:    movprfx z0, z1
1215; CHECK-NEXT:    fcvtzu z0.s, p0/m, z1.s
1216; CHECK-NEXT:    ret
1217  %res = fptoui <vscale x 4 x float> %b to <vscale x 4 x i32>
1218  ret <vscale x 4 x i32> %res
1219}
1220
1221define <vscale x 2 x i32> @fcvtzu_dtos_movprfx(<vscale x 2 x double> %a, <vscale x 2 x double> %b) {
1222; CHECK-LABEL: fcvtzu_dtos_movprfx:
1223; CHECK:       // %bb.0:
1224; CHECK-NEXT:    ptrue p0.d
1225; CHECK-NEXT:    movprfx z0, z1
1226; CHECK-NEXT:    fcvtzs z0.d, p0/m, z1.d
1227; CHECK-NEXT:    ret
1228  %res = fptoui <vscale x 2 x double> %b to <vscale x 2 x i32>
1229  ret <vscale x 2 x i32> %res
1230}
1231
1232define <vscale x 2 x i64> @fcvtzu_stod_movprfx(<vscale x 2 x float> %a, <vscale x 2 x float> %b) {
1233; CHECK-LABEL: fcvtzu_stod_movprfx:
1234; CHECK:       // %bb.0:
1235; CHECK-NEXT:    ptrue p0.d
1236; CHECK-NEXT:    movprfx z0, z1
1237; CHECK-NEXT:    fcvtzu z0.d, p0/m, z1.s
1238; CHECK-NEXT:    ret
1239  %res = fptoui <vscale x 2 x float> %b to <vscale x 2 x i64>
1240  ret <vscale x 2 x i64> %res
1241}
1242
1243define <vscale x 4 x i32> @fcvtzu_htos_movprfx(<vscale x 4 x half> %a, <vscale x 4 x half> %b) {
1244; CHECK-LABEL: fcvtzu_htos_movprfx:
1245; CHECK:       // %bb.0:
1246; CHECK-NEXT:    ptrue p0.s
1247; CHECK-NEXT:    movprfx z0, z1
1248; CHECK-NEXT:    fcvtzu z0.s, p0/m, z1.h
1249; CHECK-NEXT:    ret
1250  %res = fptoui <vscale x 4 x half> %b to <vscale x 4 x i32>
1251  ret <vscale x 4 x i32> %res
1252}
1253
1254define <vscale x 2 x i64> @fcvtzu_htod_movprfx(<vscale x 2 x half> %a, <vscale x 2 x half> %b) {
1255; CHECK-LABEL: fcvtzu_htod_movprfx:
1256; CHECK:       // %bb.0:
1257; CHECK-NEXT:    ptrue p0.d
1258; CHECK-NEXT:    movprfx z0, z1
1259; CHECK-NEXT:    fcvtzu z0.d, p0/m, z1.h
1260; CHECK-NEXT:    ret
1261  %res = fptoui <vscale x 2 x half> %b to <vscale x 2 x i64>
1262  ret <vscale x 2 x i64> %res
1263}
1264
1265define <vscale x 2 x i64> @fcvtzu_dtod_movprfx(<vscale x 2 x double> %a, <vscale x 2 x double> %b) {
1266; CHECK-LABEL: fcvtzu_dtod_movprfx:
1267; CHECK:       // %bb.0:
1268; CHECK-NEXT:    ptrue p0.d
1269; CHECK-NEXT:    movprfx z0, z1
1270; CHECK-NEXT:    fcvtzu z0.d, p0/m, z1.d
1271; CHECK-NEXT:    ret
1272  %res = fptoui <vscale x 2 x double> %b to <vscale x 2 x i64>
1273  ret <vscale x 2 x i64> %res
1274}
1275