1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+bf16 < %s | FileCheck %s --check-prefixes=CHECK 3 4; Extracting illegal subvectors 5 6define <vscale x 1 x i32> @extract_nxv1i32_nxv4i32(<vscale x 4 x i32> %vec) nounwind { 7; CHECK-LABEL: extract_nxv1i32_nxv4i32: 8; CHECK: // %bb.0: 9; CHECK-NEXT: ret 10 %retval = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv4i32(<vscale x 4 x i32> %vec, i64 0) 11 ret <vscale x 1 x i32> %retval 12} 13 14define <vscale x 1 x i16> @extract_nxv1i16_nxv6i16(<vscale x 6 x i16> %vec) nounwind { 15; CHECK-LABEL: extract_nxv1i16_nxv6i16: 16; CHECK: // %bb.0: 17; CHECK-NEXT: ret 18 %retval = call <vscale x 1 x i16> @llvm.vector.extract.nxv1i16.nxv6i16(<vscale x 6 x i16> %vec, i64 0) 19 ret <vscale x 1 x i16> %retval 20} 21 22declare <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv4i32(<vscale x 4 x i32>, i64) 23declare <vscale x 1 x i16> @llvm.vector.extract.nxv1i16.nxv6i16(<vscale x 6 x i16>, i64) 24 25; 26; Extract half i1 vector that needs promotion from legal type. 27; 28define <vscale x 8 x i1> @extract_nxv8i1_nxv16i1_0(<vscale x 16 x i1> %in) { 29; CHECK-LABEL: extract_nxv8i1_nxv16i1_0: 30; CHECK: // %bb.0: 31; CHECK-NEXT: punpklo p0.h, p0.b 32; CHECK-NEXT: ret 33 %res = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv16i1(<vscale x 16 x i1> %in, i64 0) 34 ret <vscale x 8 x i1> %res 35} 36 37define <vscale x 8 x i1> @extract_nxv8i1_nxv16i1_8(<vscale x 16 x i1> %in) { 38; CHECK-LABEL: extract_nxv8i1_nxv16i1_8: 39; CHECK: // %bb.0: 40; CHECK-NEXT: punpkhi p0.h, p0.b 41; CHECK-NEXT: ret 42 %res = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv16i1(<vscale x 16 x i1> %in, i64 8) 43 ret <vscale x 8 x i1> %res 44} 45 46declare <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv16i1(<vscale x 16 x i1>, i64) 47 48; 49; Extract i1 vector that needs widening from one that needs widening. 50; 51define <vscale x 14 x i1> @extract_nxv14i1_nxv28i1_0(<vscale x 28 x i1> %in) { 52; CHECK-LABEL: extract_nxv14i1_nxv28i1_0: 53; CHECK: // %bb.0: 54; CHECK-NEXT: ret 55 %res = call <vscale x 14 x i1> @llvm.vector.extract.nxv14i1.nxv28i1(<vscale x 28 x i1> %in, i64 0) 56 ret <vscale x 14 x i1> %res 57} 58 59define <vscale x 14 x i1> @extract_nxv14i1_nxv28i1_14(<vscale x 28 x i1> %in) uwtable { 60; CHECK-LABEL: extract_nxv14i1_nxv28i1_14: 61; CHECK: // %bb.0: 62; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill 63; CHECK-NEXT: .cfi_def_cfa_offset 16 64; CHECK-NEXT: .cfi_offset w29, -16 65; CHECK-NEXT: addvl sp, sp, #-1 66; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG 67; CHECK-NEXT: punpkhi p2.h, p1.b 68; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Folded Spill 69; CHECK-NEXT: punpklo p1.h, p1.b 70; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Folded Spill 71; CHECK-NEXT: punpklo p2.h, p2.b 72; CHECK-NEXT: punpkhi p3.h, p1.b 73; CHECK-NEXT: punpkhi p4.h, p2.b 74; CHECK-NEXT: punpklo p2.h, p2.b 75; CHECK-NEXT: uzp1 p4.s, p4.s, p0.s 76; CHECK-NEXT: punpkhi p0.h, p0.b 77; CHECK-NEXT: punpkhi p5.h, p3.b 78; CHECK-NEXT: punpklo p1.h, p1.b 79; CHECK-NEXT: punpkhi p0.h, p0.b 80; CHECK-NEXT: uzp1 p2.s, p5.s, p2.s 81; CHECK-NEXT: punpklo p3.h, p3.b 82; CHECK-NEXT: punpkhi p5.h, p1.b 83; CHECK-NEXT: punpklo p1.h, p1.b 84; CHECK-NEXT: punpkhi p0.h, p0.b 85; CHECK-NEXT: uzp1 p3.s, p5.s, p3.s 86; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Folded Reload 87; CHECK-NEXT: uzp1 p0.s, p0.s, p1.s 88; CHECK-NEXT: uzp1 p1.h, p2.h, p4.h 89; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Folded Reload 90; CHECK-NEXT: uzp1 p0.h, p0.h, p3.h 91; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b 92; CHECK-NEXT: addvl sp, sp, #1 93; CHECK-NEXT: .cfi_def_cfa wsp, 16 94; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload 95; CHECK-NEXT: .cfi_def_cfa_offset 0 96; CHECK-NEXT: .cfi_restore w29 97; CHECK-NEXT: ret 98 %res = call <vscale x 14 x i1> @llvm.vector.extract.nxv14i1.nxv28i1(<vscale x 28 x i1> %in, i64 14) 99 ret <vscale x 14 x i1> %res 100} 101 102declare <vscale x 14 x i1> @llvm.vector.extract.nxv14i1.nxv28i1(<vscale x 28 x i1>, i64) 103 104; 105; Extract half i1 vector that needs promotion from one that needs splitting. 106; 107define <vscale x 8 x i1> @extract_nxv8i1_nxv32i1_0(<vscale x 32 x i1> %in) { 108; CHECK-LABEL: extract_nxv8i1_nxv32i1_0: 109; CHECK: // %bb.0: 110; CHECK-NEXT: punpklo p0.h, p0.b 111; CHECK-NEXT: ret 112 %res = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv32i1(<vscale x 32 x i1> %in, i64 0) 113 ret <vscale x 8 x i1> %res 114} 115 116define <vscale x 8 x i1> @extract_nxv8i1_nxv32i1_8(<vscale x 32 x i1> %in) { 117; CHECK-LABEL: extract_nxv8i1_nxv32i1_8: 118; CHECK: // %bb.0: 119; CHECK-NEXT: punpkhi p0.h, p0.b 120; CHECK-NEXT: ret 121 %res = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv32i1(<vscale x 32 x i1> %in, i64 8) 122 ret <vscale x 8 x i1> %res 123} 124 125define <vscale x 8 x i1> @extract_nxv8i1_nxv32i1_16(<vscale x 32 x i1> %in) { 126; CHECK-LABEL: extract_nxv8i1_nxv32i1_16: 127; CHECK: // %bb.0: 128; CHECK-NEXT: punpklo p0.h, p1.b 129; CHECK-NEXT: ret 130 %res = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv32i1(<vscale x 32 x i1> %in, i64 16) 131 ret <vscale x 8 x i1> %res 132} 133 134define <vscale x 8 x i1> @extract_nxv8i1_nxv32i1_24(<vscale x 32 x i1> %in) { 135; CHECK-LABEL: extract_nxv8i1_nxv32i1_24: 136; CHECK: // %bb.0: 137; CHECK-NEXT: punpkhi p0.h, p1.b 138; CHECK-NEXT: ret 139 %res = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv32i1(<vscale x 32 x i1> %in, i64 24) 140 ret <vscale x 8 x i1> %res 141} 142 143declare <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv32i1(<vscale x 32 x i1>, i64) 144 145; 146; Extract 1/4th i1 vector that needs promotion from legal type. 147; 148define <vscale x 4 x i1> @extract_nxv4i1_nxv16i1_0(<vscale x 16 x i1> %in) { 149; CHECK-LABEL: extract_nxv4i1_nxv16i1_0: 150; CHECK: // %bb.0: 151; CHECK-NEXT: punpklo p0.h, p0.b 152; CHECK-NEXT: punpklo p0.h, p0.b 153; CHECK-NEXT: ret 154 %res = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1> %in, i64 0) 155 ret <vscale x 4 x i1> %res 156} 157 158define <vscale x 4 x i1> @extract_nxv4i1_nxv16i1_4(<vscale x 16 x i1> %in) { 159; CHECK-LABEL: extract_nxv4i1_nxv16i1_4: 160; CHECK: // %bb.0: 161; CHECK-NEXT: punpklo p0.h, p0.b 162; CHECK-NEXT: punpkhi p0.h, p0.b 163; CHECK-NEXT: ret 164 %res = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1> %in, i64 4) 165 ret <vscale x 4 x i1> %res 166} 167 168define <vscale x 4 x i1> @extract_nxv4i1_nxv16i1_8(<vscale x 16 x i1> %in) { 169; CHECK-LABEL: extract_nxv4i1_nxv16i1_8: 170; CHECK: // %bb.0: 171; CHECK-NEXT: punpkhi p0.h, p0.b 172; CHECK-NEXT: punpklo p0.h, p0.b 173; CHECK-NEXT: ret 174 %res = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1> %in, i64 8) 175 ret <vscale x 4 x i1> %res 176} 177 178define <vscale x 4 x i1> @extract_nxv4i1_nxv16i1_12(<vscale x 16 x i1> %in) { 179; CHECK-LABEL: extract_nxv4i1_nxv16i1_12: 180; CHECK: // %bb.0: 181; CHECK-NEXT: punpkhi p0.h, p0.b 182; CHECK-NEXT: punpkhi p0.h, p0.b 183; CHECK-NEXT: ret 184 %res = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1> %in, i64 12) 185 ret <vscale x 4 x i1> %res 186} 187 188declare <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1>, i64) 189 190; 191; Extract 1/8th i1 vector that needs promotion from legal type. 192; 193define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_0(<vscale x 16 x i1> %in) { 194; CHECK-LABEL: extract_nxv2i1_nxv16i1_0: 195; CHECK: // %bb.0: 196; CHECK-NEXT: punpklo p0.h, p0.b 197; CHECK-NEXT: punpklo p0.h, p0.b 198; CHECK-NEXT: punpklo p0.h, p0.b 199; CHECK-NEXT: ret 200 %res = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %in, i64 0) 201 ret <vscale x 2 x i1> %res 202} 203 204define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_2(<vscale x 16 x i1> %in) { 205; CHECK-LABEL: extract_nxv2i1_nxv16i1_2: 206; CHECK: // %bb.0: 207; CHECK-NEXT: punpklo p0.h, p0.b 208; CHECK-NEXT: punpklo p0.h, p0.b 209; CHECK-NEXT: punpkhi p0.h, p0.b 210; CHECK-NEXT: ret 211 %res = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %in, i64 2) 212 ret <vscale x 2 x i1> %res 213} 214 215define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_4(<vscale x 16 x i1> %in) { 216; CHECK-LABEL: extract_nxv2i1_nxv16i1_4: 217; CHECK: // %bb.0: 218; CHECK-NEXT: punpklo p0.h, p0.b 219; CHECK-NEXT: punpkhi p0.h, p0.b 220; CHECK-NEXT: punpklo p0.h, p0.b 221; CHECK-NEXT: ret 222 %res = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %in, i64 4) 223 ret <vscale x 2 x i1> %res 224} 225 226define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_6(<vscale x 16 x i1> %in) { 227; CHECK-LABEL: extract_nxv2i1_nxv16i1_6: 228; CHECK: // %bb.0: 229; CHECK-NEXT: punpklo p0.h, p0.b 230; CHECK-NEXT: punpkhi p0.h, p0.b 231; CHECK-NEXT: punpkhi p0.h, p0.b 232; CHECK-NEXT: ret 233 %res = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %in, i64 6) 234 ret <vscale x 2 x i1> %res 235} 236 237define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_8(<vscale x 16 x i1> %in) { 238; CHECK-LABEL: extract_nxv2i1_nxv16i1_8: 239; CHECK: // %bb.0: 240; CHECK-NEXT: punpkhi p0.h, p0.b 241; CHECK-NEXT: punpklo p0.h, p0.b 242; CHECK-NEXT: punpklo p0.h, p0.b 243; CHECK-NEXT: ret 244 %res = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %in, i64 8) 245 ret <vscale x 2 x i1> %res 246} 247 248define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_10(<vscale x 16 x i1> %in) { 249; CHECK-LABEL: extract_nxv2i1_nxv16i1_10: 250; CHECK: // %bb.0: 251; CHECK-NEXT: punpkhi p0.h, p0.b 252; CHECK-NEXT: punpklo p0.h, p0.b 253; CHECK-NEXT: punpkhi p0.h, p0.b 254; CHECK-NEXT: ret 255 %res = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %in, i64 10) 256 ret <vscale x 2 x i1> %res 257} 258 259define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_12(<vscale x 16 x i1> %in) { 260; CHECK-LABEL: extract_nxv2i1_nxv16i1_12: 261; CHECK: // %bb.0: 262; CHECK-NEXT: punpkhi p0.h, p0.b 263; CHECK-NEXT: punpkhi p0.h, p0.b 264; CHECK-NEXT: punpklo p0.h, p0.b 265; CHECK-NEXT: ret 266 %res = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %in, i64 12) 267 ret <vscale x 2 x i1> %res 268} 269 270define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_14(<vscale x 16 x i1> %in) { 271; CHECK-LABEL: extract_nxv2i1_nxv16i1_14: 272; CHECK: // %bb.0: 273; CHECK-NEXT: punpkhi p0.h, p0.b 274; CHECK-NEXT: punpkhi p0.h, p0.b 275; CHECK-NEXT: punpkhi p0.h, p0.b 276; CHECK-NEXT: ret 277 %res = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %in, i64 14) 278 ret <vscale x 2 x i1> %res 279} 280 281declare <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1>, i64) 282 283; 284; Extract i1 vector that needs promotion from one that needs widening. 285; 286define <vscale x 4 x i1> @extract_nxv4i1_nxv12i1_0(<vscale x 12 x i1> %in) { 287; CHECK-LABEL: extract_nxv4i1_nxv12i1_0: 288; CHECK: // %bb.0: 289; CHECK-NEXT: punpklo p0.h, p0.b 290; CHECK-NEXT: punpklo p0.h, p0.b 291; CHECK-NEXT: ret 292 %res = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv12i1(<vscale x 12 x i1> %in, i64 0) 293 ret <vscale x 4 x i1> %res 294} 295 296define <vscale x 4 x i1> @extract_nxv4i1_nxv12i1_4(<vscale x 12 x i1> %in) { 297; CHECK-LABEL: extract_nxv4i1_nxv12i1_4: 298; CHECK: // %bb.0: 299; CHECK-NEXT: punpklo p0.h, p0.b 300; CHECK-NEXT: punpkhi p0.h, p0.b 301; CHECK-NEXT: ret 302 %res = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv12i1(<vscale x 12 x i1> %in, i64 4) 303 ret <vscale x 4 x i1> %res 304} 305 306define <vscale x 4 x i1> @extract_nxv4i1_nxv12i1_8(<vscale x 12 x i1> %in) { 307; CHECK-LABEL: extract_nxv4i1_nxv12i1_8: 308; CHECK: // %bb.0: 309; CHECK-NEXT: punpkhi p0.h, p0.b 310; CHECK-NEXT: punpklo p0.h, p0.b 311; CHECK-NEXT: ret 312 %res = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv12i1(<vscale x 12 x i1> %in, i64 8) 313 ret <vscale x 4 x i1> %res 314} 315 316declare <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv12i1(<vscale x 12 x i1>, i64) 317 318; 319; Extract 1/8th i8 vector that needs promotion from legal type. 320; 321define <vscale x 2 x i8> @extract_nxv2i8_nxv16i8_0(<vscale x 16 x i8> %in) { 322; CHECK-LABEL: extract_nxv2i8_nxv16i8_0: 323; CHECK: // %bb.0: 324; CHECK-NEXT: uunpklo z0.h, z0.b 325; CHECK-NEXT: uunpklo z0.s, z0.h 326; CHECK-NEXT: uunpklo z0.d, z0.s 327; CHECK-NEXT: ret 328 %res = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> %in, i64 0) 329 ret <vscale x 2 x i8> %res 330} 331 332define <vscale x 2 x i8> @extract_nxv2i8_nxv16i8_2(<vscale x 16 x i8> %in) { 333; CHECK-LABEL: extract_nxv2i8_nxv16i8_2: 334; CHECK: // %bb.0: 335; CHECK-NEXT: uunpklo z0.h, z0.b 336; CHECK-NEXT: uunpklo z0.s, z0.h 337; CHECK-NEXT: uunpkhi z0.d, z0.s 338; CHECK-NEXT: ret 339 %res = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> %in, i64 2) 340 ret <vscale x 2 x i8> %res 341} 342 343define <vscale x 2 x i8> @extract_nxv2i8_nxv16i8_4(<vscale x 16 x i8> %in) { 344; CHECK-LABEL: extract_nxv2i8_nxv16i8_4: 345; CHECK: // %bb.0: 346; CHECK-NEXT: uunpklo z0.h, z0.b 347; CHECK-NEXT: uunpkhi z0.s, z0.h 348; CHECK-NEXT: uunpklo z0.d, z0.s 349; CHECK-NEXT: ret 350 %res = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> %in, i64 4) 351 ret <vscale x 2 x i8> %res 352} 353 354define <vscale x 2 x i8> @extract_nxv2i8_nxv16i8_6(<vscale x 16 x i8> %in) { 355; CHECK-LABEL: extract_nxv2i8_nxv16i8_6: 356; CHECK: // %bb.0: 357; CHECK-NEXT: uunpklo z0.h, z0.b 358; CHECK-NEXT: uunpkhi z0.s, z0.h 359; CHECK-NEXT: uunpkhi z0.d, z0.s 360; CHECK-NEXT: ret 361 %res = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> %in, i64 6) 362 ret <vscale x 2 x i8> %res 363} 364 365define <vscale x 2 x i8> @extract_nxv2i8_nxv16i8_8(<vscale x 16 x i8> %in) { 366; CHECK-LABEL: extract_nxv2i8_nxv16i8_8: 367; CHECK: // %bb.0: 368; CHECK-NEXT: uunpkhi z0.h, z0.b 369; CHECK-NEXT: uunpklo z0.s, z0.h 370; CHECK-NEXT: uunpklo z0.d, z0.s 371; CHECK-NEXT: ret 372 %res = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> %in, i64 8) 373 ret <vscale x 2 x i8> %res 374} 375 376define <vscale x 2 x i8> @extract_nxv2i8_nxv16i8_10(<vscale x 16 x i8> %in) { 377; CHECK-LABEL: extract_nxv2i8_nxv16i8_10: 378; CHECK: // %bb.0: 379; CHECK-NEXT: uunpkhi z0.h, z0.b 380; CHECK-NEXT: uunpklo z0.s, z0.h 381; CHECK-NEXT: uunpkhi z0.d, z0.s 382; CHECK-NEXT: ret 383 %res = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> %in, i64 10) 384 ret <vscale x 2 x i8> %res 385} 386 387define <vscale x 2 x i8> @extract_nxv2i8_nxv16i8_12(<vscale x 16 x i8> %in) { 388; CHECK-LABEL: extract_nxv2i8_nxv16i8_12: 389; CHECK: // %bb.0: 390; CHECK-NEXT: uunpkhi z0.h, z0.b 391; CHECK-NEXT: uunpkhi z0.s, z0.h 392; CHECK-NEXT: uunpklo z0.d, z0.s 393; CHECK-NEXT: ret 394 %res = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> %in, i64 12) 395 ret <vscale x 2 x i8> %res 396} 397 398define <vscale x 2 x i8> @extract_nxv2i8_nxv16i8_14(<vscale x 16 x i8> %in) { 399; CHECK-LABEL: extract_nxv2i8_nxv16i8_14: 400; CHECK: // %bb.0: 401; CHECK-NEXT: uunpkhi z0.h, z0.b 402; CHECK-NEXT: uunpkhi z0.s, z0.h 403; CHECK-NEXT: uunpkhi z0.d, z0.s 404; CHECK-NEXT: ret 405 %res = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8> %in, i64 14) 406 ret <vscale x 2 x i8> %res 407} 408 409declare <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv16i8(<vscale x 16 x i8>, i64) 410 411; 412; Extract i8 vector that needs promotion from one that needs widening. 413; 414define <vscale x 4 x i8> @extract_nxv4i8_nxv12i8_0(<vscale x 12 x i8> %in) { 415; CHECK-LABEL: extract_nxv4i8_nxv12i8_0: 416; CHECK: // %bb.0: 417; CHECK-NEXT: uunpklo z0.h, z0.b 418; CHECK-NEXT: uunpklo z0.s, z0.h 419; CHECK-NEXT: ret 420 %res = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv12i8(<vscale x 12 x i8> %in, i64 0) 421 ret <vscale x 4 x i8> %res 422} 423 424define <vscale x 4 x i8> @extract_nxv4i8_nxv12i8_4(<vscale x 12 x i8> %in) { 425; CHECK-LABEL: extract_nxv4i8_nxv12i8_4: 426; CHECK: // %bb.0: 427; CHECK-NEXT: uunpklo z0.h, z0.b 428; CHECK-NEXT: uunpkhi z0.s, z0.h 429; CHECK-NEXT: ret 430 %res = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv12i8(<vscale x 12 x i8> %in, i64 4) 431 ret <vscale x 4 x i8> %res 432} 433 434define <vscale x 4 x i8> @extract_nxv4i8_nxv12i8_8(<vscale x 12 x i8> %in) { 435; CHECK-LABEL: extract_nxv4i8_nxv12i8_8: 436; CHECK: // %bb.0: 437; CHECK-NEXT: uunpkhi z0.h, z0.b 438; CHECK-NEXT: uunpklo z0.s, z0.h 439; CHECK-NEXT: ret 440 %res = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv12i8(<vscale x 12 x i8> %in, i64 8) 441 ret <vscale x 4 x i8> %res 442} 443 444declare <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv12i8(<vscale x 12 x i8>, i64) 445 446; 447; Extract i8 vector that needs both widening + promotion from one that needs widening. 448; (nxv6i8 -> nxv8i8 -> nxv8i16) 449; 450define <vscale x 6 x i8> @extract_nxv6i8_nxv12i8_0(<vscale x 12 x i8> %in) { 451; CHECK-LABEL: extract_nxv6i8_nxv12i8_0: 452; CHECK: // %bb.0: 453; CHECK-NEXT: uunpklo z0.h, z0.b 454; CHECK-NEXT: ret 455 %res = call <vscale x 6 x i8> @llvm.vector.extract.nxv6i8.nxv12i8(<vscale x 12 x i8> %in, i64 0) 456 ret <vscale x 6 x i8> %res 457} 458 459define <vscale x 6 x i8> @extract_nxv6i8_nxv12i8_6(<vscale x 12 x i8> %in) { 460; CHECK-LABEL: extract_nxv6i8_nxv12i8_6: 461; CHECK: // %bb.0: 462; CHECK-NEXT: uunpkhi z1.h, z0.b 463; CHECK-NEXT: uunpklo z0.h, z0.b 464; CHECK-NEXT: uunpklo z1.s, z1.h 465; CHECK-NEXT: uunpkhi z0.s, z0.h 466; CHECK-NEXT: uunpkhi z2.d, z1.s 467; CHECK-NEXT: uunpklo z1.d, z1.s 468; CHECK-NEXT: uunpkhi z0.d, z0.s 469; CHECK-NEXT: uzp1 z2.s, z2.s, z0.s 470; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s 471; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h 472; CHECK-NEXT: ret 473 %res = call <vscale x 6 x i8> @llvm.vector.extract.nxv6i8.nxv12i8(<vscale x 12 x i8> %in, i64 6) 474 ret <vscale x 6 x i8> %res 475} 476 477declare <vscale x 6 x i8> @llvm.vector.extract.nxv6i8.nxv12i8(<vscale x 12 x i8>, i64) 478 479; 480; Extract half i8 vector that needs promotion from one that needs splitting. 481; 482define <vscale x 8 x i8> @extract_nxv8i8_nxv32i8_0(<vscale x 32 x i8> %in) { 483; CHECK-LABEL: extract_nxv8i8_nxv32i8_0: 484; CHECK: // %bb.0: 485; CHECK-NEXT: uunpklo z0.h, z0.b 486; CHECK-NEXT: ret 487 %res = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> %in, i64 0) 488 ret <vscale x 8 x i8> %res 489} 490 491define <vscale x 8 x i8> @extract_nxv8i8_nxv32i8_8(<vscale x 32 x i8> %in) { 492; CHECK-LABEL: extract_nxv8i8_nxv32i8_8: 493; CHECK: // %bb.0: 494; CHECK-NEXT: uunpkhi z0.h, z0.b 495; CHECK-NEXT: ret 496 %res = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> %in, i64 8) 497 ret <vscale x 8 x i8> %res 498} 499 500define <vscale x 8 x i8> @extract_nxv8i8_nxv32i8_16(<vscale x 32 x i8> %in) { 501; CHECK-LABEL: extract_nxv8i8_nxv32i8_16: 502; CHECK: // %bb.0: 503; CHECK-NEXT: uunpklo z0.h, z1.b 504; CHECK-NEXT: ret 505 %res = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> %in, i64 16) 506 ret <vscale x 8 x i8> %res 507} 508 509define <vscale x 8 x i8> @extract_nxv8i8_nxv32i8_24(<vscale x 32 x i8> %in) { 510; CHECK-LABEL: extract_nxv8i8_nxv32i8_24: 511; CHECK: // %bb.0: 512; CHECK-NEXT: uunpkhi z0.h, z1.b 513; CHECK-NEXT: ret 514 %res = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> %in, i64 24) 515 ret <vscale x 8 x i8> %res 516} 517 518declare <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8>, i64) 519 520; 521; Extract half i8 vector that needs promotion from legal type. 522; 523define <vscale x 8 x i8> @extract_nxv8i8_nxv16i8_0(<vscale x 16 x i8> %in) { 524; CHECK-LABEL: extract_nxv8i8_nxv16i8_0: 525; CHECK: // %bb.0: 526; CHECK-NEXT: uunpklo z0.h, z0.b 527; CHECK-NEXT: ret 528 %res = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> %in, i64 0) 529 ret <vscale x 8 x i8> %res 530} 531 532define <vscale x 8 x i8> @extract_nxv8i8_nxv16i8_8(<vscale x 16 x i8> %in) { 533; CHECK-LABEL: extract_nxv8i8_nxv16i8_8: 534; CHECK: // %bb.0: 535; CHECK-NEXT: uunpkhi z0.h, z0.b 536; CHECK-NEXT: ret 537 %res = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> %in, i64 8) 538 ret <vscale x 8 x i8> %res 539} 540 541declare <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8>, i64) 542 543; 544; Extract i8 vector that needs widening from one that needs widening. 545; 546define <vscale x 14 x i8> @extract_nxv14i8_nxv28i8_0(<vscale x 28 x i8> %in) { 547; CHECK-LABEL: extract_nxv14i8_nxv28i8_0: 548; CHECK: // %bb.0: 549; CHECK-NEXT: ret 550 %res = call <vscale x 14 x i8> @llvm.vector.extract.nxv14i8.nxv28i8(<vscale x 28 x i8> %in, i64 0) 551 ret <vscale x 14 x i8> %res 552} 553 554define <vscale x 14 x i8> @extract_nxv14i8_nxv28i8_14(<vscale x 28 x i8> %in) { 555; CHECK-LABEL: extract_nxv14i8_nxv28i8_14: 556; CHECK: // %bb.0: 557; CHECK-NEXT: uunpkhi z0.h, z0.b 558; CHECK-NEXT: uunpklo z2.h, z1.b 559; CHECK-NEXT: uunpkhi z1.h, z1.b 560; CHECK-NEXT: uunpkhi z0.s, z0.h 561; CHECK-NEXT: uunpklo z4.s, z2.h 562; CHECK-NEXT: uunpkhi z2.s, z2.h 563; CHECK-NEXT: uunpklo z1.s, z1.h 564; CHECK-NEXT: uunpkhi z0.d, z0.s 565; CHECK-NEXT: uunpklo z5.d, z4.s 566; CHECK-NEXT: uunpkhi z4.d, z4.s 567; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s 568; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h 569; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b 570; CHECK-NEXT: uunpklo z0.h, z0.b 571; CHECK-NEXT: uunpklo z3.s, z0.h 572; CHECK-NEXT: uunpkhi z0.s, z0.h 573; CHECK-NEXT: uunpklo z3.d, z3.s 574; CHECK-NEXT: uzp1 z3.s, z3.s, z5.s 575; CHECK-NEXT: uzp1 z0.h, z3.h, z0.h 576; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b 577; CHECK-NEXT: uunpklo z0.h, z0.b 578; CHECK-NEXT: uunpkhi z3.s, z0.h 579; CHECK-NEXT: uunpklo z0.s, z0.h 580; CHECK-NEXT: uunpkhi z3.d, z3.s 581; CHECK-NEXT: uzp1 z3.s, z4.s, z3.s 582; CHECK-NEXT: uunpklo z4.d, z2.s 583; CHECK-NEXT: uunpkhi z2.d, z2.s 584; CHECK-NEXT: uzp1 z0.h, z0.h, z3.h 585; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b 586; CHECK-NEXT: uunpklo z0.h, z0.b 587; CHECK-NEXT: uunpkhi z3.s, z0.h 588; CHECK-NEXT: uunpklo z0.s, z0.h 589; CHECK-NEXT: uunpklo z3.d, z3.s 590; CHECK-NEXT: uzp1 z3.s, z3.s, z4.s 591; CHECK-NEXT: uzp1 z0.h, z0.h, z3.h 592; CHECK-NEXT: uzp1 z3.b, z0.b, z0.b 593; CHECK-NEXT: uunpkhi z3.h, z3.b 594; CHECK-NEXT: uunpklo z4.s, z3.h 595; CHECK-NEXT: uunpkhi z3.s, z3.h 596; CHECK-NEXT: uunpkhi z4.d, z4.s 597; CHECK-NEXT: uzp1 z2.s, z2.s, z4.s 598; CHECK-NEXT: uunpklo z4.d, z1.s 599; CHECK-NEXT: uunpkhi z1.d, z1.s 600; CHECK-NEXT: uzp1 z2.h, z2.h, z3.h 601; CHECK-NEXT: uzp1 z2.b, z0.b, z2.b 602; CHECK-NEXT: uunpkhi z2.h, z2.b 603; CHECK-NEXT: uunpklo z3.s, z2.h 604; CHECK-NEXT: uunpkhi z2.s, z2.h 605; CHECK-NEXT: uunpklo z3.d, z3.s 606; CHECK-NEXT: uzp1 z3.s, z3.s, z4.s 607; CHECK-NEXT: uzp1 z2.h, z3.h, z2.h 608; CHECK-NEXT: uzp1 z2.b, z0.b, z2.b 609; CHECK-NEXT: uunpkhi z2.h, z2.b 610; CHECK-NEXT: uunpkhi z3.s, z2.h 611; CHECK-NEXT: uunpklo z2.s, z2.h 612; CHECK-NEXT: uunpkhi z3.d, z3.s 613; CHECK-NEXT: uzp1 z1.s, z1.s, z3.s 614; CHECK-NEXT: uzp1 z1.h, z2.h, z1.h 615; CHECK-NEXT: uzp1 z1.b, z0.b, z1.b 616; CHECK-NEXT: uunpkhi z1.h, z1.b 617; CHECK-NEXT: uunpkhi z2.s, z1.h 618; CHECK-NEXT: uunpklo z1.s, z1.h 619; CHECK-NEXT: uunpklo z2.d, z2.s 620; CHECK-NEXT: uzp1 z2.s, z2.s, z0.s 621; CHECK-NEXT: uzp1 z1.h, z1.h, z2.h 622; CHECK-NEXT: uzp1 z0.b, z0.b, z1.b 623; CHECK-NEXT: ret 624 %res = call <vscale x 14 x i8> @llvm.vector.extract.nxv14i8.nxv28i8(<vscale x 28 x i8> %in, i64 14) 625 ret <vscale x 14 x i8> %res 626} 627 628declare <vscale x 14 x i8> @llvm.vector.extract.nxv14i8.nxv28i8(<vscale x 28 x i8>, i64) 629 630; 631; Extract 1/4th i8 vector that needs promotion from legal type. 632; 633define <vscale x 4 x i8> @extract_nxv4i8_nxv16i8_0(<vscale x 16 x i8> %in) { 634; CHECK-LABEL: extract_nxv4i8_nxv16i8_0: 635; CHECK: // %bb.0: 636; CHECK-NEXT: uunpklo z0.h, z0.b 637; CHECK-NEXT: uunpklo z0.s, z0.h 638; CHECK-NEXT: ret 639 %res = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv16i8(<vscale x 16 x i8> %in, i64 0) 640 ret <vscale x 4 x i8> %res 641} 642 643define <vscale x 4 x i8> @extract_nxv4i8_nxv16i8_4(<vscale x 16 x i8> %in) { 644; CHECK-LABEL: extract_nxv4i8_nxv16i8_4: 645; CHECK: // %bb.0: 646; CHECK-NEXT: uunpklo z0.h, z0.b 647; CHECK-NEXT: uunpkhi z0.s, z0.h 648; CHECK-NEXT: ret 649 %res = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv16i8(<vscale x 16 x i8> %in, i64 4) 650 ret <vscale x 4 x i8> %res 651} 652 653define <vscale x 4 x i8> @extract_nxv4i8_nxv16i8_8(<vscale x 16 x i8> %in) { 654; CHECK-LABEL: extract_nxv4i8_nxv16i8_8: 655; CHECK: // %bb.0: 656; CHECK-NEXT: uunpkhi z0.h, z0.b 657; CHECK-NEXT: uunpklo z0.s, z0.h 658; CHECK-NEXT: ret 659 %res = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv16i8(<vscale x 16 x i8> %in, i64 8) 660 ret <vscale x 4 x i8> %res 661} 662 663define <vscale x 4 x i8> @extract_nxv4i8_nxv16i8_12(<vscale x 16 x i8> %in) { 664; CHECK-LABEL: extract_nxv4i8_nxv16i8_12: 665; CHECK: // %bb.0: 666; CHECK-NEXT: uunpkhi z0.h, z0.b 667; CHECK-NEXT: uunpkhi z0.s, z0.h 668; CHECK-NEXT: ret 669 %res = call <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv16i8(<vscale x 16 x i8> %in, i64 12) 670 ret <vscale x 4 x i8> %res 671} 672 673declare <vscale x 4 x i8> @llvm.vector.extract.nxv4i8.nxv16i8(<vscale x 16 x i8>, i64) 674 675; 676; Extract f16 vector that needs promotion from one that needs widening. 677; 678define <vscale x 2 x half> @extract_nxv2f16_nxv6f16_0(<vscale x 6 x half> %in) { 679; CHECK-LABEL: extract_nxv2f16_nxv6f16_0: 680; CHECK: // %bb.0: 681; CHECK-NEXT: uunpklo z0.s, z0.h 682; CHECK-NEXT: uunpklo z0.d, z0.s 683; CHECK-NEXT: ret 684 %res = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv6f16(<vscale x 6 x half> %in, i64 0) 685 ret <vscale x 2 x half> %res 686} 687 688define <vscale x 2 x half> @extract_nxv2f16_nxv6f16_2(<vscale x 6 x half> %in) { 689; CHECK-LABEL: extract_nxv2f16_nxv6f16_2: 690; CHECK: // %bb.0: 691; CHECK-NEXT: uunpklo z0.s, z0.h 692; CHECK-NEXT: uunpkhi z0.d, z0.s 693; CHECK-NEXT: ret 694 %res = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv6f16(<vscale x 6 x half> %in, i64 2) 695 ret <vscale x 2 x half> %res 696} 697 698define <vscale x 2 x half> @extract_nxv2f16_nxv6f16_4(<vscale x 6 x half> %in) { 699; CHECK-LABEL: extract_nxv2f16_nxv6f16_4: 700; CHECK: // %bb.0: 701; CHECK-NEXT: uunpkhi z0.s, z0.h 702; CHECK-NEXT: uunpklo z0.d, z0.s 703; CHECK-NEXT: ret 704 %res = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv6f16(<vscale x 6 x half> %in, i64 4) 705 ret <vscale x 2 x half> %res 706} 707 708declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv6f16(<vscale x 6 x half>, i64) 709 710; 711; Extract half f16 vector that needs promotion from legal type. 712; 713define <vscale x 4 x half> @extract_nxv4f16_nxv8f16_0(<vscale x 8 x half> %in) { 714; CHECK-LABEL: extract_nxv4f16_nxv8f16_0: 715; CHECK: // %bb.0: 716; CHECK-NEXT: uunpklo z0.s, z0.h 717; CHECK-NEXT: ret 718 %res = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half> %in, i64 0) 719 ret <vscale x 4 x half> %res 720} 721 722define <vscale x 4 x half> @extract_nxv4f16_nxv8f16_4(<vscale x 8 x half> %in) { 723; CHECK-LABEL: extract_nxv4f16_nxv8f16_4: 724; CHECK: // %bb.0: 725; CHECK-NEXT: uunpkhi z0.s, z0.h 726; CHECK-NEXT: ret 727 %res = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half> %in, i64 4) 728 ret <vscale x 4 x half> %res 729} 730 731declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half>, i64) 732 733; 734; Extract f16 vector that needs widening from one that needs widening. 735; 736define <vscale x 6 x half> @extract_nxv6f16_nxv12f16_0(<vscale x 12 x half> %in) { 737; CHECK-LABEL: extract_nxv6f16_nxv12f16_0: 738; CHECK: // %bb.0: 739; CHECK-NEXT: ret 740 %res = call <vscale x 6 x half> @llvm.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half> %in, i64 0) 741 ret <vscale x 6 x half> %res 742} 743 744define <vscale x 6 x half> @extract_nxv6f16_nxv12f16_6(<vscale x 12 x half> %in) { 745; CHECK-LABEL: extract_nxv6f16_nxv12f16_6: 746; CHECK: // %bb.0: 747; CHECK-NEXT: uunpklo z1.s, z1.h 748; CHECK-NEXT: uunpkhi z0.s, z0.h 749; CHECK-NEXT: uunpkhi z2.d, z1.s 750; CHECK-NEXT: uunpklo z1.d, z1.s 751; CHECK-NEXT: uunpkhi z0.d, z0.s 752; CHECK-NEXT: uzp1 z2.s, z2.s, z0.s 753; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s 754; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h 755; CHECK-NEXT: ret 756 %res = call <vscale x 6 x half> @llvm.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half> %in, i64 6) 757 ret <vscale x 6 x half> %res 758} 759 760declare <vscale x 6 x half> @llvm.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half>, i64) 761 762; 763; Extract half f16 vector that needs promotion from one that needs splitting. 764; 765define <vscale x 4 x half> @extract_nxv4f16_nxv16f16_0(<vscale x 16 x half> %in) { 766; CHECK-LABEL: extract_nxv4f16_nxv16f16_0: 767; CHECK: // %bb.0: 768; CHECK-NEXT: uunpklo z0.s, z0.h 769; CHECK-NEXT: ret 770 %res = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %in, i64 0) 771 ret <vscale x 4 x half> %res 772} 773 774define <vscale x 4 x half> @extract_nxv4f16_nxv16f16_4(<vscale x 16 x half> %in) { 775; CHECK-LABEL: extract_nxv4f16_nxv16f16_4: 776; CHECK: // %bb.0: 777; CHECK-NEXT: uunpkhi z0.s, z0.h 778; CHECK-NEXT: ret 779 %res = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %in, i64 4) 780 ret <vscale x 4 x half> %res 781} 782 783define <vscale x 4 x half> @extract_nxv4f16_nxv16f16_8(<vscale x 16 x half> %in) { 784; CHECK-LABEL: extract_nxv4f16_nxv16f16_8: 785; CHECK: // %bb.0: 786; CHECK-NEXT: uunpklo z0.s, z1.h 787; CHECK-NEXT: ret 788 %res = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %in, i64 8) 789 ret <vscale x 4 x half> %res 790} 791 792define <vscale x 4 x half> @extract_nxv4f16_nxv16f16_12(<vscale x 16 x half> %in) { 793; CHECK-LABEL: extract_nxv4f16_nxv16f16_12: 794; CHECK: // %bb.0: 795; CHECK-NEXT: uunpkhi z0.s, z1.h 796; CHECK-NEXT: ret 797 %res = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %in, i64 12) 798 ret <vscale x 4 x half> %res 799} 800 801declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half>, i64) 802 803; 804; Extract 1/4th f16 vector that needs promotion from legal type. 805; 806define <vscale x 2 x half> @extract_nxv2f16_nxv8f16_0(<vscale x 8 x half> %in) { 807; CHECK-LABEL: extract_nxv2f16_nxv8f16_0: 808; CHECK: // %bb.0: 809; CHECK-NEXT: uunpklo z0.s, z0.h 810; CHECK-NEXT: uunpklo z0.d, z0.s 811; CHECK-NEXT: ret 812 %res = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half> %in, i64 0) 813 ret <vscale x 2 x half> %res 814} 815 816define <vscale x 2 x half> @extract_nxv2f16_nxv8f16_2(<vscale x 8 x half> %in) { 817; CHECK-LABEL: extract_nxv2f16_nxv8f16_2: 818; CHECK: // %bb.0: 819; CHECK-NEXT: uunpklo z0.s, z0.h 820; CHECK-NEXT: uunpkhi z0.d, z0.s 821; CHECK-NEXT: ret 822 %res = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half> %in, i64 2) 823 ret <vscale x 2 x half> %res 824} 825 826define <vscale x 2 x half> @extract_nxv2f16_nxv8f16_4(<vscale x 8 x half> %in) { 827; CHECK-LABEL: extract_nxv2f16_nxv8f16_4: 828; CHECK: // %bb.0: 829; CHECK-NEXT: uunpkhi z0.s, z0.h 830; CHECK-NEXT: uunpklo z0.d, z0.s 831; CHECK-NEXT: ret 832 %res = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half> %in, i64 4) 833 ret <vscale x 2 x half> %res 834} 835 836define <vscale x 2 x half> @extract_nxv2f16_nxv8f16_6(<vscale x 8 x half> %in) { 837; CHECK-LABEL: extract_nxv2f16_nxv8f16_6: 838; CHECK: // %bb.0: 839; CHECK-NEXT: uunpkhi z0.s, z0.h 840; CHECK-NEXT: uunpkhi z0.d, z0.s 841; CHECK-NEXT: ret 842 %res = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half> %in, i64 6) 843 ret <vscale x 2 x half> %res 844} 845 846declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half>, i64) 847 848; 849; Extract half bf16 vector that needs promotion from legal type. 850; 851define <vscale x 4 x bfloat> @extract_nxv4bf16_nxv8bf16_0(<vscale x 8 x bfloat> %in) { 852; CHECK-LABEL: extract_nxv4bf16_nxv8bf16_0: 853; CHECK: // %bb.0: 854; CHECK-NEXT: uunpklo z0.s, z0.h 855; CHECK-NEXT: ret 856 %res = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat> %in, i64 0) 857 ret <vscale x 4 x bfloat> %res 858} 859 860define <vscale x 4 x bfloat> @extract_nxv4bf16_nxv8bf16_4(<vscale x 8 x bfloat> %in) { 861; CHECK-LABEL: extract_nxv4bf16_nxv8bf16_4: 862; CHECK: // %bb.0: 863; CHECK-NEXT: uunpkhi z0.s, z0.h 864; CHECK-NEXT: ret 865 %res = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat> %in, i64 4) 866 ret <vscale x 4 x bfloat> %res 867} 868 869declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat>, i64) 870 871; 872; Extract bf16 vector that needs widening from one that needs widening. 873; 874define <vscale x 6 x bfloat> @extract_nxv6bf16_nxv12bf16_0(<vscale x 12 x bfloat> %in) { 875; CHECK-LABEL: extract_nxv6bf16_nxv12bf16_0: 876; CHECK: // %bb.0: 877; CHECK-NEXT: ret 878 %res = call <vscale x 6 x bfloat> @llvm.vector.extract.nxv6bf16.nxv12bf16(<vscale x 12 x bfloat> %in, i64 0) 879 ret <vscale x 6 x bfloat> %res 880} 881 882define <vscale x 6 x bfloat> @extract_nxv6bf16_nxv12bf16_6(<vscale x 12 x bfloat> %in) { 883; CHECK-LABEL: extract_nxv6bf16_nxv12bf16_6: 884; CHECK: // %bb.0: 885; CHECK-NEXT: uunpklo z1.s, z1.h 886; CHECK-NEXT: uunpkhi z0.s, z0.h 887; CHECK-NEXT: uunpkhi z2.d, z1.s 888; CHECK-NEXT: uunpklo z1.d, z1.s 889; CHECK-NEXT: uunpkhi z0.d, z0.s 890; CHECK-NEXT: uzp1 z2.s, z2.s, z0.s 891; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s 892; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h 893; CHECK-NEXT: ret 894 %res = call <vscale x 6 x bfloat> @llvm.vector.extract.nxv6bf16.nxv12bf16(<vscale x 12 x bfloat> %in, i64 6) 895 ret <vscale x 6 x bfloat> %res 896} 897 898declare <vscale x 6 x bfloat> @llvm.vector.extract.nxv6bf16.nxv12bf16(<vscale x 12 x bfloat>, i64) 899 900; 901; Extract bf16 vector that needs promotion from one that needs widening. 902; 903define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv6bf16_0(<vscale x 6 x bfloat> %in) { 904; CHECK-LABEL: extract_nxv2bf16_nxv6bf16_0: 905; CHECK: // %bb.0: 906; CHECK-NEXT: uunpklo z0.s, z0.h 907; CHECK-NEXT: uunpklo z0.d, z0.s 908; CHECK-NEXT: ret 909 %res = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv6bf16(<vscale x 6 x bfloat> %in, i64 0) 910 ret <vscale x 2 x bfloat> %res 911} 912 913define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv6bf16_2(<vscale x 6 x bfloat> %in) { 914; CHECK-LABEL: extract_nxv2bf16_nxv6bf16_2: 915; CHECK: // %bb.0: 916; CHECK-NEXT: uunpklo z0.s, z0.h 917; CHECK-NEXT: uunpkhi z0.d, z0.s 918; CHECK-NEXT: ret 919 %res = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv6bf16(<vscale x 6 x bfloat> %in, i64 2) 920 ret <vscale x 2 x bfloat> %res 921} 922 923define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv6bf16_4(<vscale x 6 x bfloat> %in) { 924; CHECK-LABEL: extract_nxv2bf16_nxv6bf16_4: 925; CHECK: // %bb.0: 926; CHECK-NEXT: uunpkhi z0.s, z0.h 927; CHECK-NEXT: uunpklo z0.d, z0.s 928; CHECK-NEXT: ret 929 %res = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv6bf16(<vscale x 6 x bfloat> %in, i64 4) 930 ret <vscale x 2 x bfloat> %res 931} 932 933declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv6bf16(<vscale x 6 x bfloat>, i64) 934 935; 936; Extract 1/4th bf16 vector that needs promotion from legal type. 937; 938define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv8bf16_0(<vscale x 8 x bfloat> %in) { 939; CHECK-LABEL: extract_nxv2bf16_nxv8bf16_0: 940; CHECK: // %bb.0: 941; CHECK-NEXT: uunpklo z0.s, z0.h 942; CHECK-NEXT: uunpklo z0.d, z0.s 943; CHECK-NEXT: ret 944 %res = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat> %in, i64 0) 945 ret <vscale x 2 x bfloat> %res 946} 947 948define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv8bf16_2(<vscale x 8 x bfloat> %in) { 949; CHECK-LABEL: extract_nxv2bf16_nxv8bf16_2: 950; CHECK: // %bb.0: 951; CHECK-NEXT: uunpklo z0.s, z0.h 952; CHECK-NEXT: uunpkhi z0.d, z0.s 953; CHECK-NEXT: ret 954 %res = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat> %in, i64 2) 955 ret <vscale x 2 x bfloat> %res 956} 957 958define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv8bf16_4(<vscale x 8 x bfloat> %in) { 959; CHECK-LABEL: extract_nxv2bf16_nxv8bf16_4: 960; CHECK: // %bb.0: 961; CHECK-NEXT: uunpkhi z0.s, z0.h 962; CHECK-NEXT: uunpklo z0.d, z0.s 963; CHECK-NEXT: ret 964 %res = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat> %in, i64 4) 965 ret <vscale x 2 x bfloat> %res 966} 967 968define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv8bf16_6(<vscale x 8 x bfloat> %in) { 969; CHECK-LABEL: extract_nxv2bf16_nxv8bf16_6: 970; CHECK: // %bb.0: 971; CHECK-NEXT: uunpkhi z0.s, z0.h 972; CHECK-NEXT: uunpkhi z0.d, z0.s 973; CHECK-NEXT: ret 974 %res = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat> %in, i64 6) 975 ret <vscale x 2 x bfloat> %res 976} 977 978declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat>, i64) 979 980; 981; Extract half bf16 vector that needs promotion from one that needs splitting. 982; 983define <vscale x 4 x bfloat> @extract_nxv4bf16_nxv16bf16_0(<vscale x 16 x bfloat> %in) { 984; CHECK-LABEL: extract_nxv4bf16_nxv16bf16_0: 985; CHECK: // %bb.0: 986; CHECK-NEXT: uunpklo z0.s, z0.h 987; CHECK-NEXT: ret 988 %res = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %in, i64 0) 989 ret <vscale x 4 x bfloat> %res 990} 991 992define <vscale x 4 x bfloat> @extract_nxv4bf16_nxv16bf16_4(<vscale x 16 x bfloat> %in) { 993; CHECK-LABEL: extract_nxv4bf16_nxv16bf16_4: 994; CHECK: // %bb.0: 995; CHECK-NEXT: uunpkhi z0.s, z0.h 996; CHECK-NEXT: ret 997 %res = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %in, i64 4) 998 ret <vscale x 4 x bfloat> %res 999} 1000 1001define <vscale x 4 x bfloat> @extract_nxv4bf16_nxv16bf16_8(<vscale x 16 x bfloat> %in) { 1002; CHECK-LABEL: extract_nxv4bf16_nxv16bf16_8: 1003; CHECK: // %bb.0: 1004; CHECK-NEXT: uunpklo z0.s, z1.h 1005; CHECK-NEXT: ret 1006 %res = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %in, i64 8) 1007 ret <vscale x 4 x bfloat> %res 1008} 1009 1010define <vscale x 4 x bfloat> @extract_nxv4bf16_nxv16bf16_12(<vscale x 16 x bfloat> %in) { 1011; CHECK-LABEL: extract_nxv4bf16_nxv16bf16_12: 1012; CHECK: // %bb.0: 1013; CHECK-NEXT: uunpkhi z0.s, z1.h 1014; CHECK-NEXT: ret 1015 %res = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %in, i64 12) 1016 ret <vscale x 4 x bfloat> %res 1017} 1018 1019declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat>, i64) 1020 1021 1022; 1023; Extract from a splat 1024; 1025define <vscale x 2 x float> @extract_nxv2f32_nxv4f32_splat(float %f) { 1026; CHECK-LABEL: extract_nxv2f32_nxv4f32_splat: 1027; CHECK: // %bb.0: 1028; CHECK-NEXT: // kill: def $s0 killed $s0 def $z0 1029; CHECK-NEXT: mov z0.s, s0 1030; CHECK-NEXT: ret 1031 %ins = insertelement <vscale x 4 x float> poison, float %f, i32 0 1032 %splat = shufflevector <vscale x 4 x float> %ins, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer 1033 %ext = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float> %splat, i64 0) 1034 ret <vscale x 2 x float> %ext 1035} 1036 1037define <vscale x 2 x float> @extract_nxv2f32_nxv4f32_splat_const() { 1038; CHECK-LABEL: extract_nxv2f32_nxv4f32_splat_const: 1039; CHECK: // %bb.0: 1040; CHECK-NEXT: fmov z0.s, #1.00000000 1041; CHECK-NEXT: ret 1042 %ext = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float> splat(float 1.0), i64 0) 1043 ret <vscale x 2 x float> %ext 1044} 1045 1046define <vscale x 4 x i32> @extract_nxv4i32_nxv8i32_splat_const() { 1047; CHECK-LABEL: extract_nxv4i32_nxv8i32_splat_const: 1048; CHECK: // %bb.0: 1049; CHECK-NEXT: mov z0.s, #1 // =0x1 1050; CHECK-NEXT: ret 1051 %ext = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> splat(i32 1), i64 0) 1052 ret <vscale x 4 x i32> %ext 1053} 1054 1055define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_all_ones() { 1056; CHECK-LABEL: extract_nxv2i1_nxv16i1_all_ones: 1057; CHECK: // %bb.0: 1058; CHECK-NEXT: ptrue p0.d 1059; CHECK-NEXT: ret 1060 %ext = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> splat(i1 true), i64 0) 1061 ret <vscale x 2 x i1> %ext 1062} 1063 1064define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_all_zero() { 1065; CHECK-LABEL: extract_nxv2i1_nxv16i1_all_zero: 1066; CHECK: // %bb.0: 1067; CHECK-NEXT: pfalse p0.b 1068; CHECK-NEXT: ret 1069 %ext = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> zeroinitializer, i64 0) 1070 ret <vscale x 2 x i1> %ext 1071} 1072 1073declare <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float>, i64) 1074declare <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32>, i64) 1075 1076; 1077; Extract nxv1i1 type from: nxv2i1 1078; 1079 1080define <vscale x 1 x i1> @extract_nxv1i1_nxv2i1_0(<vscale x 2 x i1> %in) { 1081; CHECK-LABEL: extract_nxv1i1_nxv2i1_0: 1082; CHECK: // %bb.0: 1083; CHECK-NEXT: punpklo p0.h, p0.b 1084; CHECK-NEXT: ret 1085 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv2i1(<vscale x 2 x i1> %in, i64 0) 1086 ret <vscale x 1 x i1> %res 1087} 1088 1089define <vscale x 1 x i1> @extract_nxv1i1_nxv2i1_1(<vscale x 2 x i1> %in) { 1090; CHECK-LABEL: extract_nxv1i1_nxv2i1_1: 1091; CHECK: // %bb.0: 1092; CHECK-NEXT: punpkhi p0.h, p0.b 1093; CHECK-NEXT: ret 1094 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv2i1(<vscale x 2 x i1> %in, i64 1) 1095 ret <vscale x 1 x i1> %res 1096} 1097 1098; 1099; Extract nxv1i1 type from: nxv4i1 1100; 1101 1102define <vscale x 1 x i1> @extract_nxv1i1_nxv4i1_0(<vscale x 4 x i1> %in) { 1103; CHECK-LABEL: extract_nxv1i1_nxv4i1_0: 1104; CHECK: // %bb.0: 1105; CHECK-NEXT: punpklo p0.h, p0.b 1106; CHECK-NEXT: punpklo p0.h, p0.b 1107; CHECK-NEXT: ret 1108 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv4i1(<vscale x 4 x i1> %in, i64 0) 1109 ret <vscale x 1 x i1> %res 1110} 1111 1112define <vscale x 1 x i1> @extract_nxv1i1_nxv4i1_1(<vscale x 4 x i1> %in) { 1113; CHECK-LABEL: extract_nxv1i1_nxv4i1_1: 1114; CHECK: // %bb.0: 1115; CHECK-NEXT: punpklo p0.h, p0.b 1116; CHECK-NEXT: punpkhi p0.h, p0.b 1117; CHECK-NEXT: ret 1118 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv4i1(<vscale x 4 x i1> %in, i64 1) 1119 ret <vscale x 1 x i1> %res 1120} 1121 1122define <vscale x 1 x i1> @extract_nxv1i1_nxv4i1_2(<vscale x 4 x i1> %in) { 1123; CHECK-LABEL: extract_nxv1i1_nxv4i1_2: 1124; CHECK: // %bb.0: 1125; CHECK-NEXT: punpkhi p0.h, p0.b 1126; CHECK-NEXT: punpklo p0.h, p0.b 1127; CHECK-NEXT: ret 1128 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv4i1(<vscale x 4 x i1> %in, i64 2) 1129 ret <vscale x 1 x i1> %res 1130} 1131 1132define <vscale x 1 x i1> @extract_nxv1i1_nxv4i1_3(<vscale x 4 x i1> %in) { 1133; CHECK-LABEL: extract_nxv1i1_nxv4i1_3: 1134; CHECK: // %bb.0: 1135; CHECK-NEXT: punpkhi p0.h, p0.b 1136; CHECK-NEXT: punpkhi p0.h, p0.b 1137; CHECK-NEXT: ret 1138 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv4i1(<vscale x 4 x i1> %in, i64 3) 1139 ret <vscale x 1 x i1> %res 1140} 1141 1142; 1143; Extract nxv1i1 type from: nxv8i1 1144; 1145 1146define <vscale x 1 x i1> @extract_nxv1i1_nxv8i1_0(<vscale x 8 x i1> %in) { 1147; CHECK-LABEL: extract_nxv1i1_nxv8i1_0: 1148; CHECK: // %bb.0: 1149; CHECK-NEXT: punpklo p0.h, p0.b 1150; CHECK-NEXT: punpklo p0.h, p0.b 1151; CHECK-NEXT: punpklo p0.h, p0.b 1152; CHECK-NEXT: ret 1153 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv8i1(<vscale x 8 x i1> %in, i64 0) 1154 ret <vscale x 1 x i1> %res 1155} 1156 1157define <vscale x 1 x i1> @extract_nxv1i1_nxv8i1_1(<vscale x 8 x i1> %in) { 1158; CHECK-LABEL: extract_nxv1i1_nxv8i1_1: 1159; CHECK: // %bb.0: 1160; CHECK-NEXT: punpklo p0.h, p0.b 1161; CHECK-NEXT: punpklo p0.h, p0.b 1162; CHECK-NEXT: punpkhi p0.h, p0.b 1163; CHECK-NEXT: ret 1164 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv8i1(<vscale x 8 x i1> %in, i64 1) 1165 ret <vscale x 1 x i1> %res 1166} 1167 1168define <vscale x 1 x i1> @extract_nxv1i1_nxv8i1_2(<vscale x 8 x i1> %in) { 1169; CHECK-LABEL: extract_nxv1i1_nxv8i1_2: 1170; CHECK: // %bb.0: 1171; CHECK-NEXT: punpklo p0.h, p0.b 1172; CHECK-NEXT: punpkhi p0.h, p0.b 1173; CHECK-NEXT: punpklo p0.h, p0.b 1174; CHECK-NEXT: ret 1175 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv8i1(<vscale x 8 x i1> %in, i64 2) 1176 ret <vscale x 1 x i1> %res 1177} 1178 1179define <vscale x 1 x i1> @extract_nxv1i1_nxv8i1_3(<vscale x 8 x i1> %in) { 1180; CHECK-LABEL: extract_nxv1i1_nxv8i1_3: 1181; CHECK: // %bb.0: 1182; CHECK-NEXT: punpklo p0.h, p0.b 1183; CHECK-NEXT: punpkhi p0.h, p0.b 1184; CHECK-NEXT: punpkhi p0.h, p0.b 1185; CHECK-NEXT: ret 1186 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv8i1(<vscale x 8 x i1> %in, i64 3) 1187 ret <vscale x 1 x i1> %res 1188} 1189 1190define <vscale x 1 x i1> @extract_nxv1i1_nxv8i1_4(<vscale x 8 x i1> %in) { 1191; CHECK-LABEL: extract_nxv1i1_nxv8i1_4: 1192; CHECK: // %bb.0: 1193; CHECK-NEXT: punpkhi p0.h, p0.b 1194; CHECK-NEXT: punpklo p0.h, p0.b 1195; CHECK-NEXT: punpklo p0.h, p0.b 1196; CHECK-NEXT: ret 1197 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv8i1(<vscale x 8 x i1> %in, i64 4) 1198 ret <vscale x 1 x i1> %res 1199} 1200 1201define <vscale x 1 x i1> @extract_nxv1i1_nxv8i1_5(<vscale x 8 x i1> %in) { 1202; CHECK-LABEL: extract_nxv1i1_nxv8i1_5: 1203; CHECK: // %bb.0: 1204; CHECK-NEXT: punpkhi p0.h, p0.b 1205; CHECK-NEXT: punpklo p0.h, p0.b 1206; CHECK-NEXT: punpkhi p0.h, p0.b 1207; CHECK-NEXT: ret 1208 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv8i1(<vscale x 8 x i1> %in, i64 5) 1209 ret <vscale x 1 x i1> %res 1210} 1211 1212define <vscale x 1 x i1> @extract_nxv1i1_nxv8i1_6(<vscale x 8 x i1> %in) { 1213; CHECK-LABEL: extract_nxv1i1_nxv8i1_6: 1214; CHECK: // %bb.0: 1215; CHECK-NEXT: punpkhi p0.h, p0.b 1216; CHECK-NEXT: punpkhi p0.h, p0.b 1217; CHECK-NEXT: punpklo p0.h, p0.b 1218; CHECK-NEXT: ret 1219 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv8i1(<vscale x 8 x i1> %in, i64 6) 1220 ret <vscale x 1 x i1> %res 1221} 1222 1223define <vscale x 1 x i1> @extract_nxv1i1_nxv8i1_7(<vscale x 8 x i1> %in) { 1224; CHECK-LABEL: extract_nxv1i1_nxv8i1_7: 1225; CHECK: // %bb.0: 1226; CHECK-NEXT: punpkhi p0.h, p0.b 1227; CHECK-NEXT: punpkhi p0.h, p0.b 1228; CHECK-NEXT: punpkhi p0.h, p0.b 1229; CHECK-NEXT: ret 1230 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv8i1(<vscale x 8 x i1> %in, i64 7) 1231 ret <vscale x 1 x i1> %res 1232} 1233 1234 1235; 1236; Extract nxv1i1 type from: nxv16i1 1237; 1238 1239define <vscale x 1 x i1> @extract_nxv1i1_nxv16i1_0(<vscale x 16 x i1> %in) { 1240; CHECK-LABEL: extract_nxv1i1_nxv16i1_0: 1241; CHECK: // %bb.0: 1242; CHECK-NEXT: punpklo p0.h, p0.b 1243; CHECK-NEXT: punpklo p0.h, p0.b 1244; CHECK-NEXT: punpklo p0.h, p0.b 1245; CHECK-NEXT: punpklo p0.h, p0.b 1246; CHECK-NEXT: ret 1247 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv16i1(<vscale x 16 x i1> %in, i64 0) 1248 ret <vscale x 1 x i1> %res 1249} 1250 1251define <vscale x 1 x i1> @extract_nxv1i1_nxv16i1_1(<vscale x 16 x i1> %in) { 1252; CHECK-LABEL: extract_nxv1i1_nxv16i1_1: 1253; CHECK: // %bb.0: 1254; CHECK-NEXT: punpklo p0.h, p0.b 1255; CHECK-NEXT: punpklo p0.h, p0.b 1256; CHECK-NEXT: punpklo p0.h, p0.b 1257; CHECK-NEXT: punpkhi p0.h, p0.b 1258; CHECK-NEXT: ret 1259 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv16i1(<vscale x 16 x i1> %in, i64 1) 1260 ret <vscale x 1 x i1> %res 1261} 1262 1263define <vscale x 1 x i1> @extract_nxv1i1_nxv16i1_2(<vscale x 16 x i1> %in) { 1264; CHECK-LABEL: extract_nxv1i1_nxv16i1_2: 1265; CHECK: // %bb.0: 1266; CHECK-NEXT: punpklo p0.h, p0.b 1267; CHECK-NEXT: punpklo p0.h, p0.b 1268; CHECK-NEXT: punpkhi p0.h, p0.b 1269; CHECK-NEXT: punpklo p0.h, p0.b 1270; CHECK-NEXT: ret 1271 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv16i1(<vscale x 16 x i1> %in, i64 2) 1272 ret <vscale x 1 x i1> %res 1273} 1274 1275define <vscale x 1 x i1> @extract_nxv1i1_nxv16i1_3(<vscale x 16 x i1> %in) { 1276; CHECK-LABEL: extract_nxv1i1_nxv16i1_3: 1277; CHECK: // %bb.0: 1278; CHECK-NEXT: punpklo p0.h, p0.b 1279; CHECK-NEXT: punpklo p0.h, p0.b 1280; CHECK-NEXT: punpkhi p0.h, p0.b 1281; CHECK-NEXT: punpkhi p0.h, p0.b 1282; CHECK-NEXT: ret 1283 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv16i1(<vscale x 16 x i1> %in, i64 3) 1284 ret <vscale x 1 x i1> %res 1285} 1286 1287define <vscale x 1 x i1> @extract_nxv1i1_nxv16i1_4(<vscale x 16 x i1> %in) { 1288; CHECK-LABEL: extract_nxv1i1_nxv16i1_4: 1289; CHECK: // %bb.0: 1290; CHECK-NEXT: punpklo p0.h, p0.b 1291; CHECK-NEXT: punpkhi p0.h, p0.b 1292; CHECK-NEXT: punpklo p0.h, p0.b 1293; CHECK-NEXT: punpklo p0.h, p0.b 1294; CHECK-NEXT: ret 1295 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv16i1(<vscale x 16 x i1> %in, i64 4) 1296 ret <vscale x 1 x i1> %res 1297} 1298 1299define <vscale x 1 x i1> @extract_nxv1i1_nxv16i1_5(<vscale x 16 x i1> %in) { 1300; CHECK-LABEL: extract_nxv1i1_nxv16i1_5: 1301; CHECK: // %bb.0: 1302; CHECK-NEXT: punpklo p0.h, p0.b 1303; CHECK-NEXT: punpkhi p0.h, p0.b 1304; CHECK-NEXT: punpklo p0.h, p0.b 1305; CHECK-NEXT: punpkhi p0.h, p0.b 1306; CHECK-NEXT: ret 1307 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv16i1(<vscale x 16 x i1> %in, i64 5) 1308 ret <vscale x 1 x i1> %res 1309} 1310 1311define <vscale x 1 x i1> @extract_nxv1i1_nxv16i1_6(<vscale x 16 x i1> %in) { 1312; CHECK-LABEL: extract_nxv1i1_nxv16i1_6: 1313; CHECK: // %bb.0: 1314; CHECK-NEXT: punpklo p0.h, p0.b 1315; CHECK-NEXT: punpkhi p0.h, p0.b 1316; CHECK-NEXT: punpkhi p0.h, p0.b 1317; CHECK-NEXT: punpklo p0.h, p0.b 1318; CHECK-NEXT: ret 1319 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv16i1(<vscale x 16 x i1> %in, i64 6) 1320 ret <vscale x 1 x i1> %res 1321} 1322 1323define <vscale x 1 x i1> @extract_nxv1i1_nxv16i1_7(<vscale x 16 x i1> %in) { 1324; CHECK-LABEL: extract_nxv1i1_nxv16i1_7: 1325; CHECK: // %bb.0: 1326; CHECK-NEXT: punpklo p0.h, p0.b 1327; CHECK-NEXT: punpkhi p0.h, p0.b 1328; CHECK-NEXT: punpkhi p0.h, p0.b 1329; CHECK-NEXT: punpkhi p0.h, p0.b 1330; CHECK-NEXT: ret 1331 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv16i1(<vscale x 16 x i1> %in, i64 7) 1332 ret <vscale x 1 x i1> %res 1333} 1334 1335define <vscale x 1 x i1> @extract_nxv1i1_nxv16i1_8(<vscale x 16 x i1> %in) { 1336; CHECK-LABEL: extract_nxv1i1_nxv16i1_8: 1337; CHECK: // %bb.0: 1338; CHECK-NEXT: punpkhi p0.h, p0.b 1339; CHECK-NEXT: punpklo p0.h, p0.b 1340; CHECK-NEXT: punpklo p0.h, p0.b 1341; CHECK-NEXT: punpklo p0.h, p0.b 1342; CHECK-NEXT: ret 1343 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv16i1(<vscale x 16 x i1> %in, i64 8) 1344 ret <vscale x 1 x i1> %res 1345} 1346 1347define <vscale x 1 x i1> @extract_nxv1i1_nxv16i1_9(<vscale x 16 x i1> %in) { 1348; CHECK-LABEL: extract_nxv1i1_nxv16i1_9: 1349; CHECK: // %bb.0: 1350; CHECK-NEXT: punpkhi p0.h, p0.b 1351; CHECK-NEXT: punpklo p0.h, p0.b 1352; CHECK-NEXT: punpklo p0.h, p0.b 1353; CHECK-NEXT: punpkhi p0.h, p0.b 1354; CHECK-NEXT: ret 1355 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv16i1(<vscale x 16 x i1> %in, i64 9) 1356 ret <vscale x 1 x i1> %res 1357} 1358 1359define <vscale x 1 x i1> @extract_nxv1i1_nxv16i1_10(<vscale x 16 x i1> %in) { 1360; CHECK-LABEL: extract_nxv1i1_nxv16i1_10: 1361; CHECK: // %bb.0: 1362; CHECK-NEXT: punpkhi p0.h, p0.b 1363; CHECK-NEXT: punpklo p0.h, p0.b 1364; CHECK-NEXT: punpkhi p0.h, p0.b 1365; CHECK-NEXT: punpklo p0.h, p0.b 1366; CHECK-NEXT: ret 1367 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv16i1(<vscale x 16 x i1> %in, i64 10) 1368 ret <vscale x 1 x i1> %res 1369} 1370 1371define <vscale x 1 x i1> @extract_nxv1i1_nxv16i1_11(<vscale x 16 x i1> %in) { 1372; CHECK-LABEL: extract_nxv1i1_nxv16i1_11: 1373; CHECK: // %bb.0: 1374; CHECK-NEXT: punpkhi p0.h, p0.b 1375; CHECK-NEXT: punpklo p0.h, p0.b 1376; CHECK-NEXT: punpkhi p0.h, p0.b 1377; CHECK-NEXT: punpkhi p0.h, p0.b 1378; CHECK-NEXT: ret 1379 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv16i1(<vscale x 16 x i1> %in, i64 11) 1380 ret <vscale x 1 x i1> %res 1381} 1382 1383define <vscale x 1 x i1> @extract_nxv1i1_nxv16i1_12(<vscale x 16 x i1> %in) { 1384; CHECK-LABEL: extract_nxv1i1_nxv16i1_12: 1385; CHECK: // %bb.0: 1386; CHECK-NEXT: punpkhi p0.h, p0.b 1387; CHECK-NEXT: punpkhi p0.h, p0.b 1388; CHECK-NEXT: punpklo p0.h, p0.b 1389; CHECK-NEXT: punpklo p0.h, p0.b 1390; CHECK-NEXT: ret 1391 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv16i1(<vscale x 16 x i1> %in, i64 12) 1392 ret <vscale x 1 x i1> %res 1393} 1394 1395define <vscale x 1 x i1> @extract_nxv1i1_nxv16i1_13(<vscale x 16 x i1> %in) { 1396; CHECK-LABEL: extract_nxv1i1_nxv16i1_13: 1397; CHECK: // %bb.0: 1398; CHECK-NEXT: punpkhi p0.h, p0.b 1399; CHECK-NEXT: punpkhi p0.h, p0.b 1400; CHECK-NEXT: punpklo p0.h, p0.b 1401; CHECK-NEXT: punpkhi p0.h, p0.b 1402; CHECK-NEXT: ret 1403 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv16i1(<vscale x 16 x i1> %in, i64 13) 1404 ret <vscale x 1 x i1> %res 1405} 1406 1407define <vscale x 1 x i1> @extract_nxv1i1_nxv16i1_14(<vscale x 16 x i1> %in) { 1408; CHECK-LABEL: extract_nxv1i1_nxv16i1_14: 1409; CHECK: // %bb.0: 1410; CHECK-NEXT: punpkhi p0.h, p0.b 1411; CHECK-NEXT: punpkhi p0.h, p0.b 1412; CHECK-NEXT: punpkhi p0.h, p0.b 1413; CHECK-NEXT: punpklo p0.h, p0.b 1414; CHECK-NEXT: ret 1415 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv16i1(<vscale x 16 x i1> %in, i64 14) 1416 ret <vscale x 1 x i1> %res 1417} 1418 1419define <vscale x 1 x i1> @extract_nxv1i1_nxv16i1_15(<vscale x 16 x i1> %in) { 1420; CHECK-LABEL: extract_nxv1i1_nxv16i1_15: 1421; CHECK: // %bb.0: 1422; CHECK-NEXT: punpkhi p0.h, p0.b 1423; CHECK-NEXT: punpkhi p0.h, p0.b 1424; CHECK-NEXT: punpkhi p0.h, p0.b 1425; CHECK-NEXT: punpkhi p0.h, p0.b 1426; CHECK-NEXT: ret 1427 %res = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv16i1(<vscale x 16 x i1> %in, i64 15) 1428 ret <vscale x 1 x i1> %res 1429} 1430 1431declare <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv2i1(<vscale x 2 x i1>, i64) 1432declare <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv4i1(<vscale x 4 x i1>, i64) 1433declare <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv8i1(<vscale x 8 x i1>, i64) 1434declare <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv16i1(<vscale x 16 x i1>, i64) 1435