xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-extload-icmp.ll (revision 4c82f56d8fb9266f46d11c293aa10f53153ecf69) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s | FileCheck %s
3
4target triple = "aarch64-unknown-linux-gnu"
5
6define <vscale x 8 x i8> @extload_icmp_nxv8i8(ptr %in) #0 {
7; CHECK-LABEL: extload_icmp_nxv8i8:
8; CHECK:       // %bb.0:
9; CHECK-NEXT:    ptrue p0.h
10; CHECK-NEXT:    ld1b { z0.h }, p0/z, [x0]
11; CHECK-NEXT:    cnot z0.h, p0/m, z0.h
12; CHECK-NEXT:    ret
13  %ld = load <vscale x 8 x i8>, ptr %in
14  %cmp = icmp eq <vscale x 8 x i8> %ld, zeroinitializer
15  %ex = zext <vscale x 8 x i1> %cmp to <vscale x 8 x i8>
16  ret <vscale x 8 x i8> %ex
17}
18
19define <vscale x 16 x i8> @extload_icmp_nxv16i8(ptr %in) #0 {
20; CHECK-LABEL: extload_icmp_nxv16i8:
21; CHECK:       // %bb.0:
22; CHECK-NEXT:    ptrue p0.b
23; CHECK-NEXT:    ld1b { z0.b }, p0/z, [x0]
24; CHECK-NEXT:    cnot z0.b, p0/m, z0.b
25; CHECK-NEXT:    ret
26  %ld = load <vscale x 16 x i8>, ptr %in
27  %cmp = icmp eq <vscale x 16 x i8> %ld, zeroinitializer
28  %ex = zext <vscale x 16 x i1> %cmp to <vscale x 16 x i8>
29  ret <vscale x 16 x i8> %ex
30}
31
32define <vscale x 4 x i16> @extload_icmp_nxv4i16(ptr %in) #0 {
33; CHECK-LABEL: extload_icmp_nxv4i16:
34; CHECK:       // %bb.0:
35; CHECK-NEXT:    ptrue p0.s
36; CHECK-NEXT:    ld1h { z0.s }, p0/z, [x0]
37; CHECK-NEXT:    cnot z0.s, p0/m, z0.s
38; CHECK-NEXT:    ret
39  %ld = load <vscale x 4 x i16>, ptr %in
40  %cmp = icmp eq <vscale x 4 x i16> %ld, zeroinitializer
41  %ex = zext <vscale x 4 x i1> %cmp to <vscale x 4 x i16>
42  ret <vscale x 4 x i16> %ex
43}
44
45define <vscale x 8 x i16> @extload_icmp_nxv8i16(ptr %in) #0 {
46; CHECK-LABEL: extload_icmp_nxv8i16:
47; CHECK:       // %bb.0:
48; CHECK-NEXT:    ptrue p0.h
49; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x0]
50; CHECK-NEXT:    cnot z0.h, p0/m, z0.h
51; CHECK-NEXT:    ret
52  %ld = load <vscale x 8 x i16>, ptr %in
53  %cmp = icmp eq <vscale x 8 x i16> %ld, zeroinitializer
54  %ex = zext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
55  ret <vscale x 8 x i16> %ex
56}
57
58define <vscale x 2 x i32> @extload_icmp_nxv2i32(ptr %in) #0 {
59; CHECK-LABEL: extload_icmp_nxv2i32:
60; CHECK:       // %bb.0:
61; CHECK-NEXT:    ptrue p0.d
62; CHECK-NEXT:    ld1w { z0.d }, p0/z, [x0]
63; CHECK-NEXT:    cnot z0.d, p0/m, z0.d
64; CHECK-NEXT:    ret
65  %ld = load <vscale x 2 x i32>, ptr %in
66  %cmp = icmp eq <vscale x 2 x i32> %ld, zeroinitializer
67  %ex = zext <vscale x 2 x i1> %cmp to <vscale x 2 x i32>
68  ret <vscale x 2 x i32> %ex
69}
70
71define <vscale x 4 x i32> @extload_icmp_nxv4i32(ptr %in) #0 {
72; CHECK-LABEL: extload_icmp_nxv4i32:
73; CHECK:       // %bb.0:
74; CHECK-NEXT:    ptrue p0.s
75; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x0]
76; CHECK-NEXT:    cnot z0.s, p0/m, z0.s
77; CHECK-NEXT:    ret
78  %ld = load <vscale x 4 x i32>, ptr %in
79  %cmp = icmp eq <vscale x 4 x i32> %ld, zeroinitializer
80  %ex = zext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
81  ret <vscale x 4 x i32> %ex
82}
83
84define <vscale x 2 x i64> @extload_icmp_nxv2i64(ptr %in) #0 {
85; CHECK-LABEL: extload_icmp_nxv2i64:
86; CHECK:       // %bb.0:
87; CHECK-NEXT:    ptrue p0.d
88; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x0]
89; CHECK-NEXT:    cnot z0.d, p0/m, z0.d
90; CHECK-NEXT:    ret
91  %ld = load <vscale x 2 x i64>, ptr %in
92  %cmp = icmp eq <vscale x 2 x i64> %ld, zeroinitializer
93  %ex = zext <vscale x 2 x i1> %cmp to <vscale x 2 x i64>
94  ret <vscale x 2 x i64> %ex
95}
96
97
98
99attributes #0 = { "target-features"="+sve" }
100