xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-cntp-combine-i64.ll (revision c9eec3b085de0f7ce885cbdf9d35d9159ddd272a) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s | FileCheck %s
3
4target triple = "aarch64-unknown-linux-gnu"
5
6; INCP
7
8define i64 @cntp_add_all_active_nxv16i1(i64 %x, <vscale x 16 x i1> %pg) #0 {
9; CHECK-LABEL: cntp_add_all_active_nxv16i1:
10; CHECK:       // %bb.0:
11; CHECK-NEXT:    incp x0, p0.b
12; CHECK-NEXT:    ret
13  %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
14  %2 = tail call i64 @llvm.aarch64.sve.cntp.nxv16i1(<vscale x 16 x i1> %1, <vscale x 16 x i1> %pg)
15  %add = add i64 %2, %x
16  ret i64 %add
17}
18
19define i64 @cntp_add_all_active_nxv8i1(i64 %x, <vscale x 8 x i1> %pg) #0 {
20; CHECK-LABEL: cntp_add_all_active_nxv8i1:
21; CHECK:       // %bb.0:
22; CHECK-NEXT:    incp x0, p0.h
23; CHECK-NEXT:    ret
24  %1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
25  %2 = tail call i64 @llvm.aarch64.sve.cntp.nxv8i1(<vscale x 8 x i1> %1, <vscale x 8 x i1> %pg)
26  %add = add i64 %2, %x
27  ret i64 %add
28}
29
30define i64 @cntp_add_all_active_nxv4i1(i64 %x, <vscale x 4 x i1> %pg) #0 {
31; CHECK-LABEL: cntp_add_all_active_nxv4i1:
32; CHECK:       // %bb.0:
33; CHECK-NEXT:    incp x0, p0.s
34; CHECK-NEXT:    ret
35  %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
36  %2 = tail call i64 @llvm.aarch64.sve.cntp.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %pg)
37  %add = add i64 %2, %x
38  ret i64 %add
39}
40
41define i64 @cntp_add_all_active_nxv2i1(i64 %x, <vscale x 2 x i1> %pg) #0 {
42; CHECK-LABEL: cntp_add_all_active_nxv2i1:
43; CHECK:       // %bb.0:
44; CHECK-NEXT:    incp x0, p0.d
45; CHECK-NEXT:    ret
46  %1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
47  %2 = tail call i64 @llvm.aarch64.sve.cntp.nxv2i1(<vscale x 2 x i1> %1, <vscale x 2 x i1> %pg)
48  %add = add i64 %2, %x
49  ret i64 %add
50}
51
52define i64 @cntp_add_all_active_nxv8i1_via_cast(i64 %x, <vscale x 8 x i1> %pg) #0 {
53; CHECK-LABEL: cntp_add_all_active_nxv8i1_via_cast:
54; CHECK:       // %bb.0:
55; CHECK-NEXT:    incp x0, p0.h
56; CHECK-NEXT:    ret
57  %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
58  %2 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
59  %3 = tail call i64 @llvm.aarch64.sve.cntp.nxv8i1(<vscale x 8 x i1> %2, <vscale x 8 x i1> %pg)
60  %add = add i64 %3, %x
61  ret i64 %add
62}
63
64define i64 @cntp_add_all_active_nxv2i1_multiuse(i64 %x, <vscale x 2 x i1> %pg) #0 {
65; CHECK-LABEL: cntp_add_all_active_nxv2i1_multiuse:
66; CHECK:       // %bb.0:
67; CHECK-NEXT:    ptrue p1.d
68; CHECK-NEXT:    cntp x8, p1, p0.d
69; CHECK-NEXT:    add x9, x8, x0
70; CHECK-NEXT:    madd x0, x8, x0, x9
71; CHECK-NEXT:    ret
72  %1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
73  %2 = tail call i64 @llvm.aarch64.sve.cntp.nxv2i1(<vscale x 2 x i1> %1, <vscale x 2 x i1> %pg)
74  %add = add i64 %2, %x
75  %mul = mul i64 %2, %x
76  %res = add i64 %add, %mul
77  ret i64 %res
78}
79
80define i64 @cntp_add_same_active_nxv16i1(i64 %x, <vscale x 16 x i1> %pg) #0 {
81; CHECK-LABEL: cntp_add_same_active_nxv16i1:
82; CHECK:       // %bb.0:
83; CHECK-NEXT:    incp x0, p0.b
84; CHECK-NEXT:    ret
85  %1 = tail call i64 @llvm.aarch64.sve.cntp.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %pg)
86  %add = add i64 %1, %x
87  ret i64 %add
88}
89
90define i64 @cntp_add_same_active_nxv8i1(i64 %x, <vscale x 8 x i1> %pg) #0 {
91; CHECK-LABEL: cntp_add_same_active_nxv8i1:
92; CHECK:       // %bb.0:
93; CHECK-NEXT:    incp x0, p0.h
94; CHECK-NEXT:    ret
95  %1 = tail call i64 @llvm.aarch64.sve.cntp.nxv8i1(<vscale x 8 x i1> %pg, <vscale x 8 x i1> %pg)
96  %add = add i64 %1, %x
97  ret i64 %add
98}
99
100define i64 @cntp_add_same_active_nxv4i1(i64 %x, <vscale x 4 x i1> %pg) #0 {
101; CHECK-LABEL: cntp_add_same_active_nxv4i1:
102; CHECK:       // %bb.0:
103; CHECK-NEXT:    incp x0, p0.s
104; CHECK-NEXT:    ret
105  %1 = tail call i64 @llvm.aarch64.sve.cntp.nxv4i1(<vscale x 4 x i1> %pg, <vscale x 4 x i1> %pg)
106  %add = add i64 %1, %x
107  ret i64 %add
108}
109
110define i64 @cntp_add_same_active_nxv2i1(i64 %x, <vscale x 2 x i1> %pg) #0 {
111; CHECK-LABEL: cntp_add_same_active_nxv2i1:
112; CHECK:       // %bb.0:
113; CHECK-NEXT:    incp x0, p0.d
114; CHECK-NEXT:    ret
115  %1 = tail call i64 @llvm.aarch64.sve.cntp.nxv2i1(<vscale x 2 x i1> %pg, <vscale x 2 x i1> %pg)
116  %add = add i64 %1, %x
117  ret i64 %add
118}
119
120define i64 @cntp_add_same_active_nxv2i1_multiuse(i64 %x, <vscale x 2 x i1> %pg) #0 {
121; CHECK-LABEL: cntp_add_same_active_nxv2i1_multiuse:
122; CHECK:       // %bb.0:
123; CHECK-NEXT:    cntp x8, p0, p0.d
124; CHECK-NEXT:    add x9, x8, x0
125; CHECK-NEXT:    madd x0, x8, x0, x9
126; CHECK-NEXT:    ret
127  %1 = tail call i64 @llvm.aarch64.sve.cntp.nxv2i1(<vscale x 2 x i1> %pg, <vscale x 2 x i1> %pg)
128  %add = add i64 %1, %x
129  %mul = mul i64 %1, %x
130  %res = add i64 %add, %mul
131  ret i64 %res
132}
133
134; DECP
135
136define i64 @cntp_sub_all_active_nxv16i1(i64 %x, <vscale x 16 x i1> %pg) #0 {
137; CHECK-LABEL: cntp_sub_all_active_nxv16i1:
138; CHECK:       // %bb.0:
139; CHECK-NEXT:    decp x0, p0.b
140; CHECK-NEXT:    ret
141  %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
142  %2 = tail call i64 @llvm.aarch64.sve.cntp.nxv16i1(<vscale x 16 x i1> %1, <vscale x 16 x i1> %pg)
143  %sub = sub i64 %x, %2
144  ret i64 %sub
145}
146
147define i64 @cntp_sub_all_active_nxv8i1(i64 %x, <vscale x 8 x i1> %pg) #0 {
148; CHECK-LABEL: cntp_sub_all_active_nxv8i1:
149; CHECK:       // %bb.0:
150; CHECK-NEXT:    decp x0, p0.h
151; CHECK-NEXT:    ret
152  %1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
153  %2 = tail call i64 @llvm.aarch64.sve.cntp.nxv8i1(<vscale x 8 x i1> %1, <vscale x 8 x i1> %pg)
154  %sub = sub i64 %x, %2
155  ret i64 %sub
156}
157
158define i64 @cntp_sub_all_active_nxv4i1(i64 %x, <vscale x 4 x i1> %pg) #0 {
159; CHECK-LABEL: cntp_sub_all_active_nxv4i1:
160; CHECK:       // %bb.0:
161; CHECK-NEXT:    decp x0, p0.s
162; CHECK-NEXT:    ret
163  %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
164  %2 = tail call i64 @llvm.aarch64.sve.cntp.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %pg)
165  %sub = sub i64 %x, %2
166  ret i64 %sub
167}
168
169define i64 @cntp_sub_all_active_nxv2i1(i64 %x, <vscale x 2 x i1> %pg) #0 {
170; CHECK-LABEL: cntp_sub_all_active_nxv2i1:
171; CHECK:       // %bb.0:
172; CHECK-NEXT:    decp x0, p0.d
173; CHECK-NEXT:    ret
174  %1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
175  %2 = tail call i64 @llvm.aarch64.sve.cntp.nxv2i1(<vscale x 2 x i1> %1, <vscale x 2 x i1> %pg)
176  %sub = sub i64 %x, %2
177  ret i64 %sub
178}
179
180define i64 @cntp_sub_all_active_nxv8i1_via_cast(i64 %x, <vscale x 8 x i1> %pg) #0 {
181; CHECK-LABEL: cntp_sub_all_active_nxv8i1_via_cast:
182; CHECK:       // %bb.0:
183; CHECK-NEXT:    decp x0, p0.h
184; CHECK-NEXT:    ret
185  %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
186  %2 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
187  %3 = tail call i64 @llvm.aarch64.sve.cntp.nxv8i1(<vscale x 8 x i1> %2, <vscale x 8 x i1> %pg)
188  %sub = sub i64 %x, %3
189  ret i64 %sub
190}
191
192define i64 @cntp_sub_all_active_nxv2i1_multiuse(i64 %x, <vscale x 2 x i1> %pg) #0 {
193; CHECK-LABEL: cntp_sub_all_active_nxv2i1_multiuse:
194; CHECK:       // %bb.0:
195; CHECK-NEXT:    ptrue p1.d
196; CHECK-NEXT:    cntp x8, p1, p0.d
197; CHECK-NEXT:    sub x9, x8, x0
198; CHECK-NEXT:    madd x0, x8, x0, x9
199; CHECK-NEXT:    ret
200  %1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
201  %2 = tail call i64 @llvm.aarch64.sve.cntp.nxv2i1(<vscale x 2 x i1> %1, <vscale x 2 x i1> %pg)
202  %sub = sub i64 %2, %x
203  %mul = mul i64 %2, %x
204  %res = add i64 %sub, %mul
205  ret i64 %res
206}
207
208define i64 @cntp_sub_same_active_nxv16i1(i64 %x, <vscale x 16 x i1> %pg) #0 {
209; CHECK-LABEL: cntp_sub_same_active_nxv16i1:
210; CHECK:       // %bb.0:
211; CHECK-NEXT:    decp x0, p0.b
212; CHECK-NEXT:    ret
213  %1 = tail call i64 @llvm.aarch64.sve.cntp.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %pg)
214  %sub = sub i64 %x, %1
215  ret i64 %sub
216}
217
218define i64 @cntp_sub_same_active_nxv8i1(i64 %x, <vscale x 8 x i1> %pg) #0 {
219; CHECK-LABEL: cntp_sub_same_active_nxv8i1:
220; CHECK:       // %bb.0:
221; CHECK-NEXT:    decp x0, p0.h
222; CHECK-NEXT:    ret
223  %1 = tail call i64 @llvm.aarch64.sve.cntp.nxv8i1(<vscale x 8 x i1> %pg, <vscale x 8 x i1> %pg)
224  %sub = sub i64 %x, %1
225  ret i64 %sub
226}
227
228define i64 @cntp_sub_same_active_nxv4i1(i64 %x, <vscale x 4 x i1> %pg) #0 {
229; CHECK-LABEL: cntp_sub_same_active_nxv4i1:
230; CHECK:       // %bb.0:
231; CHECK-NEXT:    decp x0, p0.s
232; CHECK-NEXT:    ret
233  %1 = tail call i64 @llvm.aarch64.sve.cntp.nxv4i1(<vscale x 4 x i1> %pg, <vscale x 4 x i1> %pg)
234  %sub = sub i64 %x, %1
235  ret i64 %sub
236}
237
238define i64 @cntp_sub_same_active_nxv2i1(i64 %x, <vscale x 2 x i1> %pg) #0 {
239; CHECK-LABEL: cntp_sub_same_active_nxv2i1:
240; CHECK:       // %bb.0:
241; CHECK-NEXT:    decp x0, p0.d
242; CHECK-NEXT:    ret
243  %1 = tail call i64 @llvm.aarch64.sve.cntp.nxv2i1(<vscale x 2 x i1> %pg, <vscale x 2 x i1> %pg)
244  %sub = sub i64 %x, %1
245  ret i64 %sub
246}
247
248define i64 @cntp_sub_same_active_nxv2i1_multiuse(i64 %x, <vscale x 2 x i1> %pg) #0 {
249; CHECK-LABEL: cntp_sub_same_active_nxv2i1_multiuse:
250; CHECK:       // %bb.0:
251; CHECK-NEXT:    cntp x8, p0, p0.d
252; CHECK-NEXT:    sub x9, x8, x0
253; CHECK-NEXT:    madd x0, x8, x0, x9
254; CHECK-NEXT:    ret
255  %1 = tail call i64 @llvm.aarch64.sve.cntp.nxv2i1(<vscale x 2 x i1> %pg, <vscale x 2 x i1> %pg)
256  %sub = sub i64 %1, %x
257  %mul = mul i64 %1, %x
258  %res = add i64 %sub, %mul
259  ret i64 %res
260}
261
262declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>)
263declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>)
264declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>)
265
266declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32)
267declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32)
268declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32)
269declare <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32)
270
271declare i64 @llvm.aarch64.sve.cntp.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
272declare i64 @llvm.aarch64.sve.cntp.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>)
273declare i64 @llvm.aarch64.sve.cntp.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>)
274declare i64 @llvm.aarch64.sve.cntp.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>)
275
276attributes #0 = { "target-features"="+sve" }
277