xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-bit-counting-pred.ll (revision 672f673004663aeb15ece1af4b5b219994924167) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
3
4;
5; CTPOP
6;
7
8define <vscale x 16 x i1> @ctpop_nxv16i1(<vscale x 16 x i1> %a) {
9; CHECK-LABEL: ctpop_nxv16i1:
10; CHECK:       // %bb.0:
11; CHECK-NEXT:    ret
12  %res = call <vscale x 16 x i1> @llvm.ctpop.nxv16i1(<vscale x 16 x i1> %a)
13  ret <vscale x 16 x i1> %res
14}
15
16define <vscale x 8 x i1> @ctpop_nxv8i1(<vscale x 8 x i1> %a) {
17; CHECK-LABEL: ctpop_nxv8i1:
18; CHECK:       // %bb.0:
19; CHECK-NEXT:    ret
20  %res = call <vscale x 8 x i1> @llvm.ctpop.nxv8i1(<vscale x 8 x i1> %a)
21  ret <vscale x 8 x i1> %res
22}
23
24define <vscale x 4 x i1> @ctpop_nxv4i1(<vscale x 4 x i1> %a) {
25; CHECK-LABEL: ctpop_nxv4i1:
26; CHECK:       // %bb.0:
27; CHECK-NEXT:    ret
28  %res = call <vscale x 4 x i1> @llvm.ctpop.nxv4i1(<vscale x 4 x i1> %a)
29  ret <vscale x 4 x i1> %res
30}
31
32define <vscale x 2 x i1> @ctpop_nxv2i1(<vscale x 2 x i1> %a) {
33; CHECK-LABEL: ctpop_nxv2i1:
34; CHECK:       // %bb.0:
35; CHECK-NEXT:    ret
36  %res = call <vscale x 2 x i1> @llvm.ctpop.nxv2i1(<vscale x 2 x i1> %a)
37  ret <vscale x 2 x i1> %res
38}
39
40; CTLZ
41
42define <vscale x 16 x i1> @ctlz_nxv16i1(<vscale x 16 x i1> %a) {
43; CHECK-LABEL: ctlz_nxv16i1:
44; CHECK:       // %bb.0:
45; CHECK-NEXT:    ptrue p1.b
46; CHECK-NEXT:    not p0.b, p1/z, p0.b
47; CHECK-NEXT:    ret
48  %res = call <vscale x 16 x i1> @llvm.ctlz.nxv16i1(<vscale x 16 x i1> %a)
49  ret <vscale x 16 x i1> %res
50}
51
52define <vscale x 8 x i1> @ctlz_nxv8i1(<vscale x 8 x i1> %a) {
53; CHECK-LABEL: ctlz_nxv8i1:
54; CHECK:       // %bb.0:
55; CHECK-NEXT:    ptrue p1.h
56; CHECK-NEXT:    not p0.b, p1/z, p0.b
57; CHECK-NEXT:    ret
58  %res = call <vscale x 8 x i1> @llvm.ctlz.nxv8i1(<vscale x 8 x i1> %a)
59  ret <vscale x 8 x i1> %res
60}
61
62define <vscale x 4 x i1> @ctlz_nxv4i1(<vscale x 4 x i1> %a) {
63; CHECK-LABEL: ctlz_nxv4i1:
64; CHECK:       // %bb.0:
65; CHECK-NEXT:    ptrue p1.s
66; CHECK-NEXT:    not p0.b, p1/z, p0.b
67; CHECK-NEXT:    ret
68  %res = call <vscale x 4 x i1> @llvm.ctlz.nxv4i1(<vscale x 4 x i1> %a)
69  ret <vscale x 4 x i1> %res
70}
71
72define <vscale x 2 x i1> @ctlz_nxv2i1(<vscale x 2 x i1> %a) {
73; CHECK-LABEL: ctlz_nxv2i1:
74; CHECK:       // %bb.0:
75; CHECK-NEXT:    ptrue p1.d
76; CHECK-NEXT:    not p0.b, p1/z, p0.b
77; CHECK-NEXT:    ret
78  %res = call <vscale x 2 x i1> @llvm.ctlz.nxv2i1(<vscale x 2 x i1> %a)
79  ret <vscale x 2 x i1> %res
80}
81
82; CTTZ
83
84define <vscale x 16 x i1> @cttz_nxv16i1(<vscale x 16 x i1> %a) {
85; CHECK-LABEL: cttz_nxv16i1:
86; CHECK:       // %bb.0:
87; CHECK-NEXT:    ptrue p1.b
88; CHECK-NEXT:    not p0.b, p1/z, p0.b
89; CHECK-NEXT:    ret
90  %res = call <vscale x 16 x i1> @llvm.cttz.nxv16i1(<vscale x 16 x i1> %a)
91  ret <vscale x 16 x i1> %res
92}
93
94define <vscale x 8 x i1> @cttz_nxv8i1(<vscale x 8 x i1> %a) {
95; CHECK-LABEL: cttz_nxv8i1:
96; CHECK:       // %bb.0:
97; CHECK-NEXT:    ptrue p1.h
98; CHECK-NEXT:    not p0.b, p1/z, p0.b
99; CHECK-NEXT:    ret
100  %res = call <vscale x 8 x i1> @llvm.cttz.nxv8i1(<vscale x 8 x i1> %a)
101  ret <vscale x 8 x i1> %res
102}
103
104define <vscale x 4 x i1> @cttz_nxv4i1(<vscale x 4 x i1> %a) {
105; CHECK-LABEL: cttz_nxv4i1:
106; CHECK:       // %bb.0:
107; CHECK-NEXT:    ptrue p1.s
108; CHECK-NEXT:    not p0.b, p1/z, p0.b
109; CHECK-NEXT:    ret
110  %res = call <vscale x 4 x i1> @llvm.cttz.nxv4i1(<vscale x 4 x i1> %a)
111  ret <vscale x 4 x i1> %res
112}
113
114define <vscale x 2 x i1> @cttz_nxv2i1(<vscale x 2 x i1> %a) {
115; CHECK-LABEL: cttz_nxv2i1:
116; CHECK:       // %bb.0:
117; CHECK-NEXT:    ptrue p1.d
118; CHECK-NEXT:    not p0.b, p1/z, p0.b
119; CHECK-NEXT:    ret
120  %res = call <vscale x 2 x i1> @llvm.cttz.nxv2i1(<vscale x 2 x i1> %a)
121  ret <vscale x 2 x i1> %res
122}
123
124declare <vscale x 16 x i1> @llvm.ctpop.nxv16i1(<vscale x 16 x i1>)
125declare <vscale x 8 x i1> @llvm.ctpop.nxv8i1(<vscale x 8 x i1>)
126declare <vscale x 4 x i1> @llvm.ctpop.nxv4i1(<vscale x 4 x i1>)
127declare <vscale x 2 x i1> @llvm.ctpop.nxv2i1(<vscale x 2 x i1>)
128
129declare <vscale x 16 x i1> @llvm.ctlz.nxv16i1(<vscale x 16 x i1>)
130declare <vscale x 8 x i1> @llvm.ctlz.nxv8i1(<vscale x 8 x i1>)
131declare <vscale x 4 x i1> @llvm.ctlz.nxv4i1(<vscale x 4 x i1>)
132declare <vscale x 2 x i1> @llvm.ctlz.nxv2i1(<vscale x 2 x i1>)
133
134declare <vscale x 16 x i1> @llvm.cttz.nxv16i1(<vscale x 16 x i1>)
135declare <vscale x 8 x i1> @llvm.cttz.nxv8i1(<vscale x 8 x i1>)
136declare <vscale x 4 x i1> @llvm.cttz.nxv4i1(<vscale x 4 x i1>)
137declare <vscale x 2 x i1> @llvm.cttz.nxv2i1(<vscale x 2 x i1>)
138