xref: /llvm-project/llvm/test/CodeGen/AArch64/sub1.ll (revision d0eec5f7e7874ecfdface473cd4718ac5e6e629e) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
3
4define i64 @sub1_disguised_constant(i64 %x) {
5; CHECK-LABEL: sub1_disguised_constant:
6; CHECK:       // %bb.0:
7; CHECK-NEXT:    sub w8, w0, #1
8; CHECK-NEXT:    and w8, w0, w8
9; CHECK-NEXT:    and x0, x8, #0xffff
10; CHECK-NEXT:    ret
11  %a1 = and i64 %x, 65535
12  %a2 = add i64 %x, 65535
13  %r = and i64 %a1, %a2
14  ret i64 %r
15}
16
17define i8 @masked_sub_i8(i8 %x) {
18; CHECK-LABEL: masked_sub_i8:
19; CHECK:       // %bb.0:
20; CHECK-NEXT:    mov w8, #5
21; CHECK-NEXT:    and w8, w0, w8
22; CHECK-NEXT:    eor w0, w8, #0x7
23; CHECK-NEXT:    ret
24  %a = and i8 %x, 5
25  %m = sub i8 7, %a
26  ret i8 %m
27}
28
29; Borrow from the MSB is ok.
30
31define i8 @masked_sub_high_bit_mask_i8(i8 %x) {
32; CHECK-LABEL: masked_sub_high_bit_mask_i8:
33; CHECK:       // %bb.0:
34; CHECK-NEXT:    mov w8, #-96
35; CHECK-NEXT:    and w8, w0, w8
36; CHECK-NEXT:    eor w0, w8, #0x3c
37; CHECK-NEXT:    ret
38  %maskx = and i8 %x, 160 ; 0b10100000
39  %s = sub i8 60, %maskx  ; 0b00111100
40  ret i8 %s
41}
42
43define i8 @not_masked_sub_i8(i8 %x) {
44; CHECK-LABEL: not_masked_sub_i8:
45; CHECK:       // %bb.0:
46; CHECK-NEXT:    mov w8, #7
47; CHECK-NEXT:    and w9, w0, #0x8
48; CHECK-NEXT:    sub w0, w8, w9
49; CHECK-NEXT:    ret
50  %a = and i8 %x, 8
51  %m = sub i8 7, %a
52  ret i8 %m
53}
54
55define i32 @masked_sub_i32(i32 %x) {
56; CHECK-LABEL: masked_sub_i32:
57; CHECK:       // %bb.0:
58; CHECK-NEXT:    mov w8, #9
59; CHECK-NEXT:    and w8, w0, w8
60; CHECK-NEXT:    eor w0, w8, #0x1f
61; CHECK-NEXT:    ret
62  %a = and i32 %x, 9
63  %m = sub i32 31, %a
64  ret i32 %m
65}
66
67define <4 x i32> @masked_sub_v4i32(<4 x i32> %x) {
68; CHECK-LABEL: masked_sub_v4i32:
69; CHECK:       // %bb.0:
70; CHECK-NEXT:    movi v1.4s, #42
71; CHECK-NEXT:    movi v2.4s, #1, msl #8
72; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
73; CHECK-NEXT:    eor v0.16b, v0.16b, v2.16b
74; CHECK-NEXT:    ret
75  %a = and <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42>
76  %m = sub <4 x i32> <i32 511, i32 511, i32 511, i32 511>, %a
77  ret <4 x i32>  %m
78}
79