1; RUN: llc < %s -mtriple=aarch64-apple-darwin | FileCheck %s 2 3target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" 4 5; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps 6; CHECK-NEXT: __LLVM_StackMaps: 7; Header 8; CHECK-NEXT: .byte 3 9; CHECK-NEXT: .byte 0 10; CHECK-NEXT: .short 0 11; Num Functions 12; CHECK-NEXT: .long 1 13; Num LargeConstants 14; CHECK-NEXT: .long 0 15; Num Callsites 16; CHECK-NEXT: .long 1 17 18; Functions and stack size 19; CHECK-NEXT: .quad _stackmap_liveness 20; CHECK-NEXT: .quad 16 21 22; Test that the return register is recognized as an live-out. 23define i64 @stackmap_liveness(i1 %c) { 24; CHECK-LABEL: .long L{{.*}}-_stackmap_liveness 25; CHECK-NEXT: .short 0 26; CHECK-NEXT: .short 0 27; Padding 28; CHECK-NEXT: .p2align 3 29; CHECK-NEXT: .short 0 30; Num LiveOut Entries: 20 31; CHECK-NEXT: .short 20 32; LiveOut Entry 1: X0 33; CHECK-NEXT: .short 0 34; CHECK-NEXT: .byte 0 35; CHECK-NEXT: .byte 8 36; LiveOut Entry 2: 37; CHECK-NEXT: .short 19 38; CHECK-NEXT: .byte 0 39; CHECK-NEXT: .byte 8 40; LiveOut Entry 3: 41; CHECK-NEXT: .short 20 42; CHECK-NEXT: .byte 0 43; CHECK-NEXT: .byte 8 44; LiveOut Entry 4: 45; CHECK-NEXT: .short 21 46; CHECK-NEXT: .byte 0 47; CHECK-NEXT: .byte 8 48; LiveOut Entry 5: 49; CHECK-NEXT: .short 22 50; CHECK-NEXT: .byte 0 51; CHECK-NEXT: .byte 8 52; LiveOut Entry 6: 53; CHECK-NEXT: .short 23 54; CHECK-NEXT: .byte 0 55; CHECK-NEXT: .byte 8 56; LiveOut Entry 7: 57; CHECK-NEXT: .short 24 58; CHECK-NEXT: .byte 0 59; CHECK-NEXT: .byte 8 60; LiveOut Entry 8: 61; CHECK-NEXT: .short 25 62; CHECK-NEXT: .byte 0 63; CHECK-NEXT: .byte 8 64; LiveOut Entry 9: 65; CHECK-NEXT: .short 26 66; CHECK-NEXT: .byte 0 67; CHECK-NEXT: .byte 8 68; LiveOut Entry 10: 69; CHECK-NEXT: .short 27 70; CHECK-NEXT: .byte 0 71; CHECK-NEXT: .byte 8 72; LiveOut Entry 11: 73; CHECK-NEXT: .short 28 74; CHECK-NEXT: .byte 0 75; CHECK-NEXT: .byte 8 76; LiveOut Entry 12: SP 77; CHECK-NEXT: .short 31 78; CHECK-NEXT: .byte 0 79; CHECK-NEXT: .byte 8 80; LiveOut Entry 13: 81; CHECK-NEXT: .short 72 82; CHECK-NEXT: .byte 0 83; CHECK-NEXT: .byte 8 84; LiveOut Entry 14: 85; CHECK-NEXT: .short 73 86; CHECK-NEXT: .byte 0 87; CHECK-NEXT: .byte 8 88; LiveOut Entry 15: 89; CHECK-NEXT: .short 74 90; CHECK-NEXT: .byte 0 91; CHECK-NEXT: .byte 8 92; LiveOut Entry 16: 93; CHECK-NEXT: .short 75 94; CHECK-NEXT: .byte 0 95; CHECK-NEXT: .byte 8 96; LiveOut Entry 17: 97; CHECK-NEXT: .short 76 98; CHECK-NEXT: .byte 0 99; CHECK-NEXT: .byte 8 100; LiveOut Entry 18: 101; CHECK-NEXT: .short 77 102; CHECK-NEXT: .byte 0 103; CHECK-NEXT: .byte 8 104; LiveOut Entry 19: 105; CHECK-NEXT: .short 78 106; CHECK-NEXT: .byte 0 107; CHECK-NEXT: .byte 8 108; LiveOut Entry 20: 109; CHECK-NEXT: .short 79 110; CHECK-NEXT: .byte 0 111; CHECK-NEXT: .byte 8 112; Align 113; CHECK-NEXT: .p2align 3 114 %1 = select i1 %c, i64 1, i64 2 115 call anyregcc void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 1, i32 32, ptr null, i32 0) 116 ret i64 %1 117} 118 119declare void @llvm.experimental.patchpoint.void(i64, i32, ptr, i32, ...) 120