xref: /llvm-project/llvm/test/CodeGen/AArch64/srem-vec-crash.ll (revision 7c9b5228da94a44f5e3948814d896de537d162bb)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2; RUN: llc -mtriple=aarch64-unknown-unknown < %s | FileCheck %s
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4define i32 @pr84830(i1 %arg) {
5; CHECK-LABEL: pr84830:
6; CHECK:       // %bb.0: // %bb
7; CHECK-NEXT:    mov w0, #1 // =0x1
8; CHECK-NEXT:    ret
9bb:
10  %new0 = srem i1 %arg, true
11  %last = zext i1 %new0 to i32
12  %i = icmp ne i32 %last, 0
13  %i1 = select i1 %i, i32 0, i32 1
14  ret i32 %i1
15}
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