xref: /llvm-project/llvm/test/CodeGen/AArch64/srem-seteq-vec-nonsplat.ll (revision 6c84709eff20460a75fb58d2face54432c133967) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
3
4; Odd+Even divisors
5define <4 x i32> @test_srem_odd_even(<4 x i32> %X) nounwind {
6; CHECK-LABEL: test_srem_odd_even:
7; CHECK:       // %bb.0:
8; CHECK-NEXT:    adrp x8, .LCPI0_0
9; CHECK-NEXT:    adrp x9, .LCPI0_1
10; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI0_0]
11; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI0_1]
12; CHECK-NEXT:    adrp x8, .LCPI0_2
13; CHECK-NEXT:    adrp x9, .LCPI0_3
14; CHECK-NEXT:    mla v2.4s, v0.4s, v1.4s
15; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI0_2]
16; CHECK-NEXT:    ldr q1, [x9, :lo12:.LCPI0_3]
17; CHECK-NEXT:    adrp x8, .LCPI0_4
18; CHECK-NEXT:    ushl v0.4s, v2.4s, v0.4s
19; CHECK-NEXT:    ushl v1.4s, v2.4s, v1.4s
20; CHECK-NEXT:    movi v2.4s, #1
21; CHECK-NEXT:    orr v0.16b, v1.16b, v0.16b
22; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI0_4]
23; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
24; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
25; CHECK-NEXT:    ret
26  %srem = srem <4 x i32> %X, <i32 5, i32 14, i32 25, i32 100>
27  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
28  %ret = zext <4 x i1> %cmp to <4 x i32>
29  ret <4 x i32> %ret
30}
31
32;==============================================================================;
33
34; One all-ones divisor in odd divisor
35define <4 x i32> @test_srem_odd_allones_eq(<4 x i32> %X) nounwind {
36; CHECK-LABEL: test_srem_odd_allones_eq:
37; CHECK:       // %bb.0:
38; CHECK-NEXT:    movi v1.16b, #153
39; CHECK-NEXT:    mov w8, #52429 // =0xcccd
40; CHECK-NEXT:    movk w8, #52428, lsl #16
41; CHECK-NEXT:    dup v2.4s, w8
42; CHECK-NEXT:    adrp x8, .LCPI1_0
43; CHECK-NEXT:    fneg v1.4s, v1.4s
44; CHECK-NEXT:    mla v1.4s, v0.4s, v2.4s
45; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI1_0]
46; CHECK-NEXT:    movi v2.4s, #1
47; CHECK-NEXT:    cmhs v0.4s, v0.4s, v1.4s
48; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
49; CHECK-NEXT:    ret
50  %srem = srem <4 x i32> %X, <i32 5, i32 5, i32 4294967295, i32 5>
51  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
52  %ret = zext <4 x i1> %cmp to <4 x i32>
53  ret <4 x i32> %ret
54}
55define <4 x i32> @test_srem_odd_allones_ne(<4 x i32> %X) nounwind {
56; CHECK-LABEL: test_srem_odd_allones_ne:
57; CHECK:       // %bb.0:
58; CHECK-NEXT:    movi v1.16b, #153
59; CHECK-NEXT:    mov w8, #52429 // =0xcccd
60; CHECK-NEXT:    movk w8, #52428, lsl #16
61; CHECK-NEXT:    dup v2.4s, w8
62; CHECK-NEXT:    adrp x8, .LCPI2_0
63; CHECK-NEXT:    fneg v1.4s, v1.4s
64; CHECK-NEXT:    mla v1.4s, v0.4s, v2.4s
65; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI2_0]
66; CHECK-NEXT:    movi v2.4s, #1
67; CHECK-NEXT:    cmhi v0.4s, v1.4s, v0.4s
68; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
69; CHECK-NEXT:    ret
70  %srem = srem <4 x i32> %X, <i32 5, i32 5, i32 4294967295, i32 5>
71  %cmp = icmp ne <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
72  %ret = zext <4 x i1> %cmp to <4 x i32>
73  ret <4 x i32> %ret
74}
75
76; One all-ones divisor in even divisor
77define <4 x i32> @test_srem_even_allones_eq(<4 x i32> %X) nounwind {
78; CHECK-LABEL: test_srem_even_allones_eq:
79; CHECK:       // %bb.0:
80; CHECK-NEXT:    mov w8, #28087 // =0x6db7
81; CHECK-NEXT:    mov w9, #9362 // =0x2492
82; CHECK-NEXT:    movk w8, #46811, lsl #16
83; CHECK-NEXT:    movk w9, #4681, lsl #16
84; CHECK-NEXT:    dup v1.4s, w8
85; CHECK-NEXT:    dup v2.4s, w9
86; CHECK-NEXT:    adrp x8, .LCPI3_0
87; CHECK-NEXT:    mla v2.4s, v0.4s, v1.4s
88; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI3_0]
89; CHECK-NEXT:    shl v0.4s, v2.4s, #31
90; CHECK-NEXT:    usra v0.4s, v2.4s, #1
91; CHECK-NEXT:    movi v2.4s, #1
92; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
93; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
94; CHECK-NEXT:    ret
95  %srem = srem <4 x i32> %X, <i32 14, i32 14, i32 4294967295, i32 14>
96  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
97  %ret = zext <4 x i1> %cmp to <4 x i32>
98  ret <4 x i32> %ret
99}
100define <4 x i32> @test_srem_even_allones_ne(<4 x i32> %X) nounwind {
101; CHECK-LABEL: test_srem_even_allones_ne:
102; CHECK:       // %bb.0:
103; CHECK-NEXT:    mov w8, #28087 // =0x6db7
104; CHECK-NEXT:    mov w9, #9362 // =0x2492
105; CHECK-NEXT:    movk w8, #46811, lsl #16
106; CHECK-NEXT:    movk w9, #4681, lsl #16
107; CHECK-NEXT:    dup v1.4s, w8
108; CHECK-NEXT:    dup v2.4s, w9
109; CHECK-NEXT:    adrp x8, .LCPI4_0
110; CHECK-NEXT:    mla v2.4s, v0.4s, v1.4s
111; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI4_0]
112; CHECK-NEXT:    shl v0.4s, v2.4s, #31
113; CHECK-NEXT:    usra v0.4s, v2.4s, #1
114; CHECK-NEXT:    movi v2.4s, #1
115; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
116; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
117; CHECK-NEXT:    ret
118  %srem = srem <4 x i32> %X, <i32 14, i32 14, i32 4294967295, i32 14>
119  %cmp = icmp ne <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
120  %ret = zext <4 x i1> %cmp to <4 x i32>
121  ret <4 x i32> %ret
122}
123
124; One all-ones divisor in odd+even divisor
125define <4 x i32> @test_srem_odd_even_allones_eq(<4 x i32> %X) nounwind {
126; CHECK-LABEL: test_srem_odd_even_allones_eq:
127; CHECK:       // %bb.0:
128; CHECK-NEXT:    adrp x8, .LCPI5_0
129; CHECK-NEXT:    adrp x9, .LCPI5_1
130; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI5_0]
131; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI5_1]
132; CHECK-NEXT:    adrp x8, .LCPI5_2
133; CHECK-NEXT:    adrp x9, .LCPI5_3
134; CHECK-NEXT:    mla v2.4s, v0.4s, v1.4s
135; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI5_2]
136; CHECK-NEXT:    ldr q1, [x9, :lo12:.LCPI5_3]
137; CHECK-NEXT:    adrp x8, .LCPI5_4
138; CHECK-NEXT:    ushl v0.4s, v2.4s, v0.4s
139; CHECK-NEXT:    ushl v1.4s, v2.4s, v1.4s
140; CHECK-NEXT:    movi v2.4s, #1
141; CHECK-NEXT:    orr v0.16b, v1.16b, v0.16b
142; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI5_4]
143; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
144; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
145; CHECK-NEXT:    ret
146  %srem = srem <4 x i32> %X, <i32 5, i32 14, i32 4294967295, i32 100>
147  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
148  %ret = zext <4 x i1> %cmp to <4 x i32>
149  ret <4 x i32> %ret
150}
151define <4 x i32> @test_srem_odd_even_allones_ne(<4 x i32> %X) nounwind {
152; CHECK-LABEL: test_srem_odd_even_allones_ne:
153; CHECK:       // %bb.0:
154; CHECK-NEXT:    adrp x8, .LCPI6_0
155; CHECK-NEXT:    adrp x9, .LCPI6_1
156; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI6_0]
157; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI6_1]
158; CHECK-NEXT:    adrp x8, .LCPI6_2
159; CHECK-NEXT:    adrp x9, .LCPI6_3
160; CHECK-NEXT:    mla v2.4s, v0.4s, v1.4s
161; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI6_2]
162; CHECK-NEXT:    ldr q1, [x9, :lo12:.LCPI6_3]
163; CHECK-NEXT:    adrp x8, .LCPI6_4
164; CHECK-NEXT:    ushl v0.4s, v2.4s, v0.4s
165; CHECK-NEXT:    ushl v1.4s, v2.4s, v1.4s
166; CHECK-NEXT:    movi v2.4s, #1
167; CHECK-NEXT:    orr v0.16b, v1.16b, v0.16b
168; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI6_4]
169; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
170; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
171; CHECK-NEXT:    ret
172  %srem = srem <4 x i32> %X, <i32 5, i32 14, i32 4294967295, i32 100>
173  %cmp = icmp ne <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
174  %ret = zext <4 x i1> %cmp to <4 x i32>
175  ret <4 x i32> %ret
176}
177
178;------------------------------------------------------------------------------;
179
180; One power-of-two divisor in odd divisor
181define <4 x i32> @test_srem_odd_poweroftwo(<4 x i32> %X) nounwind {
182; CHECK-LABEL: test_srem_odd_poweroftwo:
183; CHECK:       // %bb.0:
184; CHECK-NEXT:    adrp x8, .LCPI7_0
185; CHECK-NEXT:    adrp x9, .LCPI7_1
186; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI7_0]
187; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI7_1]
188; CHECK-NEXT:    adrp x8, .LCPI7_2
189; CHECK-NEXT:    adrp x9, .LCPI7_3
190; CHECK-NEXT:    mla v2.4s, v0.4s, v1.4s
191; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI7_2]
192; CHECK-NEXT:    ldr q1, [x9, :lo12:.LCPI7_3]
193; CHECK-NEXT:    adrp x8, .LCPI7_4
194; CHECK-NEXT:    ushl v0.4s, v2.4s, v0.4s
195; CHECK-NEXT:    ushl v1.4s, v2.4s, v1.4s
196; CHECK-NEXT:    movi v2.4s, #1
197; CHECK-NEXT:    orr v0.16b, v1.16b, v0.16b
198; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI7_4]
199; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
200; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
201; CHECK-NEXT:    ret
202  %srem = srem <4 x i32> %X, <i32 5, i32 5, i32 16, i32 5>
203  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
204  %ret = zext <4 x i1> %cmp to <4 x i32>
205  ret <4 x i32> %ret
206}
207
208; One power-of-two divisor in even divisor
209define <4 x i32> @test_srem_even_poweroftwo(<4 x i32> %X) nounwind {
210; CHECK-LABEL: test_srem_even_poweroftwo:
211; CHECK:       // %bb.0:
212; CHECK-NEXT:    adrp x8, .LCPI8_0
213; CHECK-NEXT:    adrp x9, .LCPI8_1
214; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI8_0]
215; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI8_1]
216; CHECK-NEXT:    adrp x8, .LCPI8_2
217; CHECK-NEXT:    adrp x9, .LCPI8_3
218; CHECK-NEXT:    mla v2.4s, v0.4s, v1.4s
219; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI8_2]
220; CHECK-NEXT:    ldr q1, [x9, :lo12:.LCPI8_3]
221; CHECK-NEXT:    adrp x8, .LCPI8_4
222; CHECK-NEXT:    ushl v0.4s, v2.4s, v0.4s
223; CHECK-NEXT:    ushl v1.4s, v2.4s, v1.4s
224; CHECK-NEXT:    movi v2.4s, #1
225; CHECK-NEXT:    orr v0.16b, v1.16b, v0.16b
226; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI8_4]
227; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
228; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
229; CHECK-NEXT:    ret
230  %srem = srem <4 x i32> %X, <i32 14, i32 14, i32 16, i32 14>
231  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
232  %ret = zext <4 x i1> %cmp to <4 x i32>
233  ret <4 x i32> %ret
234}
235
236; One power-of-two divisor in odd+even divisor
237define <4 x i32> @test_srem_odd_even_poweroftwo(<4 x i32> %X) nounwind {
238; CHECK-LABEL: test_srem_odd_even_poweroftwo:
239; CHECK:       // %bb.0:
240; CHECK-NEXT:    adrp x8, .LCPI9_0
241; CHECK-NEXT:    adrp x9, .LCPI9_1
242; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI9_0]
243; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI9_1]
244; CHECK-NEXT:    adrp x8, .LCPI9_2
245; CHECK-NEXT:    adrp x9, .LCPI9_3
246; CHECK-NEXT:    mla v2.4s, v0.4s, v1.4s
247; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI9_2]
248; CHECK-NEXT:    ldr q1, [x9, :lo12:.LCPI9_3]
249; CHECK-NEXT:    adrp x8, .LCPI9_4
250; CHECK-NEXT:    ushl v0.4s, v2.4s, v0.4s
251; CHECK-NEXT:    ushl v1.4s, v2.4s, v1.4s
252; CHECK-NEXT:    movi v2.4s, #1
253; CHECK-NEXT:    orr v0.16b, v1.16b, v0.16b
254; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI9_4]
255; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
256; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
257; CHECK-NEXT:    ret
258  %srem = srem <4 x i32> %X, <i32 5, i32 14, i32 16, i32 100>
259  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
260  %ret = zext <4 x i1> %cmp to <4 x i32>
261  ret <4 x i32> %ret
262}
263
264;------------------------------------------------------------------------------;
265
266; One one divisor in odd divisor
267define <4 x i32> @test_srem_odd_one(<4 x i32> %X) nounwind {
268; CHECK-LABEL: test_srem_odd_one:
269; CHECK:       // %bb.0:
270; CHECK-NEXT:    movi v1.16b, #153
271; CHECK-NEXT:    mov w8, #52429 // =0xcccd
272; CHECK-NEXT:    movk w8, #52428, lsl #16
273; CHECK-NEXT:    dup v2.4s, w8
274; CHECK-NEXT:    adrp x8, .LCPI10_0
275; CHECK-NEXT:    fneg v1.4s, v1.4s
276; CHECK-NEXT:    mla v1.4s, v0.4s, v2.4s
277; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI10_0]
278; CHECK-NEXT:    movi v2.4s, #1
279; CHECK-NEXT:    cmhs v0.4s, v0.4s, v1.4s
280; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
281; CHECK-NEXT:    ret
282  %srem = srem <4 x i32> %X, <i32 5, i32 5, i32 1, i32 5>
283  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
284  %ret = zext <4 x i1> %cmp to <4 x i32>
285  ret <4 x i32> %ret
286}
287
288; One one divisor in even divisor
289define <4 x i32> @test_srem_even_one(<4 x i32> %X) nounwind {
290; CHECK-LABEL: test_srem_even_one:
291; CHECK:       // %bb.0:
292; CHECK-NEXT:    mov w8, #28087 // =0x6db7
293; CHECK-NEXT:    mov w9, #9362 // =0x2492
294; CHECK-NEXT:    movk w8, #46811, lsl #16
295; CHECK-NEXT:    movk w9, #4681, lsl #16
296; CHECK-NEXT:    dup v1.4s, w8
297; CHECK-NEXT:    dup v2.4s, w9
298; CHECK-NEXT:    adrp x8, .LCPI11_0
299; CHECK-NEXT:    mla v2.4s, v0.4s, v1.4s
300; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI11_0]
301; CHECK-NEXT:    shl v0.4s, v2.4s, #31
302; CHECK-NEXT:    usra v0.4s, v2.4s, #1
303; CHECK-NEXT:    movi v2.4s, #1
304; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
305; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
306; CHECK-NEXT:    ret
307  %srem = srem <4 x i32> %X, <i32 14, i32 14, i32 1, i32 14>
308  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
309  %ret = zext <4 x i1> %cmp to <4 x i32>
310  ret <4 x i32> %ret
311}
312
313; One one divisor in odd+even divisor
314define <4 x i32> @test_srem_odd_even_one(<4 x i32> %X) nounwind {
315; CHECK-LABEL: test_srem_odd_even_one:
316; CHECK:       // %bb.0:
317; CHECK-NEXT:    adrp x8, .LCPI12_0
318; CHECK-NEXT:    adrp x9, .LCPI12_1
319; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI12_0]
320; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI12_1]
321; CHECK-NEXT:    adrp x8, .LCPI12_2
322; CHECK-NEXT:    adrp x9, .LCPI12_3
323; CHECK-NEXT:    mla v2.4s, v0.4s, v1.4s
324; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI12_2]
325; CHECK-NEXT:    ldr q1, [x9, :lo12:.LCPI12_3]
326; CHECK-NEXT:    adrp x8, .LCPI12_4
327; CHECK-NEXT:    ushl v0.4s, v2.4s, v0.4s
328; CHECK-NEXT:    ushl v1.4s, v2.4s, v1.4s
329; CHECK-NEXT:    movi v2.4s, #1
330; CHECK-NEXT:    orr v0.16b, v1.16b, v0.16b
331; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI12_4]
332; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
333; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
334; CHECK-NEXT:    ret
335  %srem = srem <4 x i32> %X, <i32 5, i32 14, i32 1, i32 100>
336  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
337  %ret = zext <4 x i1> %cmp to <4 x i32>
338  ret <4 x i32> %ret
339}
340
341;------------------------------------------------------------------------------;
342
343; One INT_MIN divisor in odd divisor
344define <4 x i32> @test_srem_odd_INT_MIN(<4 x i32> %X) nounwind {
345; CHECK-LABEL: test_srem_odd_INT_MIN:
346; CHECK:       // %bb.0:
347; CHECK-NEXT:    adrp x8, .LCPI13_0
348; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI13_0]
349; CHECK-NEXT:    adrp x8, .LCPI13_1
350; CHECK-NEXT:    smull2 v2.2d, v0.4s, v1.4s
351; CHECK-NEXT:    smull v1.2d, v0.2s, v1.2s
352; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v2.4s
353; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI13_1]
354; CHECK-NEXT:    adrp x8, .LCPI13_2
355; CHECK-NEXT:    mla v1.4s, v0.4s, v2.4s
356; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI13_2]
357; CHECK-NEXT:    adrp x8, .LCPI13_3
358; CHECK-NEXT:    sshl v2.4s, v1.4s, v2.4s
359; CHECK-NEXT:    usra v2.4s, v1.4s, #31
360; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI13_3]
361; CHECK-NEXT:    mls v0.4s, v2.4s, v1.4s
362; CHECK-NEXT:    movi v1.4s, #1
363; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
364; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
365; CHECK-NEXT:    ret
366  %srem = srem <4 x i32> %X, <i32 5, i32 5, i32 2147483648, i32 5>
367  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
368  %ret = zext <4 x i1> %cmp to <4 x i32>
369  ret <4 x i32> %ret
370}
371
372; One INT_MIN divisor in even divisor
373define <4 x i32> @test_srem_even_INT_MIN(<4 x i32> %X) nounwind {
374; CHECK-LABEL: test_srem_even_INT_MIN:
375; CHECK:       // %bb.0:
376; CHECK-NEXT:    adrp x8, .LCPI14_0
377; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI14_0]
378; CHECK-NEXT:    adrp x8, .LCPI14_1
379; CHECK-NEXT:    smull2 v2.2d, v0.4s, v1.4s
380; CHECK-NEXT:    smull v1.2d, v0.2s, v1.2s
381; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v2.4s
382; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI14_1]
383; CHECK-NEXT:    adrp x8, .LCPI14_2
384; CHECK-NEXT:    mla v1.4s, v0.4s, v2.4s
385; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI14_2]
386; CHECK-NEXT:    adrp x8, .LCPI14_3
387; CHECK-NEXT:    sshl v2.4s, v1.4s, v2.4s
388; CHECK-NEXT:    usra v2.4s, v1.4s, #31
389; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI14_3]
390; CHECK-NEXT:    mls v0.4s, v2.4s, v1.4s
391; CHECK-NEXT:    movi v1.4s, #1
392; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
393; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
394; CHECK-NEXT:    ret
395  %srem = srem <4 x i32> %X, <i32 14, i32 14, i32 2147483648, i32 14>
396  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
397  %ret = zext <4 x i1> %cmp to <4 x i32>
398  ret <4 x i32> %ret
399}
400
401; One INT_MIN divisor in odd+even divisor
402define <4 x i32> @test_srem_odd_even_INT_MIN(<4 x i32> %X) nounwind {
403; CHECK-LABEL: test_srem_odd_even_INT_MIN:
404; CHECK:       // %bb.0:
405; CHECK-NEXT:    adrp x8, .LCPI15_0
406; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI15_0]
407; CHECK-NEXT:    adrp x8, .LCPI15_1
408; CHECK-NEXT:    smull2 v2.2d, v0.4s, v1.4s
409; CHECK-NEXT:    smull v1.2d, v0.2s, v1.2s
410; CHECK-NEXT:    uzp2 v1.4s, v1.4s, v2.4s
411; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI15_1]
412; CHECK-NEXT:    adrp x8, .LCPI15_2
413; CHECK-NEXT:    mla v1.4s, v0.4s, v2.4s
414; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI15_2]
415; CHECK-NEXT:    adrp x8, .LCPI15_3
416; CHECK-NEXT:    sshl v2.4s, v1.4s, v2.4s
417; CHECK-NEXT:    usra v2.4s, v1.4s, #31
418; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI15_3]
419; CHECK-NEXT:    mls v0.4s, v2.4s, v1.4s
420; CHECK-NEXT:    movi v1.4s, #1
421; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
422; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
423; CHECK-NEXT:    ret
424  %srem = srem <4 x i32> %X, <i32 5, i32 14, i32 2147483648, i32 100>
425  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
426  %ret = zext <4 x i1> %cmp to <4 x i32>
427  ret <4 x i32> %ret
428}
429
430;==============================================================================;
431
432; One all-ones divisor and power-of-two divisor divisor in odd divisor
433define <4 x i32> @test_srem_odd_allones_and_poweroftwo(<4 x i32> %X) nounwind {
434; CHECK-LABEL: test_srem_odd_allones_and_poweroftwo:
435; CHECK:       // %bb.0:
436; CHECK-NEXT:    adrp x8, .LCPI16_0
437; CHECK-NEXT:    adrp x9, .LCPI16_1
438; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI16_0]
439; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI16_1]
440; CHECK-NEXT:    adrp x8, .LCPI16_2
441; CHECK-NEXT:    adrp x9, .LCPI16_3
442; CHECK-NEXT:    mla v2.4s, v0.4s, v1.4s
443; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI16_2]
444; CHECK-NEXT:    ldr q1, [x9, :lo12:.LCPI16_3]
445; CHECK-NEXT:    adrp x8, .LCPI16_4
446; CHECK-NEXT:    ushl v0.4s, v2.4s, v0.4s
447; CHECK-NEXT:    ushl v1.4s, v2.4s, v1.4s
448; CHECK-NEXT:    movi v2.4s, #1
449; CHECK-NEXT:    orr v0.16b, v1.16b, v0.16b
450; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI16_4]
451; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
452; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
453; CHECK-NEXT:    ret
454  %srem = srem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 5>
455  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
456  %ret = zext <4 x i1> %cmp to <4 x i32>
457  ret <4 x i32> %ret
458}
459
460; One all-ones divisor and power-of-two divisor divisor in even divisor
461define <4 x i32> @test_srem_even_allones_and_poweroftwo(<4 x i32> %X) nounwind {
462; CHECK-LABEL: test_srem_even_allones_and_poweroftwo:
463; CHECK:       // %bb.0:
464; CHECK-NEXT:    adrp x8, .LCPI17_0
465; CHECK-NEXT:    adrp x9, .LCPI17_1
466; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI17_0]
467; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI17_1]
468; CHECK-NEXT:    adrp x8, .LCPI17_2
469; CHECK-NEXT:    adrp x9, .LCPI17_3
470; CHECK-NEXT:    mla v2.4s, v0.4s, v1.4s
471; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI17_2]
472; CHECK-NEXT:    ldr q1, [x9, :lo12:.LCPI17_3]
473; CHECK-NEXT:    adrp x8, .LCPI17_4
474; CHECK-NEXT:    ushl v0.4s, v2.4s, v0.4s
475; CHECK-NEXT:    ushl v1.4s, v2.4s, v1.4s
476; CHECK-NEXT:    movi v2.4s, #1
477; CHECK-NEXT:    orr v0.16b, v1.16b, v0.16b
478; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI17_4]
479; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
480; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
481; CHECK-NEXT:    ret
482  %srem = srem <4 x i32> %X, <i32 14, i32 4294967295, i32 16, i32 14>
483  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
484  %ret = zext <4 x i1> %cmp to <4 x i32>
485  ret <4 x i32> %ret
486}
487
488; One all-ones divisor and power-of-two divisor divisor in odd+even divisor
489define <4 x i32> @test_srem_odd_even_allones_and_poweroftwo(<4 x i32> %X) nounwind {
490; CHECK-LABEL: test_srem_odd_even_allones_and_poweroftwo:
491; CHECK:       // %bb.0:
492; CHECK-NEXT:    adrp x8, .LCPI18_0
493; CHECK-NEXT:    adrp x9, .LCPI18_1
494; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI18_0]
495; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI18_1]
496; CHECK-NEXT:    adrp x8, .LCPI18_2
497; CHECK-NEXT:    adrp x9, .LCPI18_3
498; CHECK-NEXT:    mla v2.4s, v0.4s, v1.4s
499; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI18_2]
500; CHECK-NEXT:    ldr q1, [x9, :lo12:.LCPI18_3]
501; CHECK-NEXT:    adrp x8, .LCPI18_4
502; CHECK-NEXT:    ushl v0.4s, v2.4s, v0.4s
503; CHECK-NEXT:    ushl v1.4s, v2.4s, v1.4s
504; CHECK-NEXT:    movi v2.4s, #1
505; CHECK-NEXT:    orr v0.16b, v1.16b, v0.16b
506; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI18_4]
507; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
508; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
509; CHECK-NEXT:    ret
510  %srem = srem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 100>
511  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
512  %ret = zext <4 x i1> %cmp to <4 x i32>
513  ret <4 x i32> %ret
514}
515
516;------------------------------------------------------------------------------;
517
518; One all-ones divisor and one one divisor in odd divisor
519define <4 x i32> @test_srem_odd_allones_and_one(<4 x i32> %X) nounwind {
520; CHECK-LABEL: test_srem_odd_allones_and_one:
521; CHECK:       // %bb.0:
522; CHECK-NEXT:    movi v1.16b, #153
523; CHECK-NEXT:    mov w8, #52429 // =0xcccd
524; CHECK-NEXT:    movk w8, #52428, lsl #16
525; CHECK-NEXT:    dup v2.4s, w8
526; CHECK-NEXT:    adrp x8, .LCPI19_0
527; CHECK-NEXT:    fneg v1.4s, v1.4s
528; CHECK-NEXT:    mla v1.4s, v0.4s, v2.4s
529; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI19_0]
530; CHECK-NEXT:    movi v2.4s, #1
531; CHECK-NEXT:    cmhs v0.4s, v0.4s, v1.4s
532; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
533; CHECK-NEXT:    ret
534  %srem = srem <4 x i32> %X, <i32 5, i32 4294967295, i32 1, i32 5>
535  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
536  %ret = zext <4 x i1> %cmp to <4 x i32>
537  ret <4 x i32> %ret
538}
539
540; One all-ones divisor and one one divisor in even divisor
541define <4 x i32> @test_srem_even_allones_and_one(<4 x i32> %X) nounwind {
542; CHECK-LABEL: test_srem_even_allones_and_one:
543; CHECK:       // %bb.0:
544; CHECK-NEXT:    mov w8, #28087 // =0x6db7
545; CHECK-NEXT:    mov w9, #9362 // =0x2492
546; CHECK-NEXT:    movk w8, #46811, lsl #16
547; CHECK-NEXT:    movk w9, #4681, lsl #16
548; CHECK-NEXT:    dup v1.4s, w8
549; CHECK-NEXT:    dup v2.4s, w9
550; CHECK-NEXT:    adrp x8, .LCPI20_0
551; CHECK-NEXT:    mla v2.4s, v0.4s, v1.4s
552; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI20_0]
553; CHECK-NEXT:    shl v0.4s, v2.4s, #31
554; CHECK-NEXT:    usra v0.4s, v2.4s, #1
555; CHECK-NEXT:    movi v2.4s, #1
556; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
557; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
558; CHECK-NEXT:    ret
559  %srem = srem <4 x i32> %X, <i32 14, i32 4294967295, i32 1, i32 14>
560  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
561  %ret = zext <4 x i1> %cmp to <4 x i32>
562  ret <4 x i32> %ret
563}
564
565; One all-ones divisor and one one divisor in odd+even divisor
566define <4 x i32> @test_srem_odd_even_allones_and_one(<4 x i32> %X) nounwind {
567; CHECK-LABEL: test_srem_odd_even_allones_and_one:
568; CHECK:       // %bb.0:
569; CHECK-NEXT:    adrp x8, .LCPI21_0
570; CHECK-NEXT:    adrp x9, .LCPI21_1
571; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI21_0]
572; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI21_1]
573; CHECK-NEXT:    adrp x8, .LCPI21_2
574; CHECK-NEXT:    adrp x9, .LCPI21_3
575; CHECK-NEXT:    mla v2.4s, v0.4s, v1.4s
576; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI21_2]
577; CHECK-NEXT:    ldr q1, [x9, :lo12:.LCPI21_3]
578; CHECK-NEXT:    adrp x8, .LCPI21_4
579; CHECK-NEXT:    ushl v0.4s, v2.4s, v0.4s
580; CHECK-NEXT:    ushl v1.4s, v2.4s, v1.4s
581; CHECK-NEXT:    movi v2.4s, #1
582; CHECK-NEXT:    orr v0.16b, v1.16b, v0.16b
583; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI21_4]
584; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
585; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
586; CHECK-NEXT:    ret
587  %srem = srem <4 x i32> %X, <i32 5, i32 4294967295, i32 1, i32 100>
588  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
589  %ret = zext <4 x i1> %cmp to <4 x i32>
590  ret <4 x i32> %ret
591}
592
593;------------------------------------------------------------------------------;
594
595; One power-of-two divisor divisor and one divisor in odd divisor
596define <4 x i32> @test_srem_odd_poweroftwo_and_one(<4 x i32> %X) nounwind {
597; CHECK-LABEL: test_srem_odd_poweroftwo_and_one:
598; CHECK:       // %bb.0:
599; CHECK-NEXT:    adrp x8, .LCPI22_0
600; CHECK-NEXT:    adrp x9, .LCPI22_1
601; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI22_0]
602; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI22_1]
603; CHECK-NEXT:    adrp x8, .LCPI22_2
604; CHECK-NEXT:    adrp x9, .LCPI22_3
605; CHECK-NEXT:    mla v2.4s, v0.4s, v1.4s
606; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI22_2]
607; CHECK-NEXT:    ldr q1, [x9, :lo12:.LCPI22_3]
608; CHECK-NEXT:    adrp x8, .LCPI22_4
609; CHECK-NEXT:    ushl v0.4s, v2.4s, v0.4s
610; CHECK-NEXT:    ushl v1.4s, v2.4s, v1.4s
611; CHECK-NEXT:    movi v2.4s, #1
612; CHECK-NEXT:    orr v0.16b, v1.16b, v0.16b
613; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI22_4]
614; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
615; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
616; CHECK-NEXT:    ret
617  %srem = srem <4 x i32> %X, <i32 5, i32 16, i32 1, i32 5>
618  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
619  %ret = zext <4 x i1> %cmp to <4 x i32>
620  ret <4 x i32> %ret
621}
622
623; One power-of-two divisor divisor and one divisor in even divisor
624define <4 x i32> @test_srem_even_poweroftwo_and_one(<4 x i32> %X) nounwind {
625; CHECK-LABEL: test_srem_even_poweroftwo_and_one:
626; CHECK:       // %bb.0:
627; CHECK-NEXT:    adrp x8, .LCPI23_0
628; CHECK-NEXT:    adrp x9, .LCPI23_1
629; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI23_0]
630; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI23_1]
631; CHECK-NEXT:    adrp x8, .LCPI23_2
632; CHECK-NEXT:    adrp x9, .LCPI23_3
633; CHECK-NEXT:    mla v2.4s, v0.4s, v1.4s
634; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI23_2]
635; CHECK-NEXT:    ldr q1, [x9, :lo12:.LCPI23_3]
636; CHECK-NEXT:    adrp x8, .LCPI23_4
637; CHECK-NEXT:    ushl v0.4s, v2.4s, v0.4s
638; CHECK-NEXT:    ushl v1.4s, v2.4s, v1.4s
639; CHECK-NEXT:    movi v2.4s, #1
640; CHECK-NEXT:    orr v0.16b, v1.16b, v0.16b
641; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI23_4]
642; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
643; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
644; CHECK-NEXT:    ret
645  %srem = srem <4 x i32> %X, <i32 14, i32 16, i32 1, i32 14>
646  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
647  %ret = zext <4 x i1> %cmp to <4 x i32>
648  ret <4 x i32> %ret
649}
650
651; One power-of-two divisor divisor and one divisor in odd+even divisor
652define <4 x i32> @test_srem_odd_even_poweroftwo_and_one(<4 x i32> %X) nounwind {
653; CHECK-LABEL: test_srem_odd_even_poweroftwo_and_one:
654; CHECK:       // %bb.0:
655; CHECK-NEXT:    adrp x8, .LCPI24_0
656; CHECK-NEXT:    adrp x9, .LCPI24_1
657; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI24_0]
658; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI24_1]
659; CHECK-NEXT:    adrp x8, .LCPI24_2
660; CHECK-NEXT:    adrp x9, .LCPI24_3
661; CHECK-NEXT:    mla v2.4s, v0.4s, v1.4s
662; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI24_2]
663; CHECK-NEXT:    ldr q1, [x9, :lo12:.LCPI24_3]
664; CHECK-NEXT:    adrp x8, .LCPI24_4
665; CHECK-NEXT:    ushl v0.4s, v2.4s, v0.4s
666; CHECK-NEXT:    ushl v1.4s, v2.4s, v1.4s
667; CHECK-NEXT:    movi v2.4s, #1
668; CHECK-NEXT:    orr v0.16b, v1.16b, v0.16b
669; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI24_4]
670; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
671; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
672; CHECK-NEXT:    ret
673  %srem = srem <4 x i32> %X, <i32 5, i32 16, i32 1, i32 100>
674  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
675  %ret = zext <4 x i1> %cmp to <4 x i32>
676  ret <4 x i32> %ret
677}
678
679;------------------------------------------------------------------------------;
680
681define <4 x i32> @test_srem_odd_allones_and_poweroftwo_and_one(<4 x i32> %X) nounwind {
682; CHECK-LABEL: test_srem_odd_allones_and_poweroftwo_and_one:
683; CHECK:       // %bb.0:
684; CHECK-NEXT:    adrp x8, .LCPI25_0
685; CHECK-NEXT:    adrp x9, .LCPI25_1
686; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI25_0]
687; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI25_1]
688; CHECK-NEXT:    adrp x8, .LCPI25_2
689; CHECK-NEXT:    adrp x9, .LCPI25_3
690; CHECK-NEXT:    mla v2.4s, v0.4s, v1.4s
691; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI25_2]
692; CHECK-NEXT:    ldr q1, [x9, :lo12:.LCPI25_3]
693; CHECK-NEXT:    adrp x8, .LCPI25_4
694; CHECK-NEXT:    ushl v0.4s, v2.4s, v0.4s
695; CHECK-NEXT:    ushl v1.4s, v2.4s, v1.4s
696; CHECK-NEXT:    movi v2.4s, #1
697; CHECK-NEXT:    orr v0.16b, v1.16b, v0.16b
698; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI25_4]
699; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
700; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
701; CHECK-NEXT:    ret
702  %srem = srem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 1>
703  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
704  %ret = zext <4 x i1> %cmp to <4 x i32>
705  ret <4 x i32> %ret
706}
707
708define <4 x i32> @test_srem_even_allones_and_poweroftwo_and_one(<4 x i32> %X) nounwind {
709; CHECK-LABEL: test_srem_even_allones_and_poweroftwo_and_one:
710; CHECK:       // %bb.0:
711; CHECK-NEXT:    adrp x8, .LCPI26_0
712; CHECK-NEXT:    adrp x9, .LCPI26_1
713; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI26_0]
714; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI26_1]
715; CHECK-NEXT:    adrp x8, .LCPI26_2
716; CHECK-NEXT:    adrp x9, .LCPI26_3
717; CHECK-NEXT:    mla v2.4s, v0.4s, v1.4s
718; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI26_2]
719; CHECK-NEXT:    ldr q1, [x9, :lo12:.LCPI26_3]
720; CHECK-NEXT:    adrp x8, .LCPI26_4
721; CHECK-NEXT:    ushl v0.4s, v2.4s, v0.4s
722; CHECK-NEXT:    ushl v1.4s, v2.4s, v1.4s
723; CHECK-NEXT:    movi v2.4s, #1
724; CHECK-NEXT:    orr v0.16b, v1.16b, v0.16b
725; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI26_4]
726; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
727; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
728; CHECK-NEXT:    ret
729  %srem = srem <4 x i32> %X, <i32 14, i32 4294967295, i32 16, i32 1>
730  %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
731  %ret = zext <4 x i1> %cmp to <4 x i32>
732  ret <4 x i32> %ret
733}
734