xref: /llvm-project/llvm/test/CodeGen/AArch64/srem-pow2.ll (revision 222adf338a41bb024f70812a198497ef95826e81) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
3
4define i16 @fold_srem_1_i16(i16 %x) {
5; CHECK-LABEL: fold_srem_1_i16:
6; CHECK:       // %bb.0:
7; CHECK-NEXT:    mov w0, wzr
8; CHECK-NEXT:    ret
9  %1 = srem i16 %x, 1
10  ret i16 %1
11}
12
13define i32 @fold_srem_1_i32(i32 %x) {
14; CHECK-LABEL: fold_srem_1_i32:
15; CHECK:       // %bb.0:
16; CHECK-NEXT:    mov w0, wzr
17; CHECK-NEXT:    ret
18  %1 = srem i32 %x, 1
19  ret i32 %1
20}
21
22define i64 @fold_srem_1_i64(i64 %x) {
23; CHECK-LABEL: fold_srem_1_i64:
24; CHECK:       // %bb.0:
25; CHECK-NEXT:    mov x0, xzr
26; CHECK-NEXT:    ret
27  %1 = srem i64 %x, 1
28  ret i64 %1
29}
30
31define i16 @fold_srem_2_i16(i16 %x) {
32; CHECK-LABEL: fold_srem_2_i16:
33; CHECK:       // %bb.0:
34; CHECK-NEXT:    and w8, w0, #0x8000
35; CHECK-NEXT:    add w8, w0, w8, lsr #15
36; CHECK-NEXT:    and w8, w8, #0xfffffffe
37; CHECK-NEXT:    sub w0, w0, w8
38; CHECK-NEXT:    ret
39  %1 = srem i16 %x, 2
40  ret i16 %1
41}
42
43define i32 @fold_srem_2_i64(i32 %x) {
44; CHECK-LABEL: fold_srem_2_i64:
45; CHECK:       // %bb.0:
46; CHECK-NEXT:    and w8, w0, #0x1
47; CHECK-NEXT:    cmp w0, #0
48; CHECK-NEXT:    cneg w0, w8, lt
49; CHECK-NEXT:    ret
50  %1 = srem i32 %x, 2
51  ret i32 %1
52}
53
54define i64 @fold_srem_2_i32(i64 %x) {
55; CHECK-LABEL: fold_srem_2_i32:
56; CHECK:       // %bb.0:
57; CHECK-NEXT:    and x8, x0, #0x1
58; CHECK-NEXT:    cmp x0, #0
59; CHECK-NEXT:    cneg x0, x8, lt
60; CHECK-NEXT:    ret
61  %1 = srem i64 %x, 2
62  ret i64 %1
63}
64
65define i16 @fold_srem_pow2_i16(i16 %x) {
66; CHECK-LABEL: fold_srem_pow2_i16:
67; CHECK:       // %bb.0:
68; CHECK-NEXT:    sxth w8, w0
69; CHECK-NEXT:    ubfx w8, w8, #25, #6
70; CHECK-NEXT:    add w8, w0, w8
71; CHECK-NEXT:    and w8, w8, #0xffffffc0
72; CHECK-NEXT:    sub w0, w0, w8
73; CHECK-NEXT:    ret
74  %1 = srem i16 %x, 64
75  ret i16 %1
76}
77
78define i32 @fold_srem_pow2_i32(i32 %x) {
79; CHECK-LABEL: fold_srem_pow2_i32:
80; CHECK:       // %bb.0:
81; CHECK-NEXT:    negs w8, w0
82; CHECK-NEXT:    and w9, w0, #0x3f
83; CHECK-NEXT:    and w8, w8, #0x3f
84; CHECK-NEXT:    csneg w0, w9, w8, mi
85; CHECK-NEXT:    ret
86  %1 = srem i32 %x, 64
87  ret i32 %1
88}
89
90define i64 @fold_srem_pow2_i64(i64 %x) {
91; CHECK-LABEL: fold_srem_pow2_i64:
92; CHECK:       // %bb.0:
93; CHECK-NEXT:    negs x8, x0
94; CHECK-NEXT:    and x9, x0, #0x3f
95; CHECK-NEXT:    and x8, x8, #0x3f
96; CHECK-NEXT:    csneg x0, x9, x8, mi
97; CHECK-NEXT:    ret
98  %1 = srem i64 %x, 64
99  ret i64 %1
100}
101
102define i16 @fold_srem_smax_i16(i16 %x) {
103; CHECK-LABEL: fold_srem_smax_i16:
104; CHECK:       // %bb.0:
105; CHECK-NEXT:    sxth w8, w0
106; CHECK-NEXT:    ubfx w8, w8, #16, #15
107; CHECK-NEXT:    add w8, w0, w8
108; CHECK-NEXT:    and w8, w8, #0xffff8000
109; CHECK-NEXT:    add w0, w0, w8
110; CHECK-NEXT:    ret
111  %1 = srem i16 %x, 32768
112  ret i16 %1
113}
114
115define i32 @fold_srem_smax_i32(i32 %x) {
116; CHECK-LABEL: fold_srem_smax_i32:
117; CHECK:       // %bb.0:
118; CHECK-NEXT:    negs w8, w0
119; CHECK-NEXT:    and w9, w0, #0x7fffffff
120; CHECK-NEXT:    and w8, w8, #0x7fffffff
121; CHECK-NEXT:    csneg w0, w9, w8, mi
122; CHECK-NEXT:    ret
123  %1 = srem i32 %x, 2147483648
124  ret i32 %1
125}
126
127define i64 @fold_srem_smax_i64(i64 %x) {
128; CHECK-LABEL: fold_srem_smax_i64:
129; CHECK:       // %bb.0:
130; CHECK-NEXT:    negs x8, x0
131; CHECK-NEXT:    and x9, x0, #0x7fffffffffffffff
132; CHECK-NEXT:    and x8, x8, #0x7fffffffffffffff
133; CHECK-NEXT:    csneg x0, x9, x8, mi
134; CHECK-NEXT:    ret
135  %1 = srem i64 %x, -9223372036854775808
136  ret i64 %1
137}
138