xref: /llvm-project/llvm/test/CodeGen/AArch64/sme-intrinsics-mops.ll (revision 62baf21daa377c4ec1a641b26931063c1117d262) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming -verify-machineinstrs < %s | FileCheck %s
3
4define void @bfmops(<vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) {
5; CHECK-LABEL: bfmops:
6; CHECK:       // %bb.0:
7; CHECK-NEXT:    bfmops za3.s, p0/m, p1/m, z0.h, z1.h
8; CHECK-NEXT:    ret
9  call void @llvm.aarch64.sme.mops.wide.nxv8bf16(i32 3, <vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm)
10  ret void
11}
12
13define void @fmops(<vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm) {
14; CHECK-LABEL: fmops:
15; CHECK:       // %bb.0:
16; CHECK-NEXT:    fmops za3.s, p0/m, p1/m, z0.h, z1.h
17; CHECK-NEXT:    ret
18  call void @llvm.aarch64.sme.mops.wide.nxv8f16(i32 3, <vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm)
19  ret void
20}
21
22define void @smops_s(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) {
23; CHECK-LABEL: smops_s:
24; CHECK:       // %bb.0:
25; CHECK-NEXT:    smops za3.s, p0/m, p1/m, z0.b, z1.b
26; CHECK-NEXT:    ret
27  call void @llvm.aarch64.sme.smops.wide.nxv16i8(i32 3, <vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)
28  ret void
29}
30
31define void @smops_d(<vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
32; CHECK-LABEL: smops_d:
33; CHECK:       // %bb.0:
34; CHECK-NEXT:    smops za7.d, p0/m, p1/m, z0.h, z1.h
35; CHECK-NEXT:    ret
36  call void @llvm.aarch64.sme.smops.wide.nxv8i16(i32 7, <vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)
37  ret void
38}
39
40define void @umops_s(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) {
41; CHECK-LABEL: umops_s:
42; CHECK:       // %bb.0:
43; CHECK-NEXT:    umops za3.s, p0/m, p1/m, z0.b, z1.b
44; CHECK-NEXT:    ret
45  call void @llvm.aarch64.sme.umops.wide.nxv16i8(i32 3, <vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)
46  ret void
47}
48
49define void @umops_d(<vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
50; CHECK-LABEL: umops_d:
51; CHECK:       // %bb.0:
52; CHECK-NEXT:    umops za7.d, p0/m, p1/m, z0.h, z1.h
53; CHECK-NEXT:    ret
54  call void @llvm.aarch64.sme.umops.wide.nxv8i16(i32 7, <vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)
55  ret void
56}
57
58define void @fmops_s(<vscale x 4 x i1> %pn, <vscale x 4 x i1> %pm, <vscale x 4 x float> %zn, <vscale x 4 x float> %zm) {
59; CHECK-LABEL: fmops_s:
60; CHECK:       // %bb.0:
61; CHECK-NEXT:    fmops za3.s, p0/m, p1/m, z0.s, z1.s
62; CHECK-NEXT:    ret
63  call void @llvm.aarch64.sme.mops.nxv4f32(i32 3, <vscale x 4 x i1> %pn, <vscale x 4 x i1> %pm, <vscale x 4 x float> %zn, <vscale x 4 x float> %zm)
64  ret void
65}
66
67define void @fmops_d(<vscale x 2 x i1> %pn, <vscale x 2 x i1> %pm, <vscale x 2 x double> %zn, <vscale x 2 x double> %zm) #1 {
68; CHECK-LABEL: fmops_d:
69; CHECK:       // %bb.0:
70; CHECK-NEXT:    fmops za7.d, p0/m, p1/m, z0.d, z1.d
71; CHECK-NEXT:    ret
72  call void @llvm.aarch64.sme.mops.nxv2f64(i32 7, <vscale x 2 x i1> %pn, <vscale x 2 x i1> %pm, <vscale x 2 x double> %zn, <vscale x 2 x double> %zm)
73  ret void
74}
75
76define void @sumops_s(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) {
77; CHECK-LABEL: sumops_s:
78; CHECK:       // %bb.0:
79; CHECK-NEXT:    sumops za3.s, p0/m, p1/m, z0.b, z1.b
80; CHECK-NEXT:    ret
81  call void @llvm.aarch64.sme.sumops.wide.nxv16i8(i32 3, <vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)
82  ret void
83}
84
85define void @sumops_d(<vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
86; CHECK-LABEL: sumops_d:
87; CHECK:       // %bb.0:
88; CHECK-NEXT:    sumops za7.d, p0/m, p1/m, z0.h, z1.h
89; CHECK-NEXT:    ret
90  call void @llvm.aarch64.sme.sumops.wide.nxv8i16(i32 7, <vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)
91  ret void
92}
93
94define void @usmops_s(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) {
95; CHECK-LABEL: usmops_s:
96; CHECK:       // %bb.0:
97; CHECK-NEXT:    usmops za3.s, p0/m, p1/m, z0.b, z1.b
98; CHECK-NEXT:    ret
99  call void @llvm.aarch64.sme.usmops.wide.nxv16i8(i32 3, <vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)
100  ret void
101}
102
103define void @usmops_d(<vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
104; CHECK-LABEL: usmops_d:
105; CHECK:       // %bb.0:
106; CHECK-NEXT:    usmops za7.d, p0/m, p1/m, z0.h, z1.h
107; CHECK-NEXT:    ret
108  call void @llvm.aarch64.sme.usmops.wide.nxv8i16(i32 7, <vscale x 8 x i1> %pn, <vscale x 8 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)
109  ret void
110}
111
112attributes #0 = { "target-features"="+sme-i16i64" }
113attributes #1 = { "target-features"="+sme-f64f64" }
114
115declare void @llvm.aarch64.sme.mops.wide.nxv8bf16(i32, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
116declare void @llvm.aarch64.sme.mops.wide.nxv8f16(i32, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)
117declare void @llvm.aarch64.sme.mops.nxv4f32(i32, <vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
118declare void @llvm.aarch64.sme.mops.nxv2f64(i32, <vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
119declare void @llvm.aarch64.sme.smops.wide.nxv16i8(i32, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
120declare void @llvm.aarch64.sme.smops.wide.nxv8i16(i32, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
121declare void @llvm.aarch64.sme.umops.wide.nxv16i8(i32, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
122declare void @llvm.aarch64.sme.umops.wide.nxv8i16(i32, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
123declare void @llvm.aarch64.sme.sumops.wide.nxv16i8(i32, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
124declare void @llvm.aarch64.sme.sumops.wide.nxv8i16(i32, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
125declare void @llvm.aarch64.sme.usmops.wide.nxv16i8(i32, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
126declare void @llvm.aarch64.sme.usmops.wide.nxv8i16(i32, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
127