xref: /llvm-project/llvm/test/CodeGen/AArch64/sme-intrinsics-add.ll (revision 62baf21daa377c4ec1a641b26931063c1117d262) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme-i16i64 -force-streaming -verify-machineinstrs < %s | FileCheck %s
3
4define void @addha_s(<vscale x 4 x i1> %pn, <vscale x 4 x i1> %pm, <vscale x 4 x i32> %zn) {
5; CHECK-LABEL: addha_s:
6; CHECK:       // %bb.0:
7; CHECK-NEXT:    addha za0.s, p0/m, p1/m, z0.s
8; CHECK-NEXT:    ret
9  call void @llvm.aarch64.sme.addha.nxv4i32(i32 0, <vscale x 4 x i1> %pn, <vscale x 4 x i1> %pm, <vscale x 4 x i32> %zn)
10  ret void
11}
12
13define void @addva_s(<vscale x 4 x i1> %pn, <vscale x 4 x i1> %pm, <vscale x 4 x i32> %zn) {
14; CHECK-LABEL: addva_s:
15; CHECK:       // %bb.0:
16; CHECK-NEXT:    addva za3.s, p0/m, p1/m, z0.s
17; CHECK-NEXT:    ret
18  call void @llvm.aarch64.sme.addva.nxv4i32(i32 3, <vscale x 4 x i1> %pn, <vscale x 4 x i1> %pm, <vscale x 4 x i32> %zn)
19  ret void
20}
21
22define void @addha_d(<vscale x 2 x i1> %pn, <vscale x 2 x i1> %pm, <vscale x 2 x i64> %zn) {
23; CHECK-LABEL: addha_d:
24; CHECK:       // %bb.0:
25; CHECK-NEXT:    addha za0.d, p0/m, p1/m, z0.d
26; CHECK-NEXT:    ret
27  call void @llvm.aarch64.sme.addha.nxv2i64(i32 0, <vscale x 2 x i1> %pn, <vscale x 2 x i1> %pm, <vscale x 2 x i64> %zn)
28  ret void
29}
30
31define void @addva_d(<vscale x 2 x i1> %pn, <vscale x 2 x i1> %pm, <vscale x 2 x i64> %zn) {
32; CHECK-LABEL: addva_d:
33; CHECK:       // %bb.0:
34; CHECK-NEXT:    addva za7.d, p0/m, p1/m, z0.d
35; CHECK-NEXT:    ret
36  call void @llvm.aarch64.sme.addva.nxv2i64(i32 7, <vscale x 2 x i1> %pn, <vscale x 2 x i1> %pm, <vscale x 2 x i64> %zn)
37  ret void
38}
39
40declare void @llvm.aarch64.sme.addha.nxv4i32(i32, <vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i32>)
41declare void @llvm.aarch64.sme.addha.nxv2i64(i32, <vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i64>)
42declare void @llvm.aarch64.sme.addva.nxv4i32(i32, <vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i32>)
43declare void @llvm.aarch64.sme.addva.nxv2i64(i32, <vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i64>)
44