1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s 3 4define i64 @test_clear_mask_i64_i32(i64 %x) nounwind { 5; CHECK-LABEL: test_clear_mask_i64_i32: 6; CHECK: // %bb.0: // %entry 7; CHECK-NEXT: mov w8, #42 8; CHECK-NEXT: cmp w0, #0 9; CHECK-NEXT: csel x0, x8, x0, ge 10; CHECK-NEXT: ret 11entry: 12 %a = and i64 %x, 2147483648 13 %r = icmp eq i64 %a, 0 14 br i1 %r, label %t, label %f 15t: 16 br label %f 17f: 18 %ret = phi i64 [ %x, %entry], [ 42, %t] 19 ret i64 %ret 20} 21 22define i64 @test_set_mask_i64_i32(i64 %x) nounwind { 23; CHECK-LABEL: test_set_mask_i64_i32: 24; CHECK: // %bb.0: // %entry 25; CHECK-NEXT: mov w8, #42 26; CHECK-NEXT: tst x0, #0x80000000 27; CHECK-NEXT: csel x0, x8, x0, ne 28; CHECK-NEXT: ret 29entry: 30 %a = and i64 %x, 2147483648 31 %r = icmp ne i64 %a, 0 32 br i1 %r, label %t, label %f 33t: 34 br label %f 35f: 36 %ret = phi i64 [ %x, %entry], [ 42, %t] 37 ret i64 %ret 38} 39 40define i64 @test_clear_mask_i64_i16(i64 %x) nounwind { 41; CHECK-LABEL: test_clear_mask_i64_i16: 42; CHECK: // %bb.0: // %entry 43; CHECK-NEXT: mov w8, #42 44; CHECK-NEXT: tst x0, #0x8000 45; CHECK-NEXT: csel x0, x8, x0, eq 46; CHECK-NEXT: ret 47entry: 48 %a = and i64 %x, 32768 49 %r = icmp eq i64 %a, 0 50 br i1 %r, label %t, label %f 51t: 52 br label %f 53f: 54 %ret = phi i64 [ %x, %entry], [ 42, %t] 55 ret i64 %ret 56} 57 58define i64 @test_set_mask_i64_i16(i64 %x) nounwind { 59; CHECK-LABEL: test_set_mask_i64_i16: 60; CHECK: // %bb.0: // %entry 61; CHECK-NEXT: mov w8, #42 62; CHECK-NEXT: tst x0, #0x8000 63; CHECK-NEXT: csel x0, x8, x0, ne 64; CHECK-NEXT: ret 65entry: 66 %a = and i64 %x, 32768 67 %r = icmp ne i64 %a, 0 68 br i1 %r, label %t, label %f 69t: 70 br label %f 71f: 72 %ret = phi i64 [ %x, %entry], [ 42, %t] 73 ret i64 %ret 74} 75 76define i64 @test_clear_mask_i64_i8(i64 %x) nounwind { 77; CHECK-LABEL: test_clear_mask_i64_i8: 78; CHECK: // %bb.0: // %entry 79; CHECK-NEXT: mov w8, #42 80; CHECK-NEXT: tst x0, #0x80 81; CHECK-NEXT: csel x0, x8, x0, eq 82; CHECK-NEXT: ret 83entry: 84 %a = and i64 %x, 128 85 %r = icmp eq i64 %a, 0 86 br i1 %r, label %t, label %f 87t: 88 br label %f 89f: 90 %ret = phi i64 [ %x, %entry], [ 42, %t] 91 ret i64 %ret 92} 93 94define i64 @test_set_mask_i64_i8(i64 %x) nounwind { 95; CHECK-LABEL: test_set_mask_i64_i8: 96; CHECK: // %bb.0: // %entry 97; CHECK-NEXT: mov w8, #42 98; CHECK-NEXT: tst x0, #0x80 99; CHECK-NEXT: csel x0, x8, x0, ne 100; CHECK-NEXT: ret 101entry: 102 %a = and i64 %x, 128 103 %r = icmp ne i64 %a, 0 104 br i1 %r, label %t, label %f 105t: 106 br label %f 107f: 108 %ret = phi i64 [ %x, %entry], [ 42, %t] 109 ret i64 %ret 110} 111 112define i32 @test_clear_mask_i32_i16(i32 %x) nounwind { 113; CHECK-LABEL: test_clear_mask_i32_i16: 114; CHECK: // %bb.0: // %entry 115; CHECK-NEXT: mov w8, #42 116; CHECK-NEXT: tst w0, #0x8000 117; CHECK-NEXT: csel w0, w8, w0, eq 118; CHECK-NEXT: ret 119entry: 120 %a = and i32 %x, 32768 121 %r = icmp eq i32 %a, 0 122 br i1 %r, label %t, label %f 123t: 124 br label %f 125f: 126 %ret = phi i32 [ %x, %entry], [ 42, %t] 127 ret i32 %ret 128} 129 130define i32 @test_set_mask_i32_i16(i32 %x) nounwind { 131; CHECK-LABEL: test_set_mask_i32_i16: 132; CHECK: // %bb.0: // %entry 133; CHECK-NEXT: mov w8, #42 134; CHECK-NEXT: tst w0, #0x8000 135; CHECK-NEXT: csel w0, w8, w0, ne 136; CHECK-NEXT: ret 137entry: 138 %a = and i32 %x, 32768 139 %r = icmp ne i32 %a, 0 140 br i1 %r, label %t, label %f 141t: 142 br label %f 143f: 144 %ret = phi i32 [ %x, %entry], [ 42, %t] 145 ret i32 %ret 146} 147 148define i32 @test_clear_mask_i32_i8(i32 %x) nounwind { 149; CHECK-LABEL: test_clear_mask_i32_i8: 150; CHECK: // %bb.0: // %entry 151; CHECK-NEXT: mov w8, #42 152; CHECK-NEXT: tst w0, #0x80 153; CHECK-NEXT: csel w0, w8, w0, eq 154; CHECK-NEXT: ret 155entry: 156 %a = and i32 %x, 128 157 %r = icmp eq i32 %a, 0 158 br i1 %r, label %t, label %f 159t: 160 br label %f 161f: 162 %ret = phi i32 [ %x, %entry], [ 42, %t] 163 ret i32 %ret 164} 165 166define i32 @test_set_mask_i32_i8(i32 %x) nounwind { 167; CHECK-LABEL: test_set_mask_i32_i8: 168; CHECK: // %bb.0: // %entry 169; CHECK-NEXT: mov w8, #42 170; CHECK-NEXT: tst w0, #0x80 171; CHECK-NEXT: csel w0, w8, w0, ne 172; CHECK-NEXT: ret 173entry: 174 %a = and i32 %x, 128 175 %r = icmp ne i32 %a, 0 176 br i1 %r, label %t, label %f 177t: 178 br label %f 179f: 180 %ret = phi i32 [ %x, %entry], [ 42, %t] 181 ret i32 %ret 182} 183 184define i16 @test_clear_mask_i16_i8(i16 %x) nounwind { 185; CHECK-LABEL: test_clear_mask_i16_i8: 186; CHECK: // %bb.0: // %entry 187; CHECK-NEXT: mov w8, #42 188; CHECK-NEXT: tst w0, #0x80 189; CHECK-NEXT: csel w0, w8, w0, eq 190; CHECK-NEXT: ret 191entry: 192 %a = and i16 %x, 128 193 %r = icmp eq i16 %a, 0 194 br i1 %r, label %t, label %f 195t: 196 br label %f 197f: 198 %ret = phi i16 [ %x, %entry], [ 42, %t] 199 ret i16 %ret 200} 201 202define i16 @test_set_mask_i16_i8(i16 %x) nounwind { 203; CHECK-LABEL: test_set_mask_i16_i8: 204; CHECK: // %bb.0: // %entry 205; CHECK-NEXT: mov w8, #42 206; CHECK-NEXT: tst w0, #0x80 207; CHECK-NEXT: csel w0, w8, w0, ne 208; CHECK-NEXT: ret 209entry: 210 %a = and i16 %x, 128 211 %r = icmp ne i16 %a, 0 212 br i1 %r, label %t, label %f 213t: 214 br label %f 215f: 216 %ret = phi i16 [ %x, %entry], [ 42, %t] 217 ret i16 %ret 218} 219 220define i16 @test_set_mask_i16_i7(i16 %x) nounwind { 221; CHECK-LABEL: test_set_mask_i16_i7: 222; CHECK: // %bb.0: // %entry 223; CHECK-NEXT: mov w8, #42 224; CHECK-NEXT: tst w0, #0x40 225; CHECK-NEXT: csel w0, w8, w0, ne 226; CHECK-NEXT: ret 227entry: 228 %a = and i16 %x, 64 229 %r = icmp ne i16 %a, 0 230 br i1 %r, label %t, label %f 231t: 232 br label %f 233f: 234 %ret = phi i16 [ %x, %entry], [ 42, %t] 235 ret i16 %ret 236} 237