xref: /llvm-project/llvm/test/CodeGen/AArch64/shr-exact-demanded-bits.ll (revision f92bfca9fc217cad9026598ef6755e711c0be070)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2; RUN: llc < %s | FileCheck %s
3target triple = "aarch64-linux"
4
5define <2 x i32> @f(i8  %0, i8  %1) {
6; CHECK-LABEL: f:
7; CHECK:       // %bb.0:
8; CHECK-NEXT:    movi v0.2d, #0000000000000000
9; CHECK-NEXT:    mov v0.b[3], w0
10; CHECK-NEXT:    mov v0.b[7], w1
11; CHECK-NEXT:    sshr v0.2s, v0.2s, #24
12; CHECK-NEXT:    ret
13  %3 = insertelement <2 x i8> poison, i8 %0, i64 0
14  %4 = insertelement <2 x i8> %3, i8 %1, i64 1
15  %5 = shufflevector <2 x i8> %4, <2 x i8> <i8 0, i8 poison>, <8 x i32> <i32 2, i32 2, i32 2, i32 0, i32 2, i32 2, i32 2, i32 1>
16  %6 = bitcast <8 x i8> %5 to <2 x i32>
17  %7 = ashr exact <2 x i32> %6, <i32 24, i32 24>
18  ret <2 x i32> %7
19}
20
21define <2 x i32> @g(i8  %0, i8  %1) {
22; CHECK-LABEL: g:
23; CHECK:       // %bb.0:
24; CHECK-NEXT:    movi v0.2d, #0000000000000000
25; CHECK-NEXT:    mov v0.b[3], w0
26; CHECK-NEXT:    mov v0.b[7], w1
27; CHECK-NEXT:    ushr v0.2s, v0.2s, #24
28; CHECK-NEXT:    ret
29  %3 = insertelement <2 x i8> poison, i8 %0, i64 0
30  %4 = insertelement <2 x i8> %3, i8 %1, i64 1
31  %5 = shufflevector <2 x i8> %4, <2 x i8> <i8 0, i8 poison>, <8 x i32> <i32 2, i32 2, i32 2, i32 0, i32 2, i32 2, i32 2, i32 1>
32  %6 = bitcast <8 x i8> %5 to <2 x i32>
33  %7 = lshr exact <2 x i32> %6, <i32 24, i32 24>
34  ret <2 x i32> %7
35}
36