xref: /llvm-project/llvm/test/CodeGen/AArch64/settag-merge-order.ll (revision db158c7c830807caeeb0691739c41f1d522029e9)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; RUN: llc < %s -mtriple=aarch64 -mattr=+mte -aarch64-order-frame-objects=1 | FileCheck %s
3
4declare void @use(ptr %p)
5declare void @llvm.aarch64.settag(ptr %p, i64 %a)
6declare void @llvm.aarch64.settag.zero(ptr %p, i64 %a)
7
8; Two loops of size 256; the second loop updates SP.
9; After frame reordering, two loops can be merged into one.
10define void @stg128_128_gap_128_128() {
11; CHECK-LABEL: stg128_128_gap_128_128:
12; CHECK:       // %bb.0: // %entry
13; CHECK-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
14; CHECK-NEXT:    sub sp, sp, #544
15; CHECK-NEXT:    .cfi_def_cfa_offset 560
16; CHECK-NEXT:    .cfi_offset w30, -8
17; CHECK-NEXT:    .cfi_offset w29, -16
18; CHECK-NEXT:    add x0, sp, #512
19; CHECK-NEXT:    bl use
20; CHECK-NEXT:    mov x8, #512 // =0x200
21; CHECK-NEXT:  .LBB0_1: // %entry
22; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
23; CHECK-NEXT:    st2g sp, [sp], #32
24; CHECK-NEXT:    subs x8, x8, #32
25; CHECK-NEXT:    b.ne .LBB0_1
26; CHECK-NEXT:  // %bb.2: // %entry
27; CHECK-NEXT:    add sp, sp, #32
28; CHECK-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload
29; CHECK-NEXT:    ret
30entry:
31  %a = alloca i8, i32 128, align 16
32  %a2 = alloca i8, i32 128, align 16
33  %b = alloca i8, i32 32, align 16
34  %c = alloca i8, i32 128, align 16
35  %c2 = alloca i8, i32 128, align 16
36  call void @use(ptr %b)
37  call void @llvm.aarch64.settag(ptr %a, i64 128)
38  call void @llvm.aarch64.settag(ptr %a2, i64 128)
39  call void @llvm.aarch64.settag(ptr %c, i64 128)
40  call void @llvm.aarch64.settag(ptr %c2, i64 128)
41  ret void
42}
43
44define void @stg2(i1 %flag) {
45; CHECK-LABEL: stg2:
46; CHECK:       // %bb.0: // %entry
47; CHECK-NEXT:    str x29, [sp, #-32]! // 8-byte Folded Spill
48; CHECK-NEXT:    stp x30, x19, [sp, #16] // 16-byte Folded Spill
49; CHECK-NEXT:    sub sp, sp, #608
50; CHECK-NEXT:    .cfi_def_cfa_offset 640
51; CHECK-NEXT:    .cfi_offset w19, -8
52; CHECK-NEXT:    .cfi_offset w30, -16
53; CHECK-NEXT:    .cfi_offset w29, -32
54; CHECK-NEXT:    mov w19, w0
55; CHECK-NEXT:    add x0, sp, #576
56; CHECK-NEXT:    bl use
57; CHECK-NEXT:    tbz w19, #0, .LBB1_4
58; CHECK-NEXT:  // %bb.1: // %if.then
59; CHECK-NEXT:    add x9, sp, #256
60; CHECK-NEXT:    mov x8, #320 // =0x140
61; CHECK-NEXT:  .LBB1_2: // %if.then
62; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
63; CHECK-NEXT:    st2g x9, [x9], #32
64; CHECK-NEXT:    subs x8, x8, #32
65; CHECK-NEXT:    b.ne .LBB1_2
66; CHECK-NEXT:  // %bb.3: // %if.then
67; CHECK-NEXT:    b .LBB1_7
68; CHECK-NEXT:  .LBB1_4: // %if.else
69; CHECK-NEXT:    mov x9, sp
70; CHECK-NEXT:    mov x8, #256 // =0x100
71; CHECK-NEXT:  .LBB1_5: // %if.else
72; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
73; CHECK-NEXT:    st2g x9, [x9], #32
74; CHECK-NEXT:    subs x8, x8, #32
75; CHECK-NEXT:    b.ne .LBB1_5
76; CHECK-NEXT:  // %bb.6: // %if.else
77; CHECK-NEXT:  .LBB1_7: // %if.end
78; CHECK-NEXT:    mov x8, #576 // =0x240
79; CHECK-NEXT:  .LBB1_8: // %if.end
80; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
81; CHECK-NEXT:    st2g sp, [sp], #32
82; CHECK-NEXT:    subs x8, x8, #32
83; CHECK-NEXT:    b.ne .LBB1_8
84; CHECK-NEXT:  // %bb.9: // %if.end
85; CHECK-NEXT:    add sp, sp, #32
86; CHECK-NEXT:    ldp x30, x19, [sp, #16] // 16-byte Folded Reload
87; CHECK-NEXT:    ldr x29, [sp], #32 // 8-byte Folded Reload
88; CHECK-NEXT:    ret
89entry:
90  %a = alloca i8, i32 160, align 16
91  %a2 = alloca i8, i32 160, align 16
92  %b = alloca i8, i32 32, align 16
93  %c = alloca i8, i32 128, align 16
94  %c2 = alloca i8, i32 128, align 16
95  call void @use(ptr %b)
96  br i1 %flag, label %if.then, label %if.else
97
98if.then:
99  call void @llvm.aarch64.settag(ptr %a, i64 160)
100  call void @llvm.aarch64.settag(ptr %a2, i64 160)
101  br label %if.end
102
103if.else:
104  call void @llvm.aarch64.settag(ptr %c, i64 128)
105  call void @llvm.aarch64.settag(ptr %c2, i64 128)
106  br label %if.end
107
108if.end:
109  call void @llvm.aarch64.settag(ptr %a, i64 160)
110  call void @llvm.aarch64.settag(ptr %a2, i64 160)
111  call void @llvm.aarch64.settag(ptr %c, i64 128)
112  call void @llvm.aarch64.settag(ptr %c2, i64 128)
113
114  ret void
115}
116