xref: /llvm-project/llvm/test/CodeGen/AArch64/setcc-fsh.ll (revision 8eeabf674ca0f71aaf8120ebe387ea8e8f4e686c) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-- -o - %s | FileCheck %s
3
4declare i32 @llvm.fshl.i32(i32, i32, i32)
5declare i16 @llvm.fshr.i16(i16, i16, i16)
6declare i64 @llvm.fshr.i64(i64, i64, i64)
7declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
8
9define i1 @fshl_or_eq_0(i32 %x, i32 %y) {
10; CHECK-LABEL: fshl_or_eq_0:
11; CHECK:       // %bb.0:
12; CHECK-NEXT:    orr w8, w0, w1, lsl #5
13; CHECK-NEXT:    cmp w8, #0
14; CHECK-NEXT:    cset w0, eq
15; CHECK-NEXT:    ret
16  %or = or i32 %x, %y
17  %f = call i32 @llvm.fshl.i32(i32 %or, i32 %x, i32 5)
18  %r = icmp eq i32 %f, 0
19  ret i1 %r
20}
21
22define i1 @fshl_or_commute_eq_0(i32 %x, i32 %y) {
23; CHECK-LABEL: fshl_or_commute_eq_0:
24; CHECK:       // %bb.0:
25; CHECK-NEXT:    orr w8, w0, w1, lsl #5
26; CHECK-NEXT:    cmp w8, #0
27; CHECK-NEXT:    cset w0, eq
28; CHECK-NEXT:    ret
29  %or = or i32 %y, %x
30  %f = call i32 @llvm.fshl.i32(i32 %or, i32 %x, i32 5)
31  %r = icmp eq i32 %f, 0
32  ret i1 %r
33}
34
35define <4 x i1> @fshl_or2_eq_0(<4 x i32> %x, <4 x i32> %y) {
36; CHECK-LABEL: fshl_or2_eq_0:
37; CHECK:       // %bb.0:
38; CHECK-NEXT:    ushr v1.4s, v1.4s, #7
39; CHECK-NEXT:    orr v0.16b, v1.16b, v0.16b
40; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
41; CHECK-NEXT:    xtn v0.4h, v0.4s
42; CHECK-NEXT:    ret
43  %or = or <4 x i32> %x, %y
44  %f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %or, <4 x i32> <i32 25, i32 25, i32 25, i32 25>)
45  %r = icmp eq <4 x i32> %f, zeroinitializer
46  ret <4 x i1> %r
47}
48
49define <4 x i1> @fshl_or2_commute_eq_0(<4 x i32> %x, <4 x i32> %y) {
50; CHECK-LABEL: fshl_or2_commute_eq_0:
51; CHECK:       // %bb.0:
52; CHECK-NEXT:    ushr v1.4s, v1.4s, #7
53; CHECK-NEXT:    orr v0.16b, v1.16b, v0.16b
54; CHECK-NEXT:    cmeq v0.4s, v0.4s, #0
55; CHECK-NEXT:    xtn v0.4h, v0.4s
56; CHECK-NEXT:    ret
57  %or = or <4 x i32> %y, %x
58  %f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %or, <4 x i32> <i32 25, i32 25, i32 25, i32 25>)
59  %r = icmp eq <4 x i32> %f, zeroinitializer
60  ret <4 x i1> %r
61}
62
63define i1 @fshr_or_eq_0(i16 %x, i16 %y) {
64; CHECK-LABEL: fshr_or_eq_0:
65; CHECK:       // %bb.0:
66; CHECK-NEXT:    orr w8, w0, w1, lsl #8
67; CHECK-NEXT:    tst w8, #0xffff
68; CHECK-NEXT:    cset w0, eq
69; CHECK-NEXT:    ret
70  %or = or i16 %x, %y
71  %f = call i16 @llvm.fshr.i16(i16 %or, i16 %x, i16 8)
72  %r = icmp eq i16 %f, 0
73  ret i1 %r
74}
75
76define i1 @fshr_or_commute_eq_0(i16 %x, i16 %y) {
77; CHECK-LABEL: fshr_or_commute_eq_0:
78; CHECK:       // %bb.0:
79; CHECK-NEXT:    orr w8, w0, w1, lsl #8
80; CHECK-NEXT:    tst w8, #0xffff
81; CHECK-NEXT:    cset w0, eq
82; CHECK-NEXT:    ret
83  %or = or i16 %y, %x
84  %f = call i16 @llvm.fshr.i16(i16 %or, i16 %x, i16 8)
85  %r = icmp eq i16 %f, 0
86  ret i1 %r
87}
88
89define i1 @fshr_or2_eq_0(i64 %x, i64 %y) {
90; CHECK-LABEL: fshr_or2_eq_0:
91; CHECK:       // %bb.0:
92; CHECK-NEXT:    orr x8, x0, x1, lsr #3
93; CHECK-NEXT:    cmp x8, #0
94; CHECK-NEXT:    cset w0, eq
95; CHECK-NEXT:    ret
96  %or = or i64 %x, %y
97  %f = call i64 @llvm.fshr.i64(i64 %x, i64 %or, i64 3)
98  %r = icmp eq i64 %f, 0
99  ret i1 %r
100}
101
102define i1 @fshl_or_ne_0(i32 %x, i32 %y) {
103; CHECK-LABEL: fshl_or_ne_0:
104; CHECK:       // %bb.0:
105; CHECK-NEXT:    orr w8, w0, w1, lsl #7
106; CHECK-NEXT:    cmp w8, #0
107; CHECK-NEXT:    cset w0, ne
108; CHECK-NEXT:    ret
109  %or = or i32 %x, %y
110  %f = call i32 @llvm.fshl.i32(i32 %or, i32 %x, i32 7)
111  %r = icmp ne i32 %f, 0
112  ret i1 %r
113}
114
115define i1 @fshl_or_commute_ne_0(i32 %x, i32 %y) {
116; CHECK-LABEL: fshl_or_commute_ne_0:
117; CHECK:       // %bb.0:
118; CHECK-NEXT:    orr w8, w0, w1, lsl #7
119; CHECK-NEXT:    cmp w8, #0
120; CHECK-NEXT:    cset w0, ne
121; CHECK-NEXT:    ret
122  %or = or i32 %y, %x
123  %f = call i32 @llvm.fshl.i32(i32 %or, i32 %x, i32 7)
124  %r = icmp ne i32 %f, 0
125  ret i1 %r
126}
127
128define <4 x i1> @fshl_or2_ne_0(<4 x i32> %x, <4 x i32> %y) {
129; CHECK-LABEL: fshl_or2_ne_0:
130; CHECK:       // %bb.0:
131; CHECK-NEXT:    ushr v1.4s, v1.4s, #27
132; CHECK-NEXT:    orr v0.16b, v1.16b, v0.16b
133; CHECK-NEXT:    cmtst v0.4s, v0.4s, v0.4s
134; CHECK-NEXT:    xtn v0.4h, v0.4s
135; CHECK-NEXT:    ret
136  %or = or <4 x i32> %x, %y
137  %f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %or, <4 x i32> <i32 5, i32 5, i32 5, i32 5>)
138  %r = icmp ne <4 x i32> %f, zeroinitializer
139  ret <4 x i1> %r
140}
141
142define <4 x i1> @fshl_or2_commute_ne_0(<4 x i32> %x, <4 x i32> %y) {
143; CHECK-LABEL: fshl_or2_commute_ne_0:
144; CHECK:       // %bb.0:
145; CHECK-NEXT:    ushr v1.4s, v1.4s, #27
146; CHECK-NEXT:    orr v0.16b, v1.16b, v0.16b
147; CHECK-NEXT:    cmtst v0.4s, v0.4s, v0.4s
148; CHECK-NEXT:    xtn v0.4h, v0.4s
149; CHECK-NEXT:    ret
150  %or = or <4 x i32> %y, %x
151  %f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %or, <4 x i32> <i32 5, i32 5, i32 5, i32 5>)
152  %r = icmp ne <4 x i32> %f, zeroinitializer
153  ret <4 x i1> %r
154}
155
156define i1 @fshr_or_ne_0(i64 %x, i64 %y) {
157; CHECK-LABEL: fshr_or_ne_0:
158; CHECK:       // %bb.0:
159; CHECK-NEXT:    orr x8, x0, x1, lsl #63
160; CHECK-NEXT:    cmp x8, #0
161; CHECK-NEXT:    cset w0, ne
162; CHECK-NEXT:    ret
163  %or = or i64 %x, %y
164  %f = call i64 @llvm.fshr.i64(i64 %or, i64 %x, i64 1)
165  %r = icmp ne i64 %f, 0
166  ret i1 %r
167}
168
169define i1 @fshr_or_commute_ne_0(i64 %x, i64 %y) {
170; CHECK-LABEL: fshr_or_commute_ne_0:
171; CHECK:       // %bb.0:
172; CHECK-NEXT:    orr x8, x0, x1, lsl #63
173; CHECK-NEXT:    cmp x8, #0
174; CHECK-NEXT:    cset w0, ne
175; CHECK-NEXT:    ret
176  %or = or i64 %y, %x
177  %f = call i64 @llvm.fshr.i64(i64 %or, i64 %x, i64 1)
178  %r = icmp ne i64 %f, 0
179  ret i1 %r
180}
181
182define i1 @fshr_or2_ne_0(i16 %x, i16 %y) {
183; CHECK-LABEL: fshr_or2_ne_0:
184; CHECK:       // %bb.0:
185; CHECK-NEXT:    and w8, w1, #0xfffc
186; CHECK-NEXT:    orr w8, w0, w8, lsr #2
187; CHECK-NEXT:    tst w8, #0xffff
188; CHECK-NEXT:    cset w0, ne
189; CHECK-NEXT:    ret
190  %or = or i16 %x, %y
191  %f = call i16 @llvm.fshr.i16(i16 %x, i16 %or, i16 2)
192  %r = icmp ne i16 %f, 0
193  ret i1 %r
194}
195
196define i1 @fshr_or2_commute_ne_0(i16 %x, i16 %y) {
197; CHECK-LABEL: fshr_or2_commute_ne_0:
198; CHECK:       // %bb.0:
199; CHECK-NEXT:    and w8, w1, #0xfffc
200; CHECK-NEXT:    orr w8, w0, w8, lsr #2
201; CHECK-NEXT:    tst w8, #0xffff
202; CHECK-NEXT:    cset w0, ne
203; CHECK-NEXT:    ret
204  %or = or i16 %y, %x
205  %f = call i16 @llvm.fshr.i16(i16 %x, i16 %or, i16 2)
206  %r = icmp ne i16 %f, 0
207  ret i1 %r
208}
209
210define i1 @fshl_xor_eq_0(i32 %x, i32 %y) {
211; CHECK-LABEL: fshl_xor_eq_0:
212; CHECK:       // %bb.0:
213; CHECK-NEXT:    eor w8, w0, w1
214; CHECK-NEXT:    extr w8, w8, w0, #30
215; CHECK-NEXT:    cmp w8, #0
216; CHECK-NEXT:    cset w0, eq
217; CHECK-NEXT:    ret
218  %or = xor i32 %x, %y
219  %f = call i32 @llvm.fshl.i32(i32 %or, i32 %x, i32 2)
220  %r = icmp eq i32 %f, 0
221  ret i1 %r
222}
223
224define i1 @fshl_or_sgt_0(i32 %x, i32 %y) {
225; CHECK-LABEL: fshl_or_sgt_0:
226; CHECK:       // %bb.0:
227; CHECK-NEXT:    orr w8, w0, w1
228; CHECK-NEXT:    extr w8, w8, w0, #30
229; CHECK-NEXT:    cmp w8, #0
230; CHECK-NEXT:    cset w0, gt
231; CHECK-NEXT:    ret
232  %or = or i32 %x, %y
233  %f = call i32 @llvm.fshl.i32(i32 %or, i32 %x, i32 2)
234  %r = icmp sgt i32 %f, 0
235  ret i1 %r
236}
237
238define i1 @fshl_or_ne_2(i32 %x, i32 %y) {
239; CHECK-LABEL: fshl_or_ne_2:
240; CHECK:       // %bb.0:
241; CHECK-NEXT:    orr w8, w0, w1
242; CHECK-NEXT:    extr w8, w8, w0, #30
243; CHECK-NEXT:    cmp w8, #2
244; CHECK-NEXT:    cset w0, ne
245; CHECK-NEXT:    ret
246  %or = or i32 %x, %y
247  %f = call i32 @llvm.fshl.i32(i32 %or, i32 %x, i32 2)
248  %r = icmp ne i32 %f, 2
249  ret i1 %r
250}
251