1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -select-optimize -mtriple=aarch64-linux-gnu -mcpu=neoverse-v2 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-STANDARD 3; RUN: opt -select-optimize -mtriple=aarch64-linux-gnu -mcpu=neoverse-v2 -S -disable-loop-level-heuristics < %s | FileCheck %s --check-prefixes=CHECK,CHECK-FORCED 4 5target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" 6target triple = "aarch64" 7 8define i32 @minloc1(ptr nocapture readonly %0, ptr nocapture readonly %1, ptr nocapture readonly %2) { 9; CHECK-LABEL: @minloc1( 10; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0:%.*]], i64 40 11; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8 12; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i64 64 13; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr [[TMP6]], align 8 14; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i64 80 15; CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 8 16; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[TMP0]], i64 88 17; CHECK-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8 18; CHECK-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP0]], align 8 19; CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP1:%.*]], align 4 20; CHECK-NEXT: [[TMP14:%.*]] = sext i32 [[TMP13]] to i64 21; CHECK-NEXT: [[TMP15:%.*]] = add nsw i64 [[TMP14]], -1 22; CHECK-NEXT: [[TMP16:%.*]] = mul i64 [[TMP15]], [[TMP5]] 23; CHECK-NEXT: [[TMP17:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP16]] 24; CHECK-NEXT: [[TMP18:%.*]] = shl i64 [[TMP7]], 3 25; CHECK-NEXT: [[TMP19:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP18]] 26; CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP2:%.*]], align 4 27; CHECK-NEXT: [[DOTNOT:%.*]] = icmp slt i64 [[TMP9]], 1 28; CHECK-NEXT: br i1 [[DOTNOT]], label [[DOTPREHEADER:%.*]], label [[DOTPREHEADER35_LR_PH:%.*]] 29; CHECK: .preheader35.lr.ph: 30; CHECK-NEXT: [[TMP21:%.*]] = sub i64 0, [[TMP7]] 31; CHECK-NEXT: br label [[DOTPREHEADER35:%.*]] 32; CHECK: .preheader35: 33; CHECK-NEXT: [[TMP22:%.*]] = phi i32 [ 2147483647, [[DOTPREHEADER35_LR_PH]] ], [ [[TMP30:%.*]], [[SELECT_END:%.*]] ] 34; CHECK-NEXT: [[TMP23:%.*]] = phi i64 [ 0, [[DOTPREHEADER35_LR_PH]] ], [ [[IV_N:%.*]], [[SELECT_END]] ] 35; CHECK-NEXT: [[DOT045:%.*]] = phi i1 [ false, [[DOTPREHEADER35_LR_PH]] ], [ [[DOT2:%.*]], [[SELECT_END]] ] 36; CHECK-NEXT: [[DOTLCSSA364144:%.*]] = phi i32 [ 0, [[DOTPREHEADER35_LR_PH]] ], [ [[TMP29:%.*]], [[SELECT_END]] ] 37; CHECK-NEXT: [[TMP24:%.*]] = mul nsw i64 [[TMP23]], [[TMP11]] 38; CHECK-NEXT: [[TMP25:%.*]] = getelementptr i8, ptr [[TMP19]], i64 [[TMP24]] 39; CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4 40; CHECK-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], [[TMP20]] 41; CHECK-NEXT: [[TMP28:%.*]] = icmp sge i32 [[TMP26]], [[TMP22]] 42; CHECK-NEXT: [[DOTNOT33:%.*]] = and i1 [[DOT045]], [[TMP28]] 43; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[TMP27]], i1 true, i1 [[DOTNOT33]] 44; CHECK-NEXT: [[OR_COND_FROZEN:%.*]] = freeze i1 [[OR_COND]] 45; CHECK-NEXT: br i1 [[OR_COND_FROZEN]], label [[SELECT_END]], label [[SELECT_FALSE:%.*]] 46; CHECK: select.false: 47; CHECK-NEXT: br label [[SELECT_END]] 48; CHECK: select.end: 49; CHECK-NEXT: [[TMP29]] = phi i32 [ [[DOTLCSSA364144]], [[DOTPREHEADER35]] ], [ 1, [[SELECT_FALSE]] ] 50; CHECK-NEXT: [[DOT2]] = phi i1 [ [[DOT045]], [[DOTPREHEADER35]] ], [ true, [[SELECT_FALSE]] ] 51; CHECK-NEXT: [[TMP30]] = phi i32 [ [[TMP22]], [[DOTPREHEADER35]] ], [ [[TMP20]], [[SELECT_FALSE]] ] 52; CHECK-NEXT: [[NOT_OR_COND:%.*]] = xor i1 [[OR_COND]], true 53; CHECK-NEXT: [[IV_N]] = add nuw nsw i64 [[TMP23]], 1 54; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_N]], [[TMP9]] 55; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[DOTPREHEADER]], label [[DOTPREHEADER35]] 56; CHECK: .preheader: 57; CHECK-NEXT: [[DOTLCSSA3641_LCSSA:%.*]] = phi i32 [ 0, [[TMP3:%.*]] ], [ [[TMP29]], [[SELECT_END]] ] 58; CHECK-NEXT: ret i32 [[DOTLCSSA3641_LCSSA]] 59; 60 %4 = getelementptr i8, ptr %0, i64 40 61 %5 = load i64, ptr %4, align 8 62 %6 = getelementptr i8, ptr %0, i64 64 63 %7 = load i64, ptr %6, align 8 64 %8 = getelementptr i8, ptr %0, i64 80 65 %9 = load i64, ptr %8, align 8 66 %10 = getelementptr i8, ptr %0, i64 88 67 %11 = load i64, ptr %10, align 8 68 %12 = load ptr, ptr %0, align 8 69 %13 = load i32, ptr %1, align 4 70 %14 = sext i32 %13 to i64 71 %15 = add nsw i64 %14, -1 72 %16 = mul i64 %15, %5 73 %17 = getelementptr i8, ptr %12, i64 %16 74 %18 = shl i64 %7, 3 75 %19 = getelementptr i8, ptr %17, i64 %18 76 %20 = load i32, ptr %2, align 4 77 %.not = icmp slt i64 %9, 1 78 br i1 %.not, label %.preheader, label %.preheader35.lr.ph 79 80.preheader35.lr.ph: ; preds = %3 81 %21 = sub i64 0, %7 82 br label %.preheader35 83 84.preheader35: ; preds = %.preheader35.lr.ph, %.preheader35 85 %22 = phi i32 [ 2147483647, %.preheader35.lr.ph ], [ %30, %.preheader35 ] 86 %23 = phi i64 [ 0, %.preheader35.lr.ph ], [ %iv.n, %.preheader35 ] 87 %.045 = phi i1 [ false, %.preheader35.lr.ph ], [ %.2, %.preheader35 ] 88 %.lcssa364144 = phi i32 [ 0, %.preheader35.lr.ph ], [ %29, %.preheader35 ] 89 %24 = mul nsw i64 %23, %11 90 %25 = getelementptr i8, ptr %19, i64 %24 91 %26 = load i32, ptr %25, align 4 92 %27 = icmp ne i32 %26, %20 93 %28 = icmp sge i32 %26, %22 94 %.not33 = and i1 %.045, %28 95 %or.cond = select i1 %27, i1 true, i1 %.not33 96 %29 = select i1 %or.cond, i32 %.lcssa364144, i32 1 97 %not.or.cond = xor i1 %or.cond, true 98 %.2 = select i1 %not.or.cond, i1 true, i1 %.045 99 %30 = select i1 %or.cond, i32 %22, i32 %20 100 %iv.n = add nuw nsw i64 %23, 1 101 %exitcond.not = icmp eq i64 %iv.n, %9 102 br i1 %exitcond.not, label %.preheader, label %.preheader35 103 104.preheader: ; preds = %.preheader35, %3 105 %.lcssa3641.lcssa = phi i32 [ 0, %3 ], [ %29, %.preheader35 ] 106 ret i32 %.lcssa3641.lcssa 107} 108 109define i32 @minloc1_otherunusednot(ptr nocapture readonly %0, ptr nocapture readonly %1, ptr nocapture readonly %2) { 110; CHECK-STANDARD-LABEL: @minloc1_otherunusednot( 111; CHECK-STANDARD-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0:%.*]], i64 40 112; CHECK-STANDARD-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8 113; CHECK-STANDARD-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i64 64 114; CHECK-STANDARD-NEXT: [[TMP7:%.*]] = load i64, ptr [[TMP6]], align 8 115; CHECK-STANDARD-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i64 80 116; CHECK-STANDARD-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 8 117; CHECK-STANDARD-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[TMP0]], i64 88 118; CHECK-STANDARD-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8 119; CHECK-STANDARD-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP0]], align 8 120; CHECK-STANDARD-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP1:%.*]], align 4 121; CHECK-STANDARD-NEXT: [[TMP14:%.*]] = sext i32 [[TMP13]] to i64 122; CHECK-STANDARD-NEXT: [[TMP15:%.*]] = add nsw i64 [[TMP14]], -1 123; CHECK-STANDARD-NEXT: [[TMP16:%.*]] = mul i64 [[TMP15]], [[TMP5]] 124; CHECK-STANDARD-NEXT: [[TMP17:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP16]] 125; CHECK-STANDARD-NEXT: [[TMP18:%.*]] = shl i64 [[TMP7]], 3 126; CHECK-STANDARD-NEXT: [[TMP19:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP18]] 127; CHECK-STANDARD-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP2:%.*]], align 4 128; CHECK-STANDARD-NEXT: [[DOTNOT:%.*]] = icmp slt i64 [[TMP9]], 1 129; CHECK-STANDARD-NEXT: br i1 [[DOTNOT]], label [[DOTPREHEADER:%.*]], label [[DOTPREHEADER35_LR_PH:%.*]] 130; CHECK-STANDARD: .preheader35.lr.ph: 131; CHECK-STANDARD-NEXT: [[TMP21:%.*]] = sub i64 0, [[TMP7]] 132; CHECK-STANDARD-NEXT: br label [[DOTPREHEADER35:%.*]] 133; CHECK-STANDARD: .preheader35: 134; CHECK-STANDARD-NEXT: [[TMP22:%.*]] = phi i32 [ 2147483647, [[DOTPREHEADER35_LR_PH]] ], [ [[TMP30:%.*]], [[DOTPREHEADER35]] ] 135; CHECK-STANDARD-NEXT: [[TMP23:%.*]] = phi i64 [ 0, [[DOTPREHEADER35_LR_PH]] ], [ [[IV_N:%.*]], [[DOTPREHEADER35]] ] 136; CHECK-STANDARD-NEXT: [[DOT045:%.*]] = phi i1 [ false, [[DOTPREHEADER35_LR_PH]] ], [ [[DOT2:%.*]], [[DOTPREHEADER35]] ] 137; CHECK-STANDARD-NEXT: [[DOTLCSSA364144:%.*]] = phi i32 [ 0, [[DOTPREHEADER35_LR_PH]] ], [ [[TMP29:%.*]], [[DOTPREHEADER35]] ] 138; CHECK-STANDARD-NEXT: [[TMP24:%.*]] = mul nsw i64 [[TMP23]], [[TMP11]] 139; CHECK-STANDARD-NEXT: [[TMP25:%.*]] = getelementptr i8, ptr [[TMP19]], i64 [[TMP24]] 140; CHECK-STANDARD-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4 141; CHECK-STANDARD-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], [[TMP20]] 142; CHECK-STANDARD-NEXT: [[TMP28:%.*]] = icmp sge i32 [[TMP26]], [[TMP22]] 143; CHECK-STANDARD-NEXT: [[DOTNOT33:%.*]] = and i1 [[DOT045]], [[TMP28]] 144; CHECK-STANDARD-NEXT: [[OR_COND:%.*]] = select i1 [[TMP27]], i1 true, i1 [[DOTNOT33]] 145; CHECK-STANDARD-NEXT: [[TMP29]] = select i1 [[OR_COND]], i32 [[DOTLCSSA364144]], i32 1 146; CHECK-STANDARD-NEXT: [[DOT2]] = select i1 [[OR_COND]], i1 [[DOT045]], i1 true 147; CHECK-STANDARD-NEXT: [[NOT_OR_COND:%.*]] = xor i1 [[OR_COND]], true 148; CHECK-STANDARD-NEXT: [[TMP30]] = select i1 [[OR_COND]], i32 [[TMP22]], i32 [[TMP20]] 149; CHECK-STANDARD-NEXT: [[IV_N]] = add nuw nsw i64 [[TMP23]], 1 150; CHECK-STANDARD-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_N]], [[TMP9]] 151; CHECK-STANDARD-NEXT: br i1 [[EXITCOND_NOT]], label [[DOTPREHEADER]], label [[DOTPREHEADER35]] 152; CHECK-STANDARD: .preheader: 153; CHECK-STANDARD-NEXT: [[DOTLCSSA3641_LCSSA:%.*]] = phi i32 [ 0, [[TMP3:%.*]] ], [ [[TMP29]], [[DOTPREHEADER35]] ] 154; CHECK-STANDARD-NEXT: [[P:%.*]] = phi i1 [ false, [[TMP3]] ], [ [[NOT_OR_COND]], [[DOTPREHEADER35]] ] 155; CHECK-STANDARD-NEXT: [[Q:%.*]] = select i1 [[P]], i32 [[DOTLCSSA3641_LCSSA]], i32 1 156; CHECK-STANDARD-NEXT: ret i32 [[Q]] 157; 158; CHECK-FORCED-LABEL: @minloc1_otherunusednot( 159; CHECK-FORCED-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0:%.*]], i64 40 160; CHECK-FORCED-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8 161; CHECK-FORCED-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i64 64 162; CHECK-FORCED-NEXT: [[TMP7:%.*]] = load i64, ptr [[TMP6]], align 8 163; CHECK-FORCED-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i64 80 164; CHECK-FORCED-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 8 165; CHECK-FORCED-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[TMP0]], i64 88 166; CHECK-FORCED-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8 167; CHECK-FORCED-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP0]], align 8 168; CHECK-FORCED-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP1:%.*]], align 4 169; CHECK-FORCED-NEXT: [[TMP14:%.*]] = sext i32 [[TMP13]] to i64 170; CHECK-FORCED-NEXT: [[TMP15:%.*]] = add nsw i64 [[TMP14]], -1 171; CHECK-FORCED-NEXT: [[TMP16:%.*]] = mul i64 [[TMP15]], [[TMP5]] 172; CHECK-FORCED-NEXT: [[TMP17:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP16]] 173; CHECK-FORCED-NEXT: [[TMP18:%.*]] = shl i64 [[TMP7]], 3 174; CHECK-FORCED-NEXT: [[TMP19:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP18]] 175; CHECK-FORCED-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP2:%.*]], align 4 176; CHECK-FORCED-NEXT: [[DOTNOT:%.*]] = icmp slt i64 [[TMP9]], 1 177; CHECK-FORCED-NEXT: br i1 [[DOTNOT]], label [[DOTPREHEADER:%.*]], label [[DOTPREHEADER35_LR_PH:%.*]] 178; CHECK-FORCED: .preheader35.lr.ph: 179; CHECK-FORCED-NEXT: [[TMP21:%.*]] = sub i64 0, [[TMP7]] 180; CHECK-FORCED-NEXT: br label [[DOTPREHEADER35:%.*]] 181; CHECK-FORCED: .preheader35: 182; CHECK-FORCED-NEXT: [[TMP22:%.*]] = phi i32 [ 2147483647, [[DOTPREHEADER35_LR_PH]] ], [ [[TMP30:%.*]], [[SELECT_END:%.*]] ] 183; CHECK-FORCED-NEXT: [[TMP23:%.*]] = phi i64 [ 0, [[DOTPREHEADER35_LR_PH]] ], [ [[IV_N:%.*]], [[SELECT_END]] ] 184; CHECK-FORCED-NEXT: [[DOT045:%.*]] = phi i1 [ false, [[DOTPREHEADER35_LR_PH]] ], [ [[DOT2:%.*]], [[SELECT_END]] ] 185; CHECK-FORCED-NEXT: [[DOTLCSSA364144:%.*]] = phi i32 [ 0, [[DOTPREHEADER35_LR_PH]] ], [ [[TMP29:%.*]], [[SELECT_END]] ] 186; CHECK-FORCED-NEXT: [[TMP24:%.*]] = mul nsw i64 [[TMP23]], [[TMP11]] 187; CHECK-FORCED-NEXT: [[TMP25:%.*]] = getelementptr i8, ptr [[TMP19]], i64 [[TMP24]] 188; CHECK-FORCED-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4 189; CHECK-FORCED-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], [[TMP20]] 190; CHECK-FORCED-NEXT: [[TMP28:%.*]] = icmp sge i32 [[TMP26]], [[TMP22]] 191; CHECK-FORCED-NEXT: [[DOTNOT33:%.*]] = and i1 [[DOT045]], [[TMP28]] 192; CHECK-FORCED-NEXT: [[OR_COND:%.*]] = select i1 [[TMP27]], i1 true, i1 [[DOTNOT33]] 193; CHECK-FORCED-NEXT: [[OR_COND_FROZEN:%.*]] = freeze i1 [[OR_COND]] 194; CHECK-FORCED-NEXT: br i1 [[OR_COND_FROZEN]], label [[SELECT_END]], label [[SELECT_FALSE:%.*]] 195; CHECK-FORCED: select.false: 196; CHECK-FORCED-NEXT: br label [[SELECT_END]] 197; CHECK-FORCED: select.end: 198; CHECK-FORCED-NEXT: [[TMP29]] = phi i32 [ [[DOTLCSSA364144]], [[DOTPREHEADER35]] ], [ 1, [[SELECT_FALSE]] ] 199; CHECK-FORCED-NEXT: [[DOT2]] = phi i1 [ [[DOT045]], [[DOTPREHEADER35]] ], [ true, [[SELECT_FALSE]] ] 200; CHECK-FORCED-NEXT: [[TMP30]] = phi i32 [ [[TMP22]], [[DOTPREHEADER35]] ], [ [[TMP20]], [[SELECT_FALSE]] ] 201; CHECK-FORCED-NEXT: [[NOT_OR_COND:%.*]] = xor i1 [[OR_COND]], true 202; CHECK-FORCED-NEXT: [[IV_N]] = add nuw nsw i64 [[TMP23]], 1 203; CHECK-FORCED-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_N]], [[TMP9]] 204; CHECK-FORCED-NEXT: br i1 [[EXITCOND_NOT]], label [[DOTPREHEADER]], label [[DOTPREHEADER35]] 205; CHECK-FORCED: .preheader: 206; CHECK-FORCED-NEXT: [[DOTLCSSA3641_LCSSA:%.*]] = phi i32 [ 0, [[TMP3:%.*]] ], [ [[TMP29]], [[SELECT_END]] ] 207; CHECK-FORCED-NEXT: [[P:%.*]] = phi i1 [ false, [[TMP3]] ], [ [[NOT_OR_COND]], [[SELECT_END]] ] 208; CHECK-FORCED-NEXT: [[Q:%.*]] = select i1 [[P]], i32 [[DOTLCSSA3641_LCSSA]], i32 1 209; CHECK-FORCED-NEXT: ret i32 [[Q]] 210; 211 %4 = getelementptr i8, ptr %0, i64 40 212 %5 = load i64, ptr %4, align 8 213 %6 = getelementptr i8, ptr %0, i64 64 214 %7 = load i64, ptr %6, align 8 215 %8 = getelementptr i8, ptr %0, i64 80 216 %9 = load i64, ptr %8, align 8 217 %10 = getelementptr i8, ptr %0, i64 88 218 %11 = load i64, ptr %10, align 8 219 %12 = load ptr, ptr %0, align 8 220 %13 = load i32, ptr %1, align 4 221 %14 = sext i32 %13 to i64 222 %15 = add nsw i64 %14, -1 223 %16 = mul i64 %15, %5 224 %17 = getelementptr i8, ptr %12, i64 %16 225 %18 = shl i64 %7, 3 226 %19 = getelementptr i8, ptr %17, i64 %18 227 %20 = load i32, ptr %2, align 4 228 %.not = icmp slt i64 %9, 1 229 br i1 %.not, label %.preheader, label %.preheader35.lr.ph 230 231.preheader35.lr.ph: ; preds = %3 232 %21 = sub i64 0, %7 233 br label %.preheader35 234 235.preheader35: ; preds = %.preheader35.lr.ph, %.preheader35 236 %22 = phi i32 [ 2147483647, %.preheader35.lr.ph ], [ %30, %.preheader35 ] 237 %23 = phi i64 [ 0, %.preheader35.lr.ph ], [ %iv.n, %.preheader35 ] 238 %.045 = phi i1 [ false, %.preheader35.lr.ph ], [ %.2, %.preheader35 ] 239 %.lcssa364144 = phi i32 [ 0, %.preheader35.lr.ph ], [ %29, %.preheader35 ] 240 %24 = mul nsw i64 %23, %11 241 %25 = getelementptr i8, ptr %19, i64 %24 242 %26 = load i32, ptr %25, align 4 243 %27 = icmp ne i32 %26, %20 244 %28 = icmp sge i32 %26, %22 245 %.not33 = and i1 %.045, %28 246 %or.cond = select i1 %27, i1 true, i1 %.not33 247 %29 = select i1 %or.cond, i32 %.lcssa364144, i32 1 248 %.2 = select i1 %or.cond, i1 %.045, i1 true 249 %not.or.cond = xor i1 %or.cond, true 250 %30 = select i1 %or.cond, i32 %22, i32 %20 251 %iv.n = add nuw nsw i64 %23, 1 252 %exitcond.not = icmp eq i64 %iv.n, %9 253 br i1 %exitcond.not, label %.preheader, label %.preheader35 254 255.preheader: ; preds = %.preheader35, %3 256 %.lcssa3641.lcssa = phi i32 [ 0, %3 ], [ %29, %.preheader35 ] 257 %p = phi i1 [ false, %3 ], [ %not.or.cond, %.preheader35 ] 258 %q = select i1 %p, i32 %.lcssa3641.lcssa, i32 1 259 ret i32 %q 260} 261 262define i32 @minloc1_twonot(ptr nocapture readonly %0, ptr nocapture readonly %1, ptr nocapture readonly %2) { 263; CHECK-LABEL: @minloc1_twonot( 264; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0:%.*]], i64 40 265; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8 266; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i64 64 267; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr [[TMP6]], align 8 268; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i64 80 269; CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 8 270; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[TMP0]], i64 88 271; CHECK-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8 272; CHECK-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP0]], align 8 273; CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP1:%.*]], align 4 274; CHECK-NEXT: [[TMP14:%.*]] = sext i32 [[TMP13]] to i64 275; CHECK-NEXT: [[TMP15:%.*]] = add nsw i64 [[TMP14]], -1 276; CHECK-NEXT: [[TMP16:%.*]] = mul i64 [[TMP15]], [[TMP5]] 277; CHECK-NEXT: [[TMP17:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP16]] 278; CHECK-NEXT: [[TMP18:%.*]] = shl i64 [[TMP7]], 3 279; CHECK-NEXT: [[TMP19:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP18]] 280; CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP2:%.*]], align 4 281; CHECK-NEXT: [[DOTNOT:%.*]] = icmp slt i64 [[TMP9]], 1 282; CHECK-NEXT: br i1 [[DOTNOT]], label [[DOTPREHEADER:%.*]], label [[DOTPREHEADER35_LR_PH:%.*]] 283; CHECK: .preheader35.lr.ph: 284; CHECK-NEXT: [[TMP21:%.*]] = sub i64 0, [[TMP7]] 285; CHECK-NEXT: br label [[DOTPREHEADER35:%.*]] 286; CHECK: .preheader35: 287; CHECK-NEXT: [[TMP22:%.*]] = phi i32 [ 2147483647, [[DOTPREHEADER35_LR_PH]] ], [ [[TMP30:%.*]], [[SELECT_END:%.*]] ] 288; CHECK-NEXT: [[TMP23:%.*]] = phi i64 [ 0, [[DOTPREHEADER35_LR_PH]] ], [ [[IV_N:%.*]], [[SELECT_END]] ] 289; CHECK-NEXT: [[DOT045:%.*]] = phi i1 [ false, [[DOTPREHEADER35_LR_PH]] ], [ [[DOT3:%.*]], [[SELECT_END]] ] 290; CHECK-NEXT: [[DOTLCSSA364144:%.*]] = phi i32 [ 0, [[DOTPREHEADER35_LR_PH]] ], [ [[TMP29:%.*]], [[SELECT_END]] ] 291; CHECK-NEXT: [[TMP24:%.*]] = mul nsw i64 [[TMP23]], [[TMP11]] 292; CHECK-NEXT: [[TMP25:%.*]] = getelementptr i8, ptr [[TMP19]], i64 [[TMP24]] 293; CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4 294; CHECK-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], [[TMP20]] 295; CHECK-NEXT: [[TMP28:%.*]] = icmp sge i32 [[TMP26]], [[TMP22]] 296; CHECK-NEXT: [[DOTNOT33:%.*]] = and i1 [[DOT045]], [[TMP28]] 297; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[TMP27]], i1 true, i1 [[DOTNOT33]] 298; CHECK-NEXT: [[OR_COND_FROZEN:%.*]] = freeze i1 [[OR_COND]] 299; CHECK-NEXT: br i1 [[OR_COND_FROZEN]], label [[SELECT_END]], label [[SELECT_FALSE:%.*]] 300; CHECK: select.false: 301; CHECK-NEXT: br label [[SELECT_END]] 302; CHECK: select.end: 303; CHECK-NEXT: [[TMP29]] = phi i32 [ [[DOTLCSSA364144]], [[DOTPREHEADER35]] ], [ 1, [[SELECT_FALSE]] ] 304; CHECK-NEXT: [[DOT2:%.*]] = phi i1 [ [[DOT045]], [[DOTPREHEADER35]] ], [ true, [[SELECT_FALSE]] ] 305; CHECK-NEXT: [[DOT3]] = phi i1 [ [[DOT045]], [[DOTPREHEADER35]] ], [ true, [[SELECT_FALSE]] ] 306; CHECK-NEXT: [[TMP30]] = phi i32 [ [[TMP22]], [[DOTPREHEADER35]] ], [ [[TMP20]], [[SELECT_FALSE]] ] 307; CHECK-NEXT: [[NOT_OR_COND:%.*]] = xor i1 [[OR_COND]], true 308; CHECK-NEXT: [[IV_N]] = add nuw nsw i64 [[TMP23]], 1 309; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_N]], [[TMP9]] 310; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[DOTPREHEADER]], label [[DOTPREHEADER35]] 311; CHECK: .preheader: 312; CHECK-NEXT: [[DOTLCSSA3641_LCSSA:%.*]] = phi i32 [ 0, [[TMP3:%.*]] ], [ [[TMP29]], [[SELECT_END]] ] 313; CHECK-NEXT: ret i32 [[DOTLCSSA3641_LCSSA]] 314; 315 %4 = getelementptr i8, ptr %0, i64 40 316 %5 = load i64, ptr %4, align 8 317 %6 = getelementptr i8, ptr %0, i64 64 318 %7 = load i64, ptr %6, align 8 319 %8 = getelementptr i8, ptr %0, i64 80 320 %9 = load i64, ptr %8, align 8 321 %10 = getelementptr i8, ptr %0, i64 88 322 %11 = load i64, ptr %10, align 8 323 %12 = load ptr, ptr %0, align 8 324 %13 = load i32, ptr %1, align 4 325 %14 = sext i32 %13 to i64 326 %15 = add nsw i64 %14, -1 327 %16 = mul i64 %15, %5 328 %17 = getelementptr i8, ptr %12, i64 %16 329 %18 = shl i64 %7, 3 330 %19 = getelementptr i8, ptr %17, i64 %18 331 %20 = load i32, ptr %2, align 4 332 %.not = icmp slt i64 %9, 1 333 br i1 %.not, label %.preheader, label %.preheader35.lr.ph 334 335.preheader35.lr.ph: ; preds = %3 336 %21 = sub i64 0, %7 337 br label %.preheader35 338 339.preheader35: ; preds = %.preheader35.lr.ph, %.preheader35 340 %22 = phi i32 [ 2147483647, %.preheader35.lr.ph ], [ %30, %.preheader35 ] 341 %23 = phi i64 [ 0, %.preheader35.lr.ph ], [ %iv.n, %.preheader35 ] 342 %.045 = phi i1 [ false, %.preheader35.lr.ph ], [ %.3, %.preheader35 ] 343 %.lcssa364144 = phi i32 [ 0, %.preheader35.lr.ph ], [ %29, %.preheader35 ] 344 %24 = mul nsw i64 %23, %11 345 %25 = getelementptr i8, ptr %19, i64 %24 346 %26 = load i32, ptr %25, align 4 347 %27 = icmp ne i32 %26, %20 348 %28 = icmp sge i32 %26, %22 349 %.not33 = and i1 %.045, %28 350 %or.cond = select i1 %27, i1 true, i1 %.not33 351 %29 = select i1 %or.cond, i32 %.lcssa364144, i32 1 352 %not.or.cond = xor i1 %or.cond, true 353 %.2 = select i1 %not.or.cond, i1 true, i1 %.045 354 %.3 = select i1 %not.or.cond, i1 true, i1 %.2 355 %30 = select i1 %or.cond, i32 %22, i32 %20 356 %iv.n = add nuw nsw i64 %23, 1 357 %exitcond.not = icmp eq i64 %iv.n, %9 358 br i1 %exitcond.not, label %.preheader, label %.preheader35 359 360.preheader: ; preds = %.preheader35, %3 361 %.lcssa3641.lcssa = phi i32 [ 0, %3 ], [ %29, %.preheader35 ] 362 ret i32 %.lcssa3641.lcssa 363} 364 365define i32 @minloc1_onenotdependent(ptr nocapture readonly %0, ptr nocapture readonly %1, ptr nocapture readonly %2) { 366; CHECK-LABEL: @minloc1_onenotdependent( 367; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0:%.*]], i64 40 368; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8 369; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i64 64 370; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr [[TMP6]], align 8 371; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i64 80 372; CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 8 373; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[TMP0]], i64 88 374; CHECK-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8 375; CHECK-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP0]], align 8 376; CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP1:%.*]], align 4 377; CHECK-NEXT: [[TMP14:%.*]] = sext i32 [[TMP13]] to i64 378; CHECK-NEXT: [[TMP15:%.*]] = add nsw i64 [[TMP14]], -1 379; CHECK-NEXT: [[TMP16:%.*]] = mul i64 [[TMP15]], [[TMP5]] 380; CHECK-NEXT: [[TMP17:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP16]] 381; CHECK-NEXT: [[TMP18:%.*]] = shl i64 [[TMP7]], 3 382; CHECK-NEXT: [[TMP19:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP18]] 383; CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP2:%.*]], align 4 384; CHECK-NEXT: [[DOTNOT:%.*]] = icmp slt i64 [[TMP9]], 1 385; CHECK-NEXT: br i1 [[DOTNOT]], label [[DOTPREHEADER:%.*]], label [[DOTPREHEADER35_LR_PH:%.*]] 386; CHECK: .preheader35.lr.ph: 387; CHECK-NEXT: [[TMP21:%.*]] = sub i64 0, [[TMP7]] 388; CHECK-NEXT: br label [[DOTPREHEADER35:%.*]] 389; CHECK: .preheader35: 390; CHECK-NEXT: [[TMP22:%.*]] = phi i32 [ 2147483647, [[DOTPREHEADER35_LR_PH]] ], [ [[TMP30:%.*]], [[SELECT_END:%.*]] ] 391; CHECK-NEXT: [[TMP23:%.*]] = phi i64 [ 0, [[DOTPREHEADER35_LR_PH]] ], [ [[IV_N:%.*]], [[SELECT_END]] ] 392; CHECK-NEXT: [[DOT045:%.*]] = phi i1 [ false, [[DOTPREHEADER35_LR_PH]] ], [ [[DOT3:%.*]], [[SELECT_END]] ] 393; CHECK-NEXT: [[DOTLCSSA364144:%.*]] = phi i32 [ 0, [[DOTPREHEADER35_LR_PH]] ], [ [[TMP29:%.*]], [[SELECT_END]] ] 394; CHECK-NEXT: [[TMP24:%.*]] = mul nsw i64 [[TMP23]], [[TMP11]] 395; CHECK-NEXT: [[TMP25:%.*]] = getelementptr i8, ptr [[TMP19]], i64 [[TMP24]] 396; CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4 397; CHECK-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], [[TMP20]] 398; CHECK-NEXT: [[TMP28:%.*]] = icmp sge i32 [[TMP26]], [[TMP22]] 399; CHECK-NEXT: [[DOTNOT33:%.*]] = and i1 [[DOT045]], [[TMP28]] 400; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[TMP27]], i1 true, i1 [[DOTNOT33]] 401; CHECK-NEXT: [[OR_COND_FROZEN:%.*]] = freeze i1 [[OR_COND]] 402; CHECK-NEXT: br i1 [[OR_COND_FROZEN]], label [[SELECT_END]], label [[SELECT_FALSE:%.*]] 403; CHECK: select.false: 404; CHECK-NEXT: br label [[SELECT_END]] 405; CHECK: select.end: 406; CHECK-NEXT: [[TMP29]] = phi i32 [ [[DOTLCSSA364144]], [[DOTPREHEADER35]] ], [ 1, [[SELECT_FALSE]] ] 407; CHECK-NEXT: [[DOT2:%.*]] = phi i1 [ true, [[DOTPREHEADER35]] ], [ [[DOT045]], [[SELECT_FALSE]] ] 408; CHECK-NEXT: [[DOT3]] = phi i1 [ true, [[DOTPREHEADER35]] ], [ true, [[SELECT_FALSE]] ] 409; CHECK-NEXT: [[TMP30]] = phi i32 [ [[TMP22]], [[DOTPREHEADER35]] ], [ [[TMP20]], [[SELECT_FALSE]] ] 410; CHECK-NEXT: [[NOT_OR_COND:%.*]] = xor i1 [[OR_COND]], true 411; CHECK-NEXT: [[IV_N]] = add nuw nsw i64 [[TMP23]], 1 412; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_N]], [[TMP9]] 413; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[DOTPREHEADER]], label [[DOTPREHEADER35]] 414; CHECK: .preheader: 415; CHECK-NEXT: [[DOTLCSSA3641_LCSSA:%.*]] = phi i32 [ 0, [[TMP3:%.*]] ], [ [[TMP29]], [[SELECT_END]] ] 416; CHECK-NEXT: ret i32 [[DOTLCSSA3641_LCSSA]] 417; 418 %4 = getelementptr i8, ptr %0, i64 40 419 %5 = load i64, ptr %4, align 8 420 %6 = getelementptr i8, ptr %0, i64 64 421 %7 = load i64, ptr %6, align 8 422 %8 = getelementptr i8, ptr %0, i64 80 423 %9 = load i64, ptr %8, align 8 424 %10 = getelementptr i8, ptr %0, i64 88 425 %11 = load i64, ptr %10, align 8 426 %12 = load ptr, ptr %0, align 8 427 %13 = load i32, ptr %1, align 4 428 %14 = sext i32 %13 to i64 429 %15 = add nsw i64 %14, -1 430 %16 = mul i64 %15, %5 431 %17 = getelementptr i8, ptr %12, i64 %16 432 %18 = shl i64 %7, 3 433 %19 = getelementptr i8, ptr %17, i64 %18 434 %20 = load i32, ptr %2, align 4 435 %.not = icmp slt i64 %9, 1 436 br i1 %.not, label %.preheader, label %.preheader35.lr.ph 437 438.preheader35.lr.ph: ; preds = %3 439 %21 = sub i64 0, %7 440 br label %.preheader35 441 442.preheader35: ; preds = %.preheader35.lr.ph, %.preheader35 443 %22 = phi i32 [ 2147483647, %.preheader35.lr.ph ], [ %30, %.preheader35 ] 444 %23 = phi i64 [ 0, %.preheader35.lr.ph ], [ %iv.n, %.preheader35 ] 445 %.045 = phi i1 [ false, %.preheader35.lr.ph ], [ %.3, %.preheader35 ] 446 %.lcssa364144 = phi i32 [ 0, %.preheader35.lr.ph ], [ %29, %.preheader35 ] 447 %24 = mul nsw i64 %23, %11 448 %25 = getelementptr i8, ptr %19, i64 %24 449 %26 = load i32, ptr %25, align 4 450 %27 = icmp ne i32 %26, %20 451 %28 = icmp sge i32 %26, %22 452 %.not33 = and i1 %.045, %28 453 %or.cond = select i1 %27, i1 true, i1 %.not33 454 %29 = select i1 %or.cond, i32 %.lcssa364144, i32 1 455 %not.or.cond = xor i1 %or.cond, true 456 %.2 = select i1 %or.cond, i1 true, i1 %.045 457 %.3 = select i1 %not.or.cond, i1 true, i1 %.2 458 %30 = select i1 %or.cond, i32 %22, i32 %20 459 %iv.n = add nuw nsw i64 %23, 1 460 %exitcond.not = icmp eq i64 %iv.n, %9 461 br i1 %exitcond.not, label %.preheader, label %.preheader35 462 463.preheader: ; preds = %.preheader35, %3 464 %.lcssa3641.lcssa = phi i32 [ 0, %3 ], [ %29, %.preheader35 ] 465 ret i32 %.lcssa3641.lcssa 466} 467 468 469define i32 @minloc9(ptr nocapture readonly %0, ptr nocapture readonly %1, ptr nocapture readonly %2) { 470; CHECK-LABEL: @minloc9( 471; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0:%.*]], i64 40 472; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8 473; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i64 64 474; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr [[TMP6]], align 8 475; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i64 80 476; CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 8 477; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[TMP0]], i64 88 478; CHECK-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8 479; CHECK-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP0]], align 8 480; CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP1:%.*]], align 4 481; CHECK-NEXT: [[TMP14:%.*]] = sext i32 [[TMP13]] to i64 482; CHECK-NEXT: [[TMP15:%.*]] = add nsw i64 [[TMP14]], -1 483; CHECK-NEXT: [[TMP16:%.*]] = mul i64 [[TMP15]], [[TMP5]] 484; CHECK-NEXT: [[TMP17:%.*]] = getelementptr i8, ptr [[TMP12]], i64 [[TMP16]] 485; CHECK-NEXT: [[TMP18:%.*]] = shl i64 [[TMP7]], 3 486; CHECK-NEXT: [[TMP19:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP18]] 487; CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP2:%.*]], align 4 488; CHECK-NEXT: [[DOTNOT:%.*]] = icmp slt i64 [[TMP9]], 1 489; CHECK-NEXT: br i1 [[DOTNOT]], label [[DOTPREHEADER:%.*]], label [[DOTPREHEADER35_LR_PH:%.*]] 490; CHECK: .preheader35.lr.ph: 491; CHECK-NEXT: [[TMP21:%.*]] = sub i64 0, [[TMP7]] 492; CHECK-NEXT: [[DOTNEG:%.*]] = mul i64 [[TMP7]], -2 493; CHECK-NEXT: [[DOTNEG50:%.*]] = mul i64 [[TMP7]], -3 494; CHECK-NEXT: [[DOTNEG51:%.*]] = mul i64 [[TMP7]], -4 495; CHECK-NEXT: [[DOTNEG52:%.*]] = mul i64 [[TMP7]], -5 496; CHECK-NEXT: [[DOTNEG53:%.*]] = mul i64 [[TMP7]], -6 497; CHECK-NEXT: [[DOTNEG54:%.*]] = mul i64 [[TMP7]], -7 498; CHECK-NEXT: [[DOTNEG55:%.*]] = mul i64 [[TMP7]], -8 499; CHECK-NEXT: br label [[DOTPREHEADER35:%.*]] 500; CHECK: .preheader35: 501; CHECK-NEXT: [[TMP22:%.*]] = phi i32 [ 2147483647, [[DOTPREHEADER35_LR_PH]] ], [ [[TMP78:%.*]], [[SELECT_END15:%.*]] ] 502; CHECK-NEXT: [[TMP23:%.*]] = phi i64 [ 0, [[DOTPREHEADER35_LR_PH]] ], [ [[TMP79:%.*]], [[SELECT_END15]] ] 503; CHECK-NEXT: [[DOT045:%.*]] = phi i1 [ false, [[DOTPREHEADER35_LR_PH]] ], [ [[DOT2_8:%.*]], [[SELECT_END15]] ] 504; CHECK-NEXT: [[DOTLCSSA364144:%.*]] = phi i32 [ 0, [[DOTPREHEADER35_LR_PH]] ], [ [[TMP77:%.*]], [[SELECT_END15]] ] 505; CHECK-NEXT: [[TMP24:%.*]] = mul nsw i64 [[TMP23]], [[TMP11]] 506; CHECK-NEXT: [[TMP25:%.*]] = getelementptr i8, ptr [[TMP19]], i64 [[TMP24]] 507; CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4 508; CHECK-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], [[TMP20]] 509; CHECK-NEXT: [[TMP28:%.*]] = icmp sge i32 [[TMP26]], [[TMP22]] 510; CHECK-NEXT: [[DOTNOT33:%.*]] = and i1 [[DOT045]], [[TMP28]] 511; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[TMP27]], i1 true, i1 [[DOTNOT33]] 512; CHECK-NEXT: [[OR_COND_FROZEN:%.*]] = freeze i1 [[OR_COND]] 513; CHECK-NEXT: br i1 [[OR_COND_FROZEN]], label [[SELECT_END:%.*]], label [[SELECT_FALSE:%.*]] 514; CHECK: select.false: 515; CHECK-NEXT: br label [[SELECT_END]] 516; CHECK: select.end: 517; CHECK-NEXT: [[TMP29:%.*]] = phi i32 [ [[DOTLCSSA364144]], [[DOTPREHEADER35]] ], [ 1, [[SELECT_FALSE]] ] 518; CHECK-NEXT: [[DOT2:%.*]] = phi i1 [ [[DOT045]], [[DOTPREHEADER35]] ], [ true, [[SELECT_FALSE]] ] 519; CHECK-NEXT: [[TMP30:%.*]] = phi i32 [ [[TMP22]], [[DOTPREHEADER35]] ], [ [[TMP20]], [[SELECT_FALSE]] ] 520; CHECK-NEXT: [[NOT_OR_COND:%.*]] = xor i1 [[OR_COND]], true 521; CHECK-NEXT: [[TMP31:%.*]] = getelementptr i8, ptr [[TMP25]], i64 [[TMP21]] 522; CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[TMP31]], align 4 523; CHECK-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], [[TMP20]] 524; CHECK-NEXT: [[TMP34:%.*]] = icmp sge i32 [[TMP32]], [[TMP30]] 525; CHECK-NEXT: [[DOTNOT33_1:%.*]] = and i1 [[DOT2]], [[TMP34]] 526; CHECK-NEXT: [[OR_COND_1:%.*]] = select i1 [[TMP33]], i1 true, i1 [[DOTNOT33_1]] 527; CHECK-NEXT: [[OR_COND_1_FROZEN:%.*]] = freeze i1 [[OR_COND_1]] 528; CHECK-NEXT: br i1 [[OR_COND_1_FROZEN]], label [[SELECT_END1:%.*]], label [[SELECT_FALSE2:%.*]] 529; CHECK: select.false2: 530; CHECK-NEXT: br label [[SELECT_END1]] 531; CHECK: select.end1: 532; CHECK-NEXT: [[TMP35:%.*]] = phi i32 [ [[TMP29]], [[SELECT_END]] ], [ 2, [[SELECT_FALSE2]] ] 533; CHECK-NEXT: [[DOT2_1:%.*]] = phi i1 [ [[DOT2]], [[SELECT_END]] ], [ true, [[SELECT_FALSE2]] ] 534; CHECK-NEXT: [[TMP36:%.*]] = phi i32 [ [[TMP30]], [[SELECT_END]] ], [ [[TMP20]], [[SELECT_FALSE2]] ] 535; CHECK-NEXT: [[NOT_OR_COND_1:%.*]] = xor i1 [[OR_COND_1]], true 536; CHECK-NEXT: [[TMP37:%.*]] = getelementptr i8, ptr [[TMP25]], i64 [[DOTNEG]] 537; CHECK-NEXT: [[TMP38:%.*]] = load i32, ptr [[TMP37]], align 4 538; CHECK-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], [[TMP20]] 539; CHECK-NEXT: [[TMP40:%.*]] = icmp sge i32 [[TMP38]], [[TMP36]] 540; CHECK-NEXT: [[DOTNOT33_2:%.*]] = and i1 [[DOT2_1]], [[TMP40]] 541; CHECK-NEXT: [[OR_COND_2:%.*]] = select i1 [[TMP39]], i1 true, i1 [[DOTNOT33_2]] 542; CHECK-NEXT: [[OR_COND_2_FROZEN:%.*]] = freeze i1 [[OR_COND_2]] 543; CHECK-NEXT: br i1 [[OR_COND_2_FROZEN]], label [[SELECT_END3:%.*]], label [[SELECT_FALSE4:%.*]] 544; CHECK: select.false4: 545; CHECK-NEXT: br label [[SELECT_END3]] 546; CHECK: select.end3: 547; CHECK-NEXT: [[TMP41:%.*]] = phi i32 [ [[TMP35]], [[SELECT_END1]] ], [ 3, [[SELECT_FALSE4]] ] 548; CHECK-NEXT: [[DOT2_2:%.*]] = phi i1 [ [[DOT2_1]], [[SELECT_END1]] ], [ true, [[SELECT_FALSE4]] ] 549; CHECK-NEXT: [[TMP42:%.*]] = phi i32 [ [[TMP36]], [[SELECT_END1]] ], [ [[TMP20]], [[SELECT_FALSE4]] ] 550; CHECK-NEXT: [[NOT_OR_COND_2:%.*]] = xor i1 [[OR_COND_2]], true 551; CHECK-NEXT: [[TMP43:%.*]] = getelementptr i8, ptr [[TMP25]], i64 [[DOTNEG50]] 552; CHECK-NEXT: [[TMP44:%.*]] = load i32, ptr [[TMP43]], align 4 553; CHECK-NEXT: [[TMP45:%.*]] = icmp ne i32 [[TMP44]], [[TMP20]] 554; CHECK-NEXT: [[TMP46:%.*]] = icmp sge i32 [[TMP44]], [[TMP42]] 555; CHECK-NEXT: [[DOTNOT33_3:%.*]] = and i1 [[DOT2_2]], [[TMP46]] 556; CHECK-NEXT: [[OR_COND_3:%.*]] = select i1 [[TMP45]], i1 true, i1 [[DOTNOT33_3]] 557; CHECK-NEXT: [[OR_COND_3_FROZEN:%.*]] = freeze i1 [[OR_COND_3]] 558; CHECK-NEXT: br i1 [[OR_COND_3_FROZEN]], label [[SELECT_END5:%.*]], label [[SELECT_FALSE6:%.*]] 559; CHECK: select.false6: 560; CHECK-NEXT: br label [[SELECT_END5]] 561; CHECK: select.end5: 562; CHECK-NEXT: [[TMP47:%.*]] = phi i32 [ [[TMP41]], [[SELECT_END3]] ], [ 4, [[SELECT_FALSE6]] ] 563; CHECK-NEXT: [[DOT2_3:%.*]] = phi i1 [ [[DOT2_2]], [[SELECT_END3]] ], [ true, [[SELECT_FALSE6]] ] 564; CHECK-NEXT: [[TMP48:%.*]] = phi i32 [ [[TMP42]], [[SELECT_END3]] ], [ [[TMP20]], [[SELECT_FALSE6]] ] 565; CHECK-NEXT: [[NOT_OR_COND_3:%.*]] = xor i1 [[OR_COND_3]], true 566; CHECK-NEXT: [[TMP49:%.*]] = getelementptr i8, ptr [[TMP25]], i64 [[DOTNEG51]] 567; CHECK-NEXT: [[TMP50:%.*]] = load i32, ptr [[TMP49]], align 4 568; CHECK-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], [[TMP20]] 569; CHECK-NEXT: [[TMP52:%.*]] = icmp sge i32 [[TMP50]], [[TMP48]] 570; CHECK-NEXT: [[DOTNOT33_4:%.*]] = and i1 [[DOT2_3]], [[TMP52]] 571; CHECK-NEXT: [[OR_COND_4:%.*]] = select i1 [[TMP51]], i1 true, i1 [[DOTNOT33_4]] 572; CHECK-NEXT: [[OR_COND_4_FROZEN:%.*]] = freeze i1 [[OR_COND_4]] 573; CHECK-NEXT: br i1 [[OR_COND_4_FROZEN]], label [[SELECT_END7:%.*]], label [[SELECT_FALSE8:%.*]] 574; CHECK: select.false8: 575; CHECK-NEXT: br label [[SELECT_END7]] 576; CHECK: select.end7: 577; CHECK-NEXT: [[TMP53:%.*]] = phi i32 [ [[TMP47]], [[SELECT_END5]] ], [ 5, [[SELECT_FALSE8]] ] 578; CHECK-NEXT: [[DOT2_4:%.*]] = phi i1 [ [[DOT2_3]], [[SELECT_END5]] ], [ true, [[SELECT_FALSE8]] ] 579; CHECK-NEXT: [[TMP54:%.*]] = phi i32 [ [[TMP48]], [[SELECT_END5]] ], [ [[TMP20]], [[SELECT_FALSE8]] ] 580; CHECK-NEXT: [[NOT_OR_COND_4:%.*]] = xor i1 [[OR_COND_4]], true 581; CHECK-NEXT: [[TMP55:%.*]] = getelementptr i8, ptr [[TMP25]], i64 [[DOTNEG52]] 582; CHECK-NEXT: [[TMP56:%.*]] = load i32, ptr [[TMP55]], align 4 583; CHECK-NEXT: [[TMP57:%.*]] = icmp ne i32 [[TMP56]], [[TMP20]] 584; CHECK-NEXT: [[TMP58:%.*]] = icmp sge i32 [[TMP56]], [[TMP54]] 585; CHECK-NEXT: [[DOTNOT33_5:%.*]] = and i1 [[DOT2_4]], [[TMP58]] 586; CHECK-NEXT: [[OR_COND_5:%.*]] = select i1 [[TMP57]], i1 true, i1 [[DOTNOT33_5]] 587; CHECK-NEXT: [[OR_COND_5_FROZEN:%.*]] = freeze i1 [[OR_COND_5]] 588; CHECK-NEXT: br i1 [[OR_COND_5_FROZEN]], label [[SELECT_END9:%.*]], label [[SELECT_FALSE10:%.*]] 589; CHECK: select.false10: 590; CHECK-NEXT: br label [[SELECT_END9]] 591; CHECK: select.end9: 592; CHECK-NEXT: [[TMP59:%.*]] = phi i32 [ [[TMP53]], [[SELECT_END7]] ], [ 6, [[SELECT_FALSE10]] ] 593; CHECK-NEXT: [[DOT2_5:%.*]] = phi i1 [ [[DOT2_4]], [[SELECT_END7]] ], [ true, [[SELECT_FALSE10]] ] 594; CHECK-NEXT: [[TMP60:%.*]] = phi i32 [ [[TMP54]], [[SELECT_END7]] ], [ [[TMP20]], [[SELECT_FALSE10]] ] 595; CHECK-NEXT: [[NOT_OR_COND_5:%.*]] = xor i1 [[OR_COND_5]], true 596; CHECK-NEXT: [[TMP61:%.*]] = getelementptr i8, ptr [[TMP25]], i64 [[DOTNEG53]] 597; CHECK-NEXT: [[TMP62:%.*]] = load i32, ptr [[TMP61]], align 4 598; CHECK-NEXT: [[TMP63:%.*]] = icmp ne i32 [[TMP62]], [[TMP20]] 599; CHECK-NEXT: [[TMP64:%.*]] = icmp sge i32 [[TMP62]], [[TMP60]] 600; CHECK-NEXT: [[DOTNOT33_6:%.*]] = and i1 [[DOT2_5]], [[TMP64]] 601; CHECK-NEXT: [[OR_COND_6:%.*]] = select i1 [[TMP63]], i1 true, i1 [[DOTNOT33_6]] 602; CHECK-NEXT: [[OR_COND_6_FROZEN:%.*]] = freeze i1 [[OR_COND_6]] 603; CHECK-NEXT: br i1 [[OR_COND_6_FROZEN]], label [[SELECT_END11:%.*]], label [[SELECT_FALSE12:%.*]] 604; CHECK: select.false12: 605; CHECK-NEXT: br label [[SELECT_END11]] 606; CHECK: select.end11: 607; CHECK-NEXT: [[TMP65:%.*]] = phi i32 [ [[TMP59]], [[SELECT_END9]] ], [ 7, [[SELECT_FALSE12]] ] 608; CHECK-NEXT: [[DOT2_6:%.*]] = phi i1 [ [[DOT2_5]], [[SELECT_END9]] ], [ true, [[SELECT_FALSE12]] ] 609; CHECK-NEXT: [[TMP66:%.*]] = phi i32 [ [[TMP60]], [[SELECT_END9]] ], [ [[TMP20]], [[SELECT_FALSE12]] ] 610; CHECK-NEXT: [[NOT_OR_COND_6:%.*]] = xor i1 [[OR_COND_6]], true 611; CHECK-NEXT: [[TMP67:%.*]] = getelementptr i8, ptr [[TMP25]], i64 [[DOTNEG54]] 612; CHECK-NEXT: [[TMP68:%.*]] = load i32, ptr [[TMP67]], align 4 613; CHECK-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], [[TMP20]] 614; CHECK-NEXT: [[TMP70:%.*]] = icmp sge i32 [[TMP68]], [[TMP66]] 615; CHECK-NEXT: [[DOTNOT33_7:%.*]] = and i1 [[DOT2_6]], [[TMP70]] 616; CHECK-NEXT: [[OR_COND_7:%.*]] = select i1 [[TMP69]], i1 true, i1 [[DOTNOT33_7]] 617; CHECK-NEXT: [[OR_COND_7_FROZEN:%.*]] = freeze i1 [[OR_COND_7]] 618; CHECK-NEXT: br i1 [[OR_COND_7_FROZEN]], label [[SELECT_END13:%.*]], label [[SELECT_FALSE14:%.*]] 619; CHECK: select.false14: 620; CHECK-NEXT: br label [[SELECT_END13]] 621; CHECK: select.end13: 622; CHECK-NEXT: [[TMP71:%.*]] = phi i32 [ [[TMP65]], [[SELECT_END11]] ], [ 8, [[SELECT_FALSE14]] ] 623; CHECK-NEXT: [[DOT2_7:%.*]] = phi i1 [ [[DOT2_6]], [[SELECT_END11]] ], [ true, [[SELECT_FALSE14]] ] 624; CHECK-NEXT: [[TMP72:%.*]] = phi i32 [ [[TMP66]], [[SELECT_END11]] ], [ [[TMP20]], [[SELECT_FALSE14]] ] 625; CHECK-NEXT: [[NOT_OR_COND_7:%.*]] = xor i1 [[OR_COND_7]], true 626; CHECK-NEXT: [[TMP73:%.*]] = getelementptr i8, ptr [[TMP25]], i64 [[DOTNEG55]] 627; CHECK-NEXT: [[TMP74:%.*]] = load i32, ptr [[TMP73]], align 4 628; CHECK-NEXT: [[TMP75:%.*]] = icmp ne i32 [[TMP74]], [[TMP20]] 629; CHECK-NEXT: [[TMP76:%.*]] = icmp sge i32 [[TMP74]], [[TMP72]] 630; CHECK-NEXT: [[DOTNOT33_8:%.*]] = and i1 [[DOT2_7]], [[TMP76]] 631; CHECK-NEXT: [[OR_COND_8:%.*]] = select i1 [[TMP75]], i1 true, i1 [[DOTNOT33_8]] 632; CHECK-NEXT: [[OR_COND_8_FROZEN:%.*]] = freeze i1 [[OR_COND_8]] 633; CHECK-NEXT: br i1 [[OR_COND_8_FROZEN]], label [[SELECT_END15]], label [[SELECT_FALSE16:%.*]] 634; CHECK: select.false16: 635; CHECK-NEXT: br label [[SELECT_END15]] 636; CHECK: select.end15: 637; CHECK-NEXT: [[TMP77]] = phi i32 [ [[TMP71]], [[SELECT_END13]] ], [ 9, [[SELECT_FALSE16]] ] 638; CHECK-NEXT: [[DOT2_8]] = phi i1 [ [[DOT2_7]], [[SELECT_END13]] ], [ true, [[SELECT_FALSE16]] ] 639; CHECK-NEXT: [[TMP78]] = phi i32 [ [[TMP72]], [[SELECT_END13]] ], [ [[TMP20]], [[SELECT_FALSE16]] ] 640; CHECK-NEXT: [[NOT_OR_COND_8:%.*]] = xor i1 [[OR_COND_8]], true 641; CHECK-NEXT: [[TMP79]] = add nuw nsw i64 [[TMP23]], 1 642; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[TMP79]], [[TMP9]] 643; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[DOTPREHEADER]], label [[DOTPREHEADER35]] 644; CHECK: .preheader: 645; CHECK-NEXT: [[DOTLCSSA3641_LCSSA:%.*]] = phi i32 [ 0, [[TMP3:%.*]] ], [ [[TMP77]], [[SELECT_END15]] ] 646; CHECK-NEXT: ret i32 [[DOTLCSSA3641_LCSSA]] 647; 648 %4 = getelementptr i8, ptr %0, i64 40 649 %5 = load i64, ptr %4, align 8 650 %6 = getelementptr i8, ptr %0, i64 64 651 %7 = load i64, ptr %6, align 8 652 %8 = getelementptr i8, ptr %0, i64 80 653 %9 = load i64, ptr %8, align 8 654 %10 = getelementptr i8, ptr %0, i64 88 655 %11 = load i64, ptr %10, align 8 656 %12 = load ptr, ptr %0, align 8 657 %13 = load i32, ptr %1, align 4 658 %14 = sext i32 %13 to i64 659 %15 = add nsw i64 %14, -1 660 %16 = mul i64 %15, %5 661 %17 = getelementptr i8, ptr %12, i64 %16 662 %18 = shl i64 %7, 3 663 %19 = getelementptr i8, ptr %17, i64 %18 664 %20 = load i32, ptr %2, align 4 665 %.not = icmp slt i64 %9, 1 666 br i1 %.not, label %.preheader, label %.preheader35.lr.ph 667 668.preheader35.lr.ph: ; preds = %3 669 %21 = sub i64 0, %7 670 %.neg = mul i64 %7, -2 671 %.neg50 = mul i64 %7, -3 672 %.neg51 = mul i64 %7, -4 673 %.neg52 = mul i64 %7, -5 674 %.neg53 = mul i64 %7, -6 675 %.neg54 = mul i64 %7, -7 676 %.neg55 = mul i64 %7, -8 677 br label %.preheader35 678 679.preheader35: ; preds = %.preheader35.lr.ph, %.preheader35 680 %22 = phi i32 [ 2147483647, %.preheader35.lr.ph ], [ %78, %.preheader35 ] 681 %23 = phi i64 [ 0, %.preheader35.lr.ph ], [ %79, %.preheader35 ] 682 %.045 = phi i1 [ false, %.preheader35.lr.ph ], [ %.2.8, %.preheader35 ] 683 %.lcssa364144 = phi i32 [ 0, %.preheader35.lr.ph ], [ %77, %.preheader35 ] 684 %24 = mul nsw i64 %23, %11 685 %25 = getelementptr i8, ptr %19, i64 %24 686 %26 = load i32, ptr %25, align 4 687 %27 = icmp ne i32 %26, %20 688 %28 = icmp sge i32 %26, %22 689 %.not33 = and i1 %.045, %28 690 %or.cond = select i1 %27, i1 true, i1 %.not33 691 %29 = select i1 %or.cond, i32 %.lcssa364144, i32 1 692 %not.or.cond = xor i1 %or.cond, true 693 %.2 = select i1 %not.or.cond, i1 true, i1 %.045 694 %30 = select i1 %or.cond, i32 %22, i32 %20 695 %31 = getelementptr i8, ptr %25, i64 %21 696 %32 = load i32, ptr %31, align 4 697 %33 = icmp ne i32 %32, %20 698 %34 = icmp sge i32 %32, %30 699 %.not33.1 = and i1 %.2, %34 700 %or.cond.1 = select i1 %33, i1 true, i1 %.not33.1 701 %35 = select i1 %or.cond.1, i32 %29, i32 2 702 %not.or.cond.1 = xor i1 %or.cond.1, true 703 %.2.1 = select i1 %not.or.cond.1, i1 true, i1 %.2 704 %36 = select i1 %or.cond.1, i32 %30, i32 %20 705 %37 = getelementptr i8, ptr %25, i64 %.neg 706 %38 = load i32, ptr %37, align 4 707 %39 = icmp ne i32 %38, %20 708 %40 = icmp sge i32 %38, %36 709 %.not33.2 = and i1 %.2.1, %40 710 %or.cond.2 = select i1 %39, i1 true, i1 %.not33.2 711 %41 = select i1 %or.cond.2, i32 %35, i32 3 712 %not.or.cond.2 = xor i1 %or.cond.2, true 713 %.2.2 = select i1 %not.or.cond.2, i1 true, i1 %.2.1 714 %42 = select i1 %or.cond.2, i32 %36, i32 %20 715 %43 = getelementptr i8, ptr %25, i64 %.neg50 716 %44 = load i32, ptr %43, align 4 717 %45 = icmp ne i32 %44, %20 718 %46 = icmp sge i32 %44, %42 719 %.not33.3 = and i1 %.2.2, %46 720 %or.cond.3 = select i1 %45, i1 true, i1 %.not33.3 721 %47 = select i1 %or.cond.3, i32 %41, i32 4 722 %not.or.cond.3 = xor i1 %or.cond.3, true 723 %.2.3 = select i1 %not.or.cond.3, i1 true, i1 %.2.2 724 %48 = select i1 %or.cond.3, i32 %42, i32 %20 725 %49 = getelementptr i8, ptr %25, i64 %.neg51 726 %50 = load i32, ptr %49, align 4 727 %51 = icmp ne i32 %50, %20 728 %52 = icmp sge i32 %50, %48 729 %.not33.4 = and i1 %.2.3, %52 730 %or.cond.4 = select i1 %51, i1 true, i1 %.not33.4 731 %53 = select i1 %or.cond.4, i32 %47, i32 5 732 %not.or.cond.4 = xor i1 %or.cond.4, true 733 %.2.4 = select i1 %not.or.cond.4, i1 true, i1 %.2.3 734 %54 = select i1 %or.cond.4, i32 %48, i32 %20 735 %55 = getelementptr i8, ptr %25, i64 %.neg52 736 %56 = load i32, ptr %55, align 4 737 %57 = icmp ne i32 %56, %20 738 %58 = icmp sge i32 %56, %54 739 %.not33.5 = and i1 %.2.4, %58 740 %or.cond.5 = select i1 %57, i1 true, i1 %.not33.5 741 %59 = select i1 %or.cond.5, i32 %53, i32 6 742 %not.or.cond.5 = xor i1 %or.cond.5, true 743 %.2.5 = select i1 %not.or.cond.5, i1 true, i1 %.2.4 744 %60 = select i1 %or.cond.5, i32 %54, i32 %20 745 %61 = getelementptr i8, ptr %25, i64 %.neg53 746 %62 = load i32, ptr %61, align 4 747 %63 = icmp ne i32 %62, %20 748 %64 = icmp sge i32 %62, %60 749 %.not33.6 = and i1 %.2.5, %64 750 %or.cond.6 = select i1 %63, i1 true, i1 %.not33.6 751 %65 = select i1 %or.cond.6, i32 %59, i32 7 752 %not.or.cond.6 = xor i1 %or.cond.6, true 753 %.2.6 = select i1 %not.or.cond.6, i1 true, i1 %.2.5 754 %66 = select i1 %or.cond.6, i32 %60, i32 %20 755 %67 = getelementptr i8, ptr %25, i64 %.neg54 756 %68 = load i32, ptr %67, align 4 757 %69 = icmp ne i32 %68, %20 758 %70 = icmp sge i32 %68, %66 759 %.not33.7 = and i1 %.2.6, %70 760 %or.cond.7 = select i1 %69, i1 true, i1 %.not33.7 761 %71 = select i1 %or.cond.7, i32 %65, i32 8 762 %not.or.cond.7 = xor i1 %or.cond.7, true 763 %.2.7 = select i1 %not.or.cond.7, i1 true, i1 %.2.6 764 %72 = select i1 %or.cond.7, i32 %66, i32 %20 765 %73 = getelementptr i8, ptr %25, i64 %.neg55 766 %74 = load i32, ptr %73, align 4 767 %75 = icmp ne i32 %74, %20 768 %76 = icmp sge i32 %74, %72 769 %.not33.8 = and i1 %.2.7, %76 770 %or.cond.8 = select i1 %75, i1 true, i1 %.not33.8 771 %77 = select i1 %or.cond.8, i32 %71, i32 9 772 %not.or.cond.8 = xor i1 %or.cond.8, true 773 %.2.8 = select i1 %not.or.cond.8, i1 true, i1 %.2.7 774 %78 = select i1 %or.cond.8, i32 %72, i32 %20 775 %79 = add nuw nsw i64 %23, 1 776 %exitcond.not = icmp eq i64 %79, %9 777 br i1 %exitcond.not, label %.preheader, label %.preheader35 778 779.preheader: ; preds = %.preheader35, %3 780 %.lcssa3641.lcssa = phi i32 [ 0, %3 ], [ %77, %.preheader35 ] 781 ret i32 %.lcssa3641.lcssa 782} 783