xref: /llvm-project/llvm/test/CodeGen/AArch64/select_cc.ll (revision 5ddce70ef0e5a641d7fea95e31fc5e2439cb98cb) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
3
4define i64 @select_ogt_float(float %a, float %b) {
5; CHECK-LABEL: select_ogt_float:
6; CHECK:       // %bb.0: // %entry
7; CHECK-NEXT:    fcmp s0, s1
8; CHECK-NEXT:    cset w8, gt
9; CHECK-NEXT:    ubfiz x0, x8, #2, #32
10; CHECK-NEXT:    ret
11entry:
12  %cc = fcmp ogt float %a, %b
13  %sel = select i1 %cc, i64 4, i64 0
14  ret i64 %sel
15}
16
17define i64 @select_ule_float_inverse(float %a, float %b) {
18; CHECK-LABEL: select_ule_float_inverse:
19; CHECK:       // %bb.0: // %entry
20; CHECK-NEXT:    fcmp s0, s1
21; CHECK-NEXT:    cset w8, gt
22; CHECK-NEXT:    ubfiz x0, x8, #2, #32
23; CHECK-NEXT:    ret
24entry:
25  %cc = fcmp ule float %a, %b
26  %sel = select i1 %cc, i64 0, i64 4
27  ret i64 %sel
28}
29
30define i64 @select_eq_i32(i32 %a, i32 %b) {
31; CHECK-LABEL: select_eq_i32:
32; CHECK:       // %bb.0: // %entry
33; CHECK-NEXT:    cmp w0, w1
34; CHECK-NEXT:    cset w8, eq
35; CHECK-NEXT:    ubfiz x0, x8, #2, #32
36; CHECK-NEXT:    ret
37entry:
38  %cc = icmp eq i32 %a, %b
39  %sel = select i1 %cc, i64 4, i64 0
40  ret i64 %sel
41}
42
43define i64 @select_ne_i32_inverse(i32 %a, i32 %b) {
44; CHECK-LABEL: select_ne_i32_inverse:
45; CHECK:       // %bb.0: // %entry
46; CHECK-NEXT:    cmp w0, w1
47; CHECK-NEXT:    cset w8, eq
48; CHECK-NEXT:    ubfiz x0, x8, #2, #32
49; CHECK-NEXT:    ret
50entry:
51  %cc = icmp ne i32 %a, %b
52  %sel = select i1 %cc, i64 0, i64 4
53  ret i64 %sel
54}
55
56define <2 x double> @select_olt_load_cmp(<2 x double> %a, ptr %src) {
57; CHECK-LABEL: select_olt_load_cmp:
58; CHECK:       // %bb.0: // %entry
59; CHECK-NEXT:    movi d1, #0000000000000000
60; CHECK-NEXT:    ldr d2, [x0]
61; CHECK-NEXT:    fcmgt v1.2s, v2.2s, v1.2s
62; CHECK-NEXT:    sshll v1.2d, v1.2s, #0
63; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
64; CHECK-NEXT:    ret
65entry:
66  %l = load <2 x float>, ptr %src, align 4
67  %cmp = fcmp olt <2 x float> zeroinitializer, %l
68  %sel = select <2 x i1> %cmp, <2 x double> %a, <2 x double> zeroinitializer
69  ret <2 x double> %sel
70}
71
72define <4 x i32> @select_icmp_sgt(<4 x i32> %a, <4 x i8> %b) {
73; CHECK-LABEL: select_icmp_sgt:
74; CHECK:       // %bb.0: // %entry
75; CHECK-NEXT:    shl v1.4h, v1.4h, #8
76; CHECK-NEXT:    sshr v1.4h, v1.4h, #8
77; CHECK-NEXT:    cmgt v1.4h, v1.4h, #0
78; CHECK-NEXT:    sshll v1.4s, v1.4h, #0
79; CHECK-NEXT:    bic v0.16b, v0.16b, v1.16b
80; CHECK-NEXT:    ret
81entry:
82  %cmp = icmp sgt <4 x i8> %b, zeroinitializer
83  %sel = select <4 x i1> %cmp, <4 x i32> zeroinitializer, <4 x i32> %a
84  ret <4 x i32> %sel
85}
86