xref: /llvm-project/llvm/test/CodeGen/AArch64/select-with-and-or.ll (revision 43a0016f3dcff9d3932fb8d97e99460333ba7107) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
3
4define i1 @and(i32 %x, i32 %y, i32 %z, i32 %w) {
5; CHECK-LABEL: and:
6; CHECK:       // %bb.0:
7; CHECK-NEXT:    cmp w0, w1
8; CHECK-NEXT:    ccmp w2, w3, #4, eq
9; CHECK-NEXT:    cset w0, gt
10; CHECK-NEXT:    ret
11  %a = icmp eq i32 %x, %y
12  %b = icmp sgt i32 %z, %w
13  %s = select i1 %a, i1 %b, i1 false
14  ret i1 %s
15}
16
17define i1 @or(i32 %x, i32 %y, i32 %z, i32 %w) {
18; CHECK-LABEL: or:
19; CHECK:       // %bb.0:
20; CHECK-NEXT:    cmp w0, w1
21; CHECK-NEXT:    ccmp w2, w3, #0, ne
22; CHECK-NEXT:    cset w0, gt
23; CHECK-NEXT:    ret
24  %a = icmp eq i32 %x, %y
25  %b = icmp sgt i32 %z, %w
26  %s = select i1 %a, i1 true, i1 %b
27  ret i1 %s
28}
29
30define i1 @and_not(i32 %x, i32 %y, i32 %z, i32 %w) {
31; CHECK-LABEL: and_not:
32; CHECK:       // %bb.0:
33; CHECK-NEXT:    cmp w0, w1
34; CHECK-NEXT:    ccmp w2, w3, #4, ne
35; CHECK-NEXT:    cset w0, gt
36; CHECK-NEXT:    ret
37  %a = icmp eq i32 %x, %y
38  %b = icmp sgt i32 %z, %w
39  %s = select i1 %a, i1 false, i1 %b
40  ret i1 %s
41}
42
43define i1 @or_not(i32 %x, i32 %y, i32 %z, i32 %w) {
44; CHECK-LABEL: or_not:
45; CHECK:       // %bb.0:
46; CHECK-NEXT:    cmp w0, w1
47; CHECK-NEXT:    ccmp w2, w3, #0, eq
48; CHECK-NEXT:    cset w0, gt
49; CHECK-NEXT:    ret
50  %a = icmp eq i32 %x, %y
51  %b = icmp sgt i32 %z, %w
52  %s = select i1 %a, i1 %b, i1 true
53  ret i1 %s
54}
55
56define <4 x i1> @and_vec(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32> %w) {
57; CHECK-LABEL: and_vec:
58; CHECK:       // %bb.0:
59; CHECK-NEXT:    cmgt v2.4s, v2.4s, v3.4s
60; CHECK-NEXT:    cmeq v0.4s, v0.4s, v1.4s
61; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
62; CHECK-NEXT:    xtn v0.4h, v0.4s
63; CHECK-NEXT:    ret
64  %a = icmp eq <4 x i32> %x, %y
65  %b = icmp sgt <4 x i32> %z, %w
66  %s = select <4 x i1> %a, <4 x i1> %b, <4 x i1> zeroinitializer
67  ret <4 x i1> %s
68}
69
70define <4 x i1> @or_vec(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32> %w) {
71; CHECK-LABEL: or_vec:
72; CHECK:       // %bb.0:
73; CHECK-NEXT:    cmgt v2.4s, v2.4s, v3.4s
74; CHECK-NEXT:    cmeq v0.4s, v0.4s, v1.4s
75; CHECK-NEXT:    orr v0.16b, v0.16b, v2.16b
76; CHECK-NEXT:    xtn v0.4h, v0.4s
77; CHECK-NEXT:    ret
78  %a = icmp eq <4 x i32> %x, %y
79  %b = icmp sgt <4 x i32> %z, %w
80  %s = select <4 x i1> %a, <4 x i1> <i1 1, i1 1, i1 1, i1 1>, <4 x i1> %b
81  ret <4 x i1> %s
82}
83
84define <4 x i1> @and_not_vec(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32> %w) {
85; CHECK-LABEL: and_not_vec:
86; CHECK:       // %bb.0:
87; CHECK-NEXT:    cmgt v2.4s, v2.4s, v3.4s
88; CHECK-NEXT:    cmeq v0.4s, v0.4s, v1.4s
89; CHECK-NEXT:    bic v0.16b, v2.16b, v0.16b
90; CHECK-NEXT:    xtn v0.4h, v0.4s
91; CHECK-NEXT:    ret
92  %a = icmp eq <4 x i32> %x, %y
93  %b = icmp sgt <4 x i32> %z, %w
94  %s = select <4 x i1> %a, <4 x i1> zeroinitializer, <4 x i1> %b
95  ret <4 x i1> %s
96}
97
98define <4 x i1> @or_not_vec(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32> %w) {
99; CHECK-LABEL: or_not_vec:
100; CHECK:       // %bb.0:
101; CHECK-NEXT:    cmgt v2.4s, v2.4s, v3.4s
102; CHECK-NEXT:    cmeq v0.4s, v0.4s, v1.4s
103; CHECK-NEXT:    orn v0.16b, v2.16b, v0.16b
104; CHECK-NEXT:    xtn v0.4h, v0.4s
105; CHECK-NEXT:    ret
106  %a = icmp eq <4 x i32> %x, %y
107  %b = icmp sgt <4 x i32> %z, %w
108  %s = select <4 x i1> %a, <4 x i1> %b, <4 x i1> <i1 1, i1 1, i1 1, i1 1>
109  ret <4 x i1> %s
110}
111
112define <4 x i1> @and_vec_undef(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32> %w) {
113; CHECK-LABEL: and_vec_undef:
114; CHECK:       // %bb.0:
115; CHECK-NEXT:    cmgt v2.4s, v2.4s, v3.4s
116; CHECK-NEXT:    cmeq v0.4s, v0.4s, v1.4s
117; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
118; CHECK-NEXT:    xtn v0.4h, v0.4s
119; CHECK-NEXT:    ret
120  %a = icmp eq <4 x i32> %x, %y
121  %b = icmp sgt <4 x i32> %z, %w
122  %s = select <4 x i1> %a, <4 x i1> %b, <4 x i1> <i1 0, i1 undef, i1 0, i1 undef>
123  ret <4 x i1> %s
124}
125
126define <4 x i1> @or_vec_undef(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32> %w) {
127; CHECK-LABEL: or_vec_undef:
128; CHECK:       // %bb.0:
129; CHECK-NEXT:    cmgt v2.4s, v2.4s, v3.4s
130; CHECK-NEXT:    cmeq v0.4s, v0.4s, v1.4s
131; CHECK-NEXT:    orr v0.16b, v0.16b, v2.16b
132; CHECK-NEXT:    xtn v0.4h, v0.4s
133; CHECK-NEXT:    ret
134  %a = icmp eq <4 x i32> %x, %y
135  %b = icmp sgt <4 x i32> %z, %w
136  %s = select <4 x i1> %a, <4 x i1> <i1 undef, i1 1, i1 1, i1 undef>, <4 x i1> %b
137  ret <4 x i1> %s
138}
139
140define <4 x i1> @and_not_vec_undef(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32> %w) {
141; CHECK-LABEL: and_not_vec_undef:
142; CHECK:       // %bb.0:
143; CHECK-NEXT:    cmgt v2.4s, v2.4s, v3.4s
144; CHECK-NEXT:    cmeq v0.4s, v0.4s, v1.4s
145; CHECK-NEXT:    bic v0.16b, v2.16b, v0.16b
146; CHECK-NEXT:    xtn v0.4h, v0.4s
147; CHECK-NEXT:    ret
148  %a = icmp eq <4 x i32> %x, %y
149  %b = icmp sgt <4 x i32> %z, %w
150  %s = select <4 x i1> %a, <4 x i1> <i1 0, i1 0, i1 undef, i1 0>, <4 x i1> %b
151  ret <4 x i1> %s
152}
153
154define <4 x i1> @or_not_vec_undef(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32> %w) {
155; CHECK-LABEL: or_not_vec_undef:
156; CHECK:       // %bb.0:
157; CHECK-NEXT:    cmgt v2.4s, v2.4s, v3.4s
158; CHECK-NEXT:    cmeq v0.4s, v0.4s, v1.4s
159; CHECK-NEXT:    orn v0.16b, v2.16b, v0.16b
160; CHECK-NEXT:    xtn v0.4h, v0.4s
161; CHECK-NEXT:    ret
162  %a = icmp eq <4 x i32> %x, %y
163  %b = icmp sgt <4 x i32> %z, %w
164  %s = select <4 x i1> %a, <4 x i1> %b, <4 x i1> <i1 1, i1 undef, i1 1, i1 1>
165  ret <4 x i1> %s
166}
167