xref: /llvm-project/llvm/test/CodeGen/AArch64/select-to-and-zext.ll (revision de7881ebf5e112f978940cbff5582c19fab90eb1) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-none-elf -verify-machineinstrs %s -o - | FileCheck %s
3
4define i32 @from_cmpeq(i32 %xx, i32 %y) {
5; CHECK-LABEL: from_cmpeq:
6; CHECK:       // %bb.0:
7; CHECK-NEXT:    and w8, w1, #0x1
8; CHECK-NEXT:    cmp w0, #9
9; CHECK-NEXT:    csel w0, w8, wzr, eq
10; CHECK-NEXT:    ret
11  %x = icmp eq i32 %xx, 9
12  %masked = and i32 %y, 1
13
14  %r = select i1 %x, i32 %masked, i32 0
15  ret i32 %r
16}
17
18define i32 @from_cmpeq_fail_bad_andmask(i32 %xx, i32 %y) {
19; CHECK-LABEL: from_cmpeq_fail_bad_andmask:
20; CHECK:       // %bb.0:
21; CHECK-NEXT:    and w8, w1, #0x3
22; CHECK-NEXT:    cmp w0, #9
23; CHECK-NEXT:    csel w0, w8, wzr, eq
24; CHECK-NEXT:    ret
25  %x = icmp eq i32 %xx, 9
26  %masked = and i32 %y, 3
27  %r = select i1 %x, i32 %masked, i32 0
28  ret i32 %r
29}
30
31define i32 @from_i1(i1 %x, i32 %y) {
32; CHECK-LABEL: from_i1:
33; CHECK:       // %bb.0:
34; CHECK-NEXT:    and w8, w0, w1
35; CHECK-NEXT:    and w0, w8, #0x1
36; CHECK-NEXT:    ret
37  %masked = and i32 %y, 1
38  %r = select i1 %x, i32 %masked, i32 0
39  ret i32 %r
40}
41
42define i32 @from_trunc_i8(i8 %xx, i32 %y) {
43; CHECK-LABEL: from_trunc_i8:
44; CHECK:       // %bb.0:
45; CHECK-NEXT:    and w8, w0, w1
46; CHECK-NEXT:    and w0, w8, #0x1
47; CHECK-NEXT:    ret
48  %masked = and i32 %y, 1
49  %x = trunc i8 %xx to i1
50  %r = select i1 %x, i32 %masked, i32 0
51  ret i32 %r
52}
53
54define i32 @from_trunc_i64(i64 %xx, i32 %y) {
55; CHECK-LABEL: from_trunc_i64:
56; CHECK:       // %bb.0:
57; CHECK-NEXT:    and w8, w0, w1
58; CHECK-NEXT:    and w0, w8, #0x1
59; CHECK-NEXT:    ret
60  %masked = and i32 %y, 1
61  %x = trunc i64 %xx to i1
62  %r = select i1 %x, i32 %masked, i32 0
63  ret i32 %r
64}
65
66define i32 @from_i1_fail_bad_select0(i1 %x, i32 %y) {
67; CHECK-LABEL: from_i1_fail_bad_select0:
68; CHECK:       // %bb.0:
69; CHECK-NEXT:    and w8, w1, #0x1
70; CHECK-NEXT:    tst w0, #0x1
71; CHECK-NEXT:    csinc w0, w8, wzr, ne
72; CHECK-NEXT:    ret
73  %masked = and i32 %y, 1
74  %r = select i1 %x, i32 %masked, i32 1
75  ret i32 %r
76}
77
78define i32 @from_i1_fail_bad_select1(i1 %x, i32 %y) {
79; CHECK-LABEL: from_i1_fail_bad_select1:
80; CHECK:       // %bb.0:
81; CHECK-NEXT:    and w8, w1, #0x1
82; CHECK-NEXT:    tst w0, #0x1
83; CHECK-NEXT:    csel w0, wzr, w8, ne
84; CHECK-NEXT:    ret
85  %masked = and i32 %y, 1
86  %r = select i1 %x, i32 0, i32 %masked
87  ret i32 %r
88}
89