1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 2; RUN: llc -mtriple=aarch64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD 3; RUN: llc -mtriple=aarch64 -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI 4 5define i8 @scmp.8.8(i8 %x, i8 %y) nounwind { 6; CHECK-SD-LABEL: scmp.8.8: 7; CHECK-SD: // %bb.0: 8; CHECK-SD-NEXT: sxtb w8, w0 9; CHECK-SD-NEXT: cmp w8, w1, sxtb 10; CHECK-SD-NEXT: cset w8, gt 11; CHECK-SD-NEXT: csinv w0, w8, wzr, ge 12; CHECK-SD-NEXT: ret 13; 14; CHECK-GI-LABEL: scmp.8.8: 15; CHECK-GI: // %bb.0: 16; CHECK-GI-NEXT: sxtb w8, w0 17; CHECK-GI-NEXT: sxtb w9, w1 18; CHECK-GI-NEXT: cmp w8, w9 19; CHECK-GI-NEXT: cset w8, gt 20; CHECK-GI-NEXT: csinv w0, w8, wzr, ge 21; CHECK-GI-NEXT: ret 22 %1 = call i8 @llvm.scmp(i8 %x, i8 %y) 23 ret i8 %1 24} 25 26define i8 @scmp.8.16(i16 %x, i16 %y) nounwind { 27; CHECK-SD-LABEL: scmp.8.16: 28; CHECK-SD: // %bb.0: 29; CHECK-SD-NEXT: sxth w8, w0 30; CHECK-SD-NEXT: cmp w8, w1, sxth 31; CHECK-SD-NEXT: cset w8, gt 32; CHECK-SD-NEXT: csinv w0, w8, wzr, ge 33; CHECK-SD-NEXT: ret 34; 35; CHECK-GI-LABEL: scmp.8.16: 36; CHECK-GI: // %bb.0: 37; CHECK-GI-NEXT: sxth w8, w0 38; CHECK-GI-NEXT: sxth w9, w1 39; CHECK-GI-NEXT: cmp w8, w9 40; CHECK-GI-NEXT: cset w8, gt 41; CHECK-GI-NEXT: csinv w0, w8, wzr, ge 42; CHECK-GI-NEXT: ret 43 %1 = call i8 @llvm.scmp(i16 %x, i16 %y) 44 ret i8 %1 45} 46 47define i8 @scmp.8.32(i32 %x, i32 %y) nounwind { 48; CHECK-LABEL: scmp.8.32: 49; CHECK: // %bb.0: 50; CHECK-NEXT: cmp w0, w1 51; CHECK-NEXT: cset w8, gt 52; CHECK-NEXT: csinv w0, w8, wzr, ge 53; CHECK-NEXT: ret 54 %1 = call i8 @llvm.scmp(i32 %x, i32 %y) 55 ret i8 %1 56} 57 58define i8 @scmp.8.64(i64 %x, i64 %y) nounwind { 59; CHECK-LABEL: scmp.8.64: 60; CHECK: // %bb.0: 61; CHECK-NEXT: cmp x0, x1 62; CHECK-NEXT: cset w8, gt 63; CHECK-NEXT: csinv w0, w8, wzr, ge 64; CHECK-NEXT: ret 65 %1 = call i8 @llvm.scmp(i64 %x, i64 %y) 66 ret i8 %1 67} 68 69define i8 @scmp.8.128(i128 %x, i128 %y) nounwind { 70; CHECK-SD-LABEL: scmp.8.128: 71; CHECK-SD: // %bb.0: 72; CHECK-SD-NEXT: cmp x2, x0 73; CHECK-SD-NEXT: sbcs xzr, x3, x1 74; CHECK-SD-NEXT: cset w8, lt 75; CHECK-SD-NEXT: cmp x0, x2 76; CHECK-SD-NEXT: sbcs xzr, x1, x3 77; CHECK-SD-NEXT: csinv w0, w8, wzr, ge 78; CHECK-SD-NEXT: ret 79; 80; CHECK-GI-LABEL: scmp.8.128: 81; CHECK-GI: // %bb.0: 82; CHECK-GI-NEXT: cmp x0, x2 83; CHECK-GI-NEXT: cset w8, hi 84; CHECK-GI-NEXT: cmp x1, x3 85; CHECK-GI-NEXT: cset w9, gt 86; CHECK-GI-NEXT: csel w8, w8, w9, eq 87; CHECK-GI-NEXT: cmp x0, x2 88; CHECK-GI-NEXT: cset w9, lo 89; CHECK-GI-NEXT: cmp x1, x3 90; CHECK-GI-NEXT: cset w10, lt 91; CHECK-GI-NEXT: csel w9, w9, w10, eq 92; CHECK-GI-NEXT: tst w8, #0x1 93; CHECK-GI-NEXT: cset w8, ne 94; CHECK-GI-NEXT: tst w9, #0x1 95; CHECK-GI-NEXT: csinv w0, w8, wzr, eq 96; CHECK-GI-NEXT: ret 97 %1 = call i8 @llvm.scmp(i128 %x, i128 %y) 98 ret i8 %1 99} 100 101define i32 @scmp.32.32(i32 %x, i32 %y) nounwind { 102; CHECK-LABEL: scmp.32.32: 103; CHECK: // %bb.0: 104; CHECK-NEXT: cmp w0, w1 105; CHECK-NEXT: cset w8, gt 106; CHECK-NEXT: csinv w0, w8, wzr, ge 107; CHECK-NEXT: ret 108 %1 = call i32 @llvm.scmp(i32 %x, i32 %y) 109 ret i32 %1 110} 111 112define i32 @scmp.32.64(i64 %x, i64 %y) nounwind { 113; CHECK-LABEL: scmp.32.64: 114; CHECK: // %bb.0: 115; CHECK-NEXT: cmp x0, x1 116; CHECK-NEXT: cset w8, gt 117; CHECK-NEXT: csinv w0, w8, wzr, ge 118; CHECK-NEXT: ret 119 %1 = call i32 @llvm.scmp(i64 %x, i64 %y) 120 ret i32 %1 121} 122 123define i64 @scmp.64.64(i64 %x, i64 %y) nounwind { 124; CHECK-LABEL: scmp.64.64: 125; CHECK: // %bb.0: 126; CHECK-NEXT: cmp x0, x1 127; CHECK-NEXT: cset x8, gt 128; CHECK-NEXT: csinv x0, x8, xzr, ge 129; CHECK-NEXT: ret 130 %1 = call i64 @llvm.scmp(i64 %x, i64 %y) 131 ret i64 %1 132} 133 134define <8 x i8> @s_v8i8(<8 x i8> %a, <8 x i8> %b) { 135; CHECK-LABEL: s_v8i8: 136; CHECK: // %bb.0: // %entry 137; CHECK-NEXT: cmgt v2.8b, v0.8b, v1.8b 138; CHECK-NEXT: cmgt v0.8b, v1.8b, v0.8b 139; CHECK-NEXT: sub v0.8b, v0.8b, v2.8b 140; CHECK-NEXT: ret 141entry: 142 %c = call <8 x i8> @llvm.scmp(<8 x i8> %a, <8 x i8> %b) 143 ret <8 x i8> %c 144} 145 146define <16 x i8> @s_v16i8(<16 x i8> %a, <16 x i8> %b) { 147; CHECK-LABEL: s_v16i8: 148; CHECK: // %bb.0: // %entry 149; CHECK-NEXT: cmgt v2.16b, v0.16b, v1.16b 150; CHECK-NEXT: cmgt v0.16b, v1.16b, v0.16b 151; CHECK-NEXT: sub v0.16b, v0.16b, v2.16b 152; CHECK-NEXT: ret 153entry: 154 %c = call <16 x i8> @llvm.scmp(<16 x i8> %a, <16 x i8> %b) 155 ret <16 x i8> %c 156} 157 158define <4 x i16> @s_v4i16(<4 x i16> %a, <4 x i16> %b) { 159; CHECK-LABEL: s_v4i16: 160; CHECK: // %bb.0: // %entry 161; CHECK-NEXT: cmgt v2.4h, v0.4h, v1.4h 162; CHECK-NEXT: cmgt v0.4h, v1.4h, v0.4h 163; CHECK-NEXT: sub v0.4h, v0.4h, v2.4h 164; CHECK-NEXT: ret 165entry: 166 %c = call <4 x i16> @llvm.scmp(<4 x i16> %a, <4 x i16> %b) 167 ret <4 x i16> %c 168} 169 170define <8 x i16> @s_v8i16(<8 x i16> %a, <8 x i16> %b) { 171; CHECK-LABEL: s_v8i16: 172; CHECK: // %bb.0: // %entry 173; CHECK-NEXT: cmgt v2.8h, v0.8h, v1.8h 174; CHECK-NEXT: cmgt v0.8h, v1.8h, v0.8h 175; CHECK-NEXT: sub v0.8h, v0.8h, v2.8h 176; CHECK-NEXT: ret 177entry: 178 %c = call <8 x i16> @llvm.scmp(<8 x i16> %a, <8 x i16> %b) 179 ret <8 x i16> %c 180} 181 182define <16 x i16> @s_v16i16(<16 x i16> %a, <16 x i16> %b) { 183; CHECK-SD-LABEL: s_v16i16: 184; CHECK-SD: // %bb.0: // %entry 185; CHECK-SD-NEXT: cmgt v4.8h, v1.8h, v3.8h 186; CHECK-SD-NEXT: cmgt v5.8h, v0.8h, v2.8h 187; CHECK-SD-NEXT: cmgt v0.8h, v2.8h, v0.8h 188; CHECK-SD-NEXT: cmgt v1.8h, v3.8h, v1.8h 189; CHECK-SD-NEXT: sub v0.8h, v0.8h, v5.8h 190; CHECK-SD-NEXT: sub v1.8h, v1.8h, v4.8h 191; CHECK-SD-NEXT: ret 192; 193; CHECK-GI-LABEL: s_v16i16: 194; CHECK-GI: // %bb.0: // %entry 195; CHECK-GI-NEXT: cmgt v4.8h, v0.8h, v2.8h 196; CHECK-GI-NEXT: cmgt v5.8h, v1.8h, v3.8h 197; CHECK-GI-NEXT: cmgt v0.8h, v2.8h, v0.8h 198; CHECK-GI-NEXT: cmgt v1.8h, v3.8h, v1.8h 199; CHECK-GI-NEXT: sub v0.8h, v0.8h, v4.8h 200; CHECK-GI-NEXT: sub v1.8h, v1.8h, v5.8h 201; CHECK-GI-NEXT: ret 202entry: 203 %c = call <16 x i16> @llvm.scmp(<16 x i16> %a, <16 x i16> %b) 204 ret <16 x i16> %c 205} 206 207define <2 x i32> @s_v2i32(<2 x i32> %a, <2 x i32> %b) { 208; CHECK-LABEL: s_v2i32: 209; CHECK: // %bb.0: // %entry 210; CHECK-NEXT: cmgt v2.2s, v0.2s, v1.2s 211; CHECK-NEXT: cmgt v0.2s, v1.2s, v0.2s 212; CHECK-NEXT: sub v0.2s, v0.2s, v2.2s 213; CHECK-NEXT: ret 214entry: 215 %c = call <2 x i32> @llvm.scmp(<2 x i32> %a, <2 x i32> %b) 216 ret <2 x i32> %c 217} 218 219define <4 x i32> @s_v4i32(<4 x i32> %a, <4 x i32> %b) { 220; CHECK-LABEL: s_v4i32: 221; CHECK: // %bb.0: // %entry 222; CHECK-NEXT: cmgt v2.4s, v0.4s, v1.4s 223; CHECK-NEXT: cmgt v0.4s, v1.4s, v0.4s 224; CHECK-NEXT: sub v0.4s, v0.4s, v2.4s 225; CHECK-NEXT: ret 226entry: 227 %c = call <4 x i32> @llvm.scmp(<4 x i32> %a, <4 x i32> %b) 228 ret <4 x i32> %c 229} 230 231define <8 x i32> @s_v8i32(<8 x i32> %a, <8 x i32> %b) { 232; CHECK-SD-LABEL: s_v8i32: 233; CHECK-SD: // %bb.0: // %entry 234; CHECK-SD-NEXT: cmgt v4.4s, v1.4s, v3.4s 235; CHECK-SD-NEXT: cmgt v5.4s, v0.4s, v2.4s 236; CHECK-SD-NEXT: cmgt v0.4s, v2.4s, v0.4s 237; CHECK-SD-NEXT: cmgt v1.4s, v3.4s, v1.4s 238; CHECK-SD-NEXT: sub v0.4s, v0.4s, v5.4s 239; CHECK-SD-NEXT: sub v1.4s, v1.4s, v4.4s 240; CHECK-SD-NEXT: ret 241; 242; CHECK-GI-LABEL: s_v8i32: 243; CHECK-GI: // %bb.0: // %entry 244; CHECK-GI-NEXT: cmgt v4.4s, v0.4s, v2.4s 245; CHECK-GI-NEXT: cmgt v5.4s, v1.4s, v3.4s 246; CHECK-GI-NEXT: cmgt v0.4s, v2.4s, v0.4s 247; CHECK-GI-NEXT: cmgt v1.4s, v3.4s, v1.4s 248; CHECK-GI-NEXT: sub v0.4s, v0.4s, v4.4s 249; CHECK-GI-NEXT: sub v1.4s, v1.4s, v5.4s 250; CHECK-GI-NEXT: ret 251entry: 252 %c = call <8 x i32> @llvm.scmp(<8 x i32> %a, <8 x i32> %b) 253 ret <8 x i32> %c 254} 255 256define <2 x i64> @s_v2i64(<2 x i64> %a, <2 x i64> %b) { 257; CHECK-LABEL: s_v2i64: 258; CHECK: // %bb.0: // %entry 259; CHECK-NEXT: cmgt v2.2d, v0.2d, v1.2d 260; CHECK-NEXT: cmgt v0.2d, v1.2d, v0.2d 261; CHECK-NEXT: sub v0.2d, v0.2d, v2.2d 262; CHECK-NEXT: ret 263entry: 264 %c = call <2 x i64> @llvm.scmp(<2 x i64> %a, <2 x i64> %b) 265 ret <2 x i64> %c 266} 267 268define <4 x i64> @s_v4i64(<4 x i64> %a, <4 x i64> %b) { 269; CHECK-SD-LABEL: s_v4i64: 270; CHECK-SD: // %bb.0: // %entry 271; CHECK-SD-NEXT: cmgt v4.2d, v1.2d, v3.2d 272; CHECK-SD-NEXT: cmgt v5.2d, v0.2d, v2.2d 273; CHECK-SD-NEXT: cmgt v0.2d, v2.2d, v0.2d 274; CHECK-SD-NEXT: cmgt v1.2d, v3.2d, v1.2d 275; CHECK-SD-NEXT: sub v0.2d, v0.2d, v5.2d 276; CHECK-SD-NEXT: sub v1.2d, v1.2d, v4.2d 277; CHECK-SD-NEXT: ret 278; 279; CHECK-GI-LABEL: s_v4i64: 280; CHECK-GI: // %bb.0: // %entry 281; CHECK-GI-NEXT: cmgt v4.2d, v0.2d, v2.2d 282; CHECK-GI-NEXT: cmgt v5.2d, v1.2d, v3.2d 283; CHECK-GI-NEXT: cmgt v0.2d, v2.2d, v0.2d 284; CHECK-GI-NEXT: cmgt v1.2d, v3.2d, v1.2d 285; CHECK-GI-NEXT: sub v0.2d, v0.2d, v4.2d 286; CHECK-GI-NEXT: sub v1.2d, v1.2d, v5.2d 287; CHECK-GI-NEXT: ret 288entry: 289 %c = call <4 x i64> @llvm.scmp(<4 x i64> %a, <4 x i64> %b) 290 ret <4 x i64> %c 291} 292 293define <16 x i8> @signOf_neon_scmp(<8 x i16> %s0_lo, <8 x i16> %s0_hi, <8 x i16> %s1_lo, <8 x i16> %s1_hi) { 294; CHECK-SD-LABEL: signOf_neon_scmp: 295; CHECK-SD: // %bb.0: // %entry 296; CHECK-SD-NEXT: cmgt v4.8h, v1.8h, v3.8h 297; CHECK-SD-NEXT: cmgt v1.8h, v3.8h, v1.8h 298; CHECK-SD-NEXT: cmgt v3.8h, v0.8h, v2.8h 299; CHECK-SD-NEXT: cmgt v0.8h, v2.8h, v0.8h 300; CHECK-SD-NEXT: sub v1.8h, v1.8h, v4.8h 301; CHECK-SD-NEXT: sub v0.8h, v0.8h, v3.8h 302; CHECK-SD-NEXT: uzp1 v0.16b, v0.16b, v1.16b 303; CHECK-SD-NEXT: ret 304; 305; CHECK-GI-LABEL: signOf_neon_scmp: 306; CHECK-GI: // %bb.0: // %entry 307; CHECK-GI-NEXT: cmgt v4.8h, v0.8h, v2.8h 308; CHECK-GI-NEXT: cmgt v5.8h, v1.8h, v3.8h 309; CHECK-GI-NEXT: cmgt v0.8h, v2.8h, v0.8h 310; CHECK-GI-NEXT: cmgt v1.8h, v3.8h, v1.8h 311; CHECK-GI-NEXT: uzp1 v0.16b, v0.16b, v1.16b 312; CHECK-GI-NEXT: uzp1 v1.16b, v4.16b, v5.16b 313; CHECK-GI-NEXT: shl v0.16b, v0.16b, #7 314; CHECK-GI-NEXT: shl v1.16b, v1.16b, #7 315; CHECK-GI-NEXT: sshr v0.16b, v0.16b, #7 316; CHECK-GI-NEXT: sshr v1.16b, v1.16b, #7 317; CHECK-GI-NEXT: sub v0.16b, v0.16b, v1.16b 318; CHECK-GI-NEXT: ret 319entry: 320 %0 = shufflevector <8 x i16> %s0_lo, <8 x i16> %s0_hi, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 321 %1 = shufflevector <8 x i16> %s1_lo, <8 x i16> %s1_hi, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 322 %or.i = tail call <16 x i8> @llvm.scmp.v16i8.v16i16(<16 x i16> %0, <16 x i16> %1) 323 ret <16 x i8> %or.i 324} 325